mirror of https://github.com/efabless/caravel.git
9.6 KiB
9.6 KiB
| 1 | Metric | Value |
|---|---|---|
| 2 | timing__setup__ws__corner:nom_tt_025C_1v80 | 1.624232 |
| 3 | timing__hold__ws__corner:nom_tt_025C_1v80 | 0.274621 |
| 4 | design__instance__area | 3221.84 |
| 5 | design__instance__count | 520 |
| 6 | design__instance__total_power | 1.3465 |
| 7 | design__die__bbox | 0.0 0.0 100.0 75.0 |
| 8 | design__core__bbox | 5.52 5.44 94.3 68.0 |
| 9 | design__io | 39 |
| 10 | design__die__area | 7500 |
| 11 | design__core__area | 5554.08 |
| 12 | design__instance__count__stdcell | 520 |
| 13 | design__instance__area__stdcell | 3221.84 |
| 14 | design__instance__count__macros | 0 |
| 15 | design__instance__area__macros | 0 |
| 16 | design__instance__utilization | 0.580086 |
| 17 | design__instance__utilization__stdcell | 0.580086 |
| 18 | design__instance__count__setup_buffer | 0 |
| 19 | design__instance__count__hold_buffer | 0 |
| 20 | design__instance__displacement__total | 0 |
| 21 | design__instance__displacement__mean | 0 |
| 22 | design__instance__displacement__max | 0 |
| 23 | route__wirelength__estimated | 6909.71 |
| 24 | design__violations | 0 |
| 25 | antenna__violating__nets | 0 |
| 26 | antenna__violating__pins | 0 |
| 27 | antenna__count | 0 |
| 28 | route__net | 394 |
| 29 | route__net__special | 2 |
| 30 | route__drc_errors__iter:1 | 168 |
| 31 | route__wirelength__iter:1 | 7682 |
| 32 | route__drc_errors__iter:2 | 55 |
| 33 | route__wirelength__iter:2 | 7648 |
| 34 | route__drc_errors__iter:3 | 123 |
| 35 | route__wirelength__iter:3 | 7652 |
| 36 | route__drc_errors__iter:4 | 1 |
| 37 | route__wirelength__iter:4 | 7689 |
| 38 | route__drc_errors__iter:5 | 0 |
| 39 | route__wirelength__iter:5 | 7689 |
| 40 | route__drc_errors | 0 |
| 41 | route__wirelength | 7689 |
| 42 | route__vias | 2382 |
| 43 | route__vias__singlecut | 2382 |
| 44 | route__vias__multicut | 0 |
| 45 | design__disconnected_pins__count | 0 |
| 46 | route__wirelength__max | 252.91 |
| 47 | design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 |
| 48 | design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 |
| 49 | design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 |
| 50 | power__internal__total | 0.0006281010573729873 |
| 51 | power__switching__total | 0.0010574385523796082 |
| 52 | power__leakage__total | 3.840616269457087e-09 |
| 53 | power__total | 0.0016855434514582157 |
| 54 | clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.026419 |
| 55 | clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.026648 |
| 56 | timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0 |
| 57 | timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0 |
| 58 | timing__hold__wns__corner:nom_tt_025C_1v80 | 0.0 |
| 59 | timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0 |
| 60 | timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 |
| 61 | timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 |
| 62 | timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 |
| 63 | timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 |
| 64 | design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 |
| 65 | design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 |
| 66 | design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 |
| 67 | clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.026351 |
| 68 | clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.026574 |
| 69 | timing__hold__ws__corner:nom_ss_100C_1v60 | 0.67865 |
| 70 | timing__setup__ws__corner:nom_ss_100C_1v60 | -2.045736 |
| 71 | timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0 |
| 72 | timing__setup__tns__corner:nom_ss_100C_1v60 | -9.303928 |
| 73 | timing__hold__wns__corner:nom_ss_100C_1v60 | 0.0 |
| 74 | timing__setup__wns__corner:nom_ss_100C_1v60 | -2.045736 |
| 75 | timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 |
| 76 | timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 |
| 77 | timing__setup_vio__count__corner:nom_ss_100C_1v60 | 8 |
| 78 | timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 7 |
| 79 | design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 |
| 80 | design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 |
| 81 | design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 |
| 82 | clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.026447 |
| 83 | clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.026678 |
| 84 | timing__hold__ws__corner:nom_ff_n40C_1v95 | 0.139551 |
| 85 | timing__setup__ws__corner:nom_ff_n40C_1v95 | 2.729408 |
| 86 | timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0 |
| 87 | timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0 |
| 88 | timing__hold__wns__corner:nom_ff_n40C_1v95 | 0.0 |
| 89 | timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0 |
| 90 | timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 |
| 91 | timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 |
| 92 | timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 |
| 93 | timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 |
| 94 | design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 |
| 95 | design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 |
| 96 | design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 |
| 97 | clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.019092 |
| 98 | clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.019238 |
| 99 | timing__hold__ws__corner:min_tt_025C_1v80 | 0.274164 |
| 100 | timing__setup__ws__corner:min_tt_025C_1v80 | 1.663321 |
| 101 | timing__hold__tns__corner:min_tt_025C_1v80 | 0.0 |
| 102 | timing__setup__tns__corner:min_tt_025C_1v80 | 0.0 |
| 103 | timing__hold__wns__corner:min_tt_025C_1v80 | 0.0 |
| 104 | timing__setup__wns__corner:min_tt_025C_1v80 | 0.0 |
| 105 | timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 |
| 106 | timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 |
| 107 | timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 |
| 108 | timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 |
| 109 | design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 |
| 110 | design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 |
| 111 | design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 |
| 112 | clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.018972 |
| 113 | clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.019113 |
| 114 | timing__hold__ws__corner:min_ss_100C_1v60 | 0.67585 |
| 115 | timing__setup__ws__corner:min_ss_100C_1v60 | -1.833309 |
| 116 | timing__hold__tns__corner:min_ss_100C_1v60 | 0.0 |
| 117 | timing__setup__tns__corner:min_ss_100C_1v60 | -8.749656 |
| 118 | timing__hold__wns__corner:min_ss_100C_1v60 | 0.0 |
| 119 | timing__setup__wns__corner:min_ss_100C_1v60 | -1.833309 |
| 120 | timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 |
| 121 | timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 |
| 122 | timing__setup_vio__count__corner:min_ss_100C_1v60 | 8 |
| 123 | timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 7 |
| 124 | design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 |
| 125 | design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 |
| 126 | design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 |
| 127 | clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.01919 |
| 128 | clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.019339 |
| 129 | timing__hold__ws__corner:min_ff_n40C_1v95 | 0.139087 |
| 130 | timing__setup__ws__corner:min_ff_n40C_1v95 | 2.757252 |
| 131 | timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0 |
| 132 | timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0 |
| 133 | timing__hold__wns__corner:min_ff_n40C_1v95 | 0.0 |
| 134 | timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0 |
| 135 | timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 |
| 136 | timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 |
| 137 | timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 |
| 138 | timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 |
| 139 | design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 |
| 140 | design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 |
| 141 | design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 |
| 142 | clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.04563 |
| 143 | clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.04611 |
| 144 | timing__hold__ws__corner:max_tt_025C_1v80 | 0.273634 |
| 145 | timing__setup__ws__corner:max_tt_025C_1v80 | 1.585729 |
| 146 | timing__hold__tns__corner:max_tt_025C_1v80 | 0.0 |
| 147 | timing__setup__tns__corner:max_tt_025C_1v80 | 0.0 |
| 148 | timing__hold__wns__corner:max_tt_025C_1v80 | 0.0 |
| 149 | timing__setup__wns__corner:max_tt_025C_1v80 | 0.0 |
| 150 | timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 |
| 151 | timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 |
| 152 | timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 |
| 153 | timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 |
| 154 | design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 |
| 155 | design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 |
| 156 | design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 |
| 157 | clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.046207 |
| 158 | clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.046689 |
| 159 | timing__hold__ws__corner:max_ss_100C_1v60 | 0.680917 |
| 160 | timing__setup__ws__corner:max_ss_100C_1v60 | -2.245377 |
| 161 | timing__hold__tns__corner:max_ss_100C_1v60 | 0.0 |
| 162 | timing__setup__tns__corner:max_ss_100C_1v60 | -9.948954 |
| 163 | timing__hold__wns__corner:max_ss_100C_1v60 | 0.0 |
| 164 | timing__setup__wns__corner:max_ss_100C_1v60 | -2.245377 |
| 165 | timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 |
| 166 | timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 |
| 167 | timing__setup_vio__count__corner:max_ss_100C_1v60 | 8 |
| 168 | timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 7 |
| 169 | design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 |
| 170 | design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 |
| 171 | design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 |
| 172 | clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.044996 |
| 173 | clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.045482 |
| 174 | timing__hold__ws__corner:max_ff_n40C_1v95 | 0.139449 |
| 175 | timing__setup__ws__corner:max_ff_n40C_1v95 | 2.701741 |
| 176 | timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0 |
| 177 | timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0 |
| 178 | timing__hold__wns__corner:max_ff_n40C_1v95 | 0.0 |
| 179 | timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0 |
| 180 | timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 |
| 181 | timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 |
| 182 | timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 |
| 183 | timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 |
| 184 | design__max_slew_violation__count | 0 |
| 185 | design__max_fanout_violation__count | 18 |
| 186 | design__max_cap_violation__count | 0 |
| 187 | clock__skew__worst_hold | -0.018972 |
| 188 | clock__skew__worst_setup | 0.046689 |
| 189 | timing__hold__ws | 0.139087 |
| 190 | timing__setup__ws | -2.245377 |
| 191 | timing__hold__tns | 0.0 |
| 192 | timing__setup__tns | -28.002538 |
| 193 | timing__hold__wns | 0.0 |
| 194 | timing__setup__wns | -2.245377 |
| 195 | timing__hold_vio__count | 0 |
| 196 | timing__hold_r2r_vio__count | 0 |
| 197 | timing__setup_vio__count | 24 |
| 198 | timing__setup_r2r_vio__count | 21 |
| 199 | ir__voltage__worst | 1.8000000000000000444089209850062616169452667236328125 |
| 200 | ir__drop__avg | 0.000890999999999999973444853029747036998742260038852691650390625 |
| 201 | ir__drop__worst | 0.00120999999999999992110477631257481334614567458629608154296875 |
| 202 | design__xor_difference__count | 0 |
| 203 | magic__drc_error__count | 0 |
| 204 | magic__illegal_overlap__count | 0 |
| 205 | design__lvs_device_difference__count | 0 |
| 206 | design__lvs_net_differences__count | 0 |
| 207 | design__lvs_property_fails__count | 0 |
| 208 | design__lvs_errors__count | 0 |
| 209 | design__lvs_unmatched_devices__count | 0 |
| 210 | design__lvs_unmatched_nets__count | 0 |
| 211 | design__lvs_unmatched_pins__count | 0 |