7 Commits

Author	SHA1	Message	Date
kareem	e5d9788a43	reharden!: digital_pll ... ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched	2022-10-17 10:56:01 -07:00
kareem	d5379ab6f9	fix power pins assignment of clockp buffers again	2022-10-13 11:02:35 -07:00
kareem	fdf1f11ece	fix power pins assignment of clockp buffers	2022-10-13 11:00:04 -07:00
kareem	59743f4832	change buf16 to clkbuf16 and reimplement	2022-10-13 06:54:55 -07:00
kareem	bb2d983e03	+ add a size 16 buf for clockp signal in digital_pll	2022-10-13 05:57:09 -07:00
jeffdi	619163aec1	fixes for RTL testbenches with mgmt core wrapper	2021-12-05 10:11:10 -08:00
Tim Edwards	332f9ec2e7	Seeding with documentation of pinout and verilog RTL (mostly unchanged ... from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).	2021-10-12 16:31:42 -04:00