5 Commits

Author	SHA1	Message	Date
M0stafaRady	e8870d6a8b	fix errors for gate level	2022-10-12 10:29:56 -07:00
M0stafaRady	688429eeda	move caravel.py, cpu.py ... to interfaces directory	2022-10-10 04:50:45 -07:00
M0stafaRady	5e523bce5b	Add spi master temp created to simulate the silicon validation test and to be removed after	2022-10-04 10:46:34 -07:00
M0stafaRady	11330823b7	Add hk_regs_wr_wb_cpu test	2022-10-04 03:24:15 -07:00
M0stafaRady	79f26f6b38	add new test spi_master_rd	2022-10-03 05:36:36 -07:00