Commit Graph

113 Commits

Author SHA1 Message Date
Tim Edwards 787f1c3dae Added back wishbone verification tests, specifically those related
to areas not part of the management SoC, including chip_io,
mgmt_protect, and mprj_ctrl and sysctrl_wb (which are now part of
housekeeping).  The two housekeeping tests fail and need to be
debugged.
2021-10-28 17:26:06 -04:00
Tim Edwards 11165bfe3d Added entries in defs.h for the new input enable lines from the
management SoC to the management protect block, and updated the
documentation to include the new wishbone interface for those
signals, and the additional signals on the management SoC pinout.
2021-10-28 10:13:14 -04:00
Tim Edwards bc9944ce20 Updated the caravan netlist and implemented the caravan testbench. 2021-10-25 15:08:13 -04:00
Tim Edwards e474dbbc99 Corrected the last testbenches, added a new testbench for the spi_master
since the original one was folded into the sysctrl testbench, but that
testbench no longer uses the SPI master.  Moved the SPI master from being
an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35.
Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable
from the SPI master can be used.
2021-10-21 19:48:24 -04:00
Tim Edwards 43ced83bd8 Correction to the mprj_bitbang testbench to run the test without running
into issues of contention between the SPI and wishbone interfaces.  The
testbench now passes, although the contention isn't handled particularly
well.
2021-10-21 10:57:20 -04:00
Tim Edwards 000a5266ef Corrected an error in the bitbang testbench (but it does not cause the
testbench to pass).
2021-10-19 23:10:51 -04:00
Tim Edwards 184f4a637c Added the rest of the testbenches: mprj_bitbang, perf, pll, qspi, and
storage.  Not all of these pass simulation checks.  Added back the
bit-bang control of the GPIO programming.  Added back the read-only
interface between the housekeeping module and the SRAM 2nd port.
Revised the memory map text document to reflect the addition of the
SRAM ports.  There is not yet a testbench for the SRAM read-only
interface.
2021-10-19 19:05:47 -04:00
Tim Edwards 767342e183 Added a completely revised sysctrl testbench based on accessing the
housekeeping SPI through the back-door wishbone interface.  Checks
most of the SPI registers (but could do more).
2021-10-19 17:32:20 -04:00
Tim Edwards e2f6a02688 Added and verified testbenches timer, timer2, uart, and user_pass_thru. 2021-10-18 21:53:09 -04:00
Tim Edwards 0fa2e3bb89 Added testbenches for irq, mem, mprj_ctrl, and pass_thru (note that "mem"
does not pass yet and still needs to be debugged).
2021-10-18 20:32:50 -04:00
Tim Edwards 2e57b5da08 Added and debugged two more testbenches, gpio_mgmt and hkspi. 2021-10-18 11:25:26 -04:00
Tim Edwards 842200b7ec Changed the memory map to move the 2e and 2f wishbone domains into
the 26 domain (now dedicated to the housekeeping module), with
2e0... now 261... and 2f0... now 262...  Although this is not
strictly backwards-compatible, the addresses in defs.h have been
modified so that C code remains valid with a recompile.
2021-10-16 17:58:36 -04:00
Tim Edwards bdfa747145 First major update; current code passes syntax checks in iverilog
and simulates, but fails testbench (not surprising at this stage).
2021-10-15 21:49:49 -04:00