Commit Graph

119 Commits

Author SHA1 Message Date
Tim Edwards 1e7400c0ac Removed unused definitions from user_defines.v, and added more
explanatory comments.
2021-10-25 16:36:18 -04:00
Tim Edwards 745eee1baa Created an "open frame" version of caravan (and revised the one for
caravel, since it had not been updated since a number of changes to
the caravel top level module).
2021-10-25 16:29:12 -04:00
Tim Edwards bc9944ce20 Updated the caravan netlist and implemented the caravan testbench. 2021-10-25 15:08:13 -04:00
Tim Edwards a7fec91c4c Update to the back-door wishbone access to housekeeping to better
implement the arbitration between SPI and back-door.  The back-door
access flags when it is going to do a read or write, and the SPI
can have an invalid read or fail a write if the SPI is too fast,
but the wishbone access should be valid.  As long as the SPI is
much slower than the core clock (say, 1MHz) then there should be no
contention, which means that contention can always be avoided simply
by slowing the SPI signaling down.
2021-10-24 16:58:47 -04:00
Tim Edwards e6a94449ce Modified the housekeeping SPI to generate a read strobe (or rather
status) so that between rdstb and wrstb, the SPI signals when it is
about to read or write a byte.  The back-door wishbone interface then
stalls the CPU during these periods.  That allows the CPU to continue
running while the SPI is being accessed without data collisions and
without having to stall for the entire time CSB is held low.
Because SCK is asynchronous to the clock, rare collisions are still
possible;  this is not expected to be an issue but might be worth
investigating.
2021-10-23 22:06:24 -04:00
Tim Edwards e5c90daddd Implemented a system for setting the GPIO power-on defaults through
via programming.  The values for each of the GPIOs at power-up are
defined in the "user_defines.v" file.  For the verilog, they are
applied as parameters.  For the layout, they will need to be
separately defined cells for each of the GPIOs, or at least for
each set of unique default values.
2021-10-23 17:18:30 -04:00
Tim Edwards 3ffe67e652 Changed the SRAM read-only port signal names to match the change
made to the management SoC wrapper definition---this is just
making the nomenclature better (no functional change).
2021-10-22 11:51:07 -04:00
Tim Edwards e474dbbc99 Corrected the last testbenches, added a new testbench for the spi_master
since the original one was folded into the sysctrl testbench, but that
testbench no longer uses the SPI master.  Moved the SPI master from being
an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35.
Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable
from the SPI master can be used.
2021-10-21 19:48:24 -04:00
Tim Edwards 43ced83bd8 Correction to the mprj_bitbang testbench to run the test without running
into issues of contention between the SPI and wishbone interfaces.  The
testbench now passes, although the contention isn't handled particularly
well.
2021-10-21 10:57:20 -04:00
Tim Edwards 184f4a637c Added the rest of the testbenches: mprj_bitbang, perf, pll, qspi, and
storage.  Not all of these pass simulation checks.  Added back the
bit-bang control of the GPIO programming.  Added back the read-only
interface between the housekeeping module and the SRAM 2nd port.
Revised the memory map text document to reflect the addition of the
SRAM ports.  There is not yet a testbench for the SRAM read-only
interface.
2021-10-19 19:05:47 -04:00
Tim Edwards 767342e183 Added a completely revised sysctrl testbench based on accessing the
housekeeping SPI through the back-door wishbone interface.  Checks
most of the SPI registers (but could do more).
2021-10-19 17:32:20 -04:00
Tim Edwards 0fa2e3bb89 Added testbenches for irq, mem, mprj_ctrl, and pass_thru (note that "mem"
does not pass yet and still needs to be debugged).
2021-10-18 20:32:50 -04:00
Tim Edwards 2e57b5da08 Added and debugged two more testbenches, gpio_mgmt and hkspi. 2021-10-18 11:25:26 -04:00
Tim Edwards 33ca4e11ef Additional corrections, mostly to the housekeeping module. The
top-level simulation now passes the GPIO testbench.
2021-10-17 21:38:40 -04:00
Tim Edwards 1863a7c529 A number of small corrections. 2021-10-16 23:55:57 -04:00
Tim Edwards 842200b7ec Changed the memory map to move the 2e and 2f wishbone domains into
the 26 domain (now dedicated to the housekeeping module), with
2e0... now 261... and 2f0... now 262...  Although this is not
strictly backwards-compatible, the addresses in defs.h have been
modified so that C code remains valid with a recompile.
2021-10-16 17:58:36 -04:00
Tim Edwards 2f74fa83ee Reinstated the logic analyzer as a standard interface for the
management SoC.
2021-10-16 17:42:24 -04:00
Tim Edwards bdfa747145 First major update; current code passes syntax checks in iverilog
and simulates, but fails testbench (not surprising at this stage).
2021-10-15 21:49:49 -04:00
Tim Edwards 332f9ec2e7 Seeding with documentation of pinout and verilog RTL (mostly unchanged
from original except to remove blocks that are not supposed to be in
this repository like the processor core and the storage).
2021-10-12 16:31:42 -04:00