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1003 Commits

Author SHA1 Message Date
M0stafaRady 55eaf936b0 Cocotb - add delay at the test mgmt_gpio_bidir test 2022-10-17 04:35:29 -07:00
Marwan Abbas aae58e4609
Merge pull request #265 from efabless/caravel_redesign-top-level-with-pdn 
reharden: caravel
 2022-10-17 13:09:01 +02:00
kareefardi d00ddb536a Apply automatic changes to Manifest and README.rst 2022-10-17 11:03:16 +00:00
kareem a8794dff4b reharden: caravel 
~ reharden with updated pdn
~ add stubs for non functional blocks
 2022-10-17 03:59:28 -07:00
kareem 394546731f update caravel pdn 
~ change pr boundary to origin to (0,0)
~ sync lef and mag with gds
 2022-10-17 03:51:21 -07:00
Mohamed Shalan 6ad1461be6
Merge pull request #262 from efabless/fix_gpio_signal_buffering_syntax_err 
fix syntax error at gl/gpio_signal_buffering.v
 2022-10-17 10:07:28 +02:00
M0stafaRady de11170ab2 fix syntax error at gl/gpio_signal_buffering.v 2022-10-17 00:55:12 -07:00
Marwan Abbas a915840efe
Merge pull request #261 from efabless/caravel_redesign-top-level 
Caravel redesign top level
 2022-10-17 04:15:12 +02:00
marwaneltoukhy 2ad38fbb54 Apply automatic changes to Manifest and README.rst 2022-10-17 02:11:45 +00:00
marwaneltoukhy 2d28c973ee added views for caravel with power routing 2022-10-16 19:08:56 -07:00
marwaneltoukhy 9fe77b5dd7 Merge branch 'caravel_redesign-top-level' of github.com:efabless/caravel into caravel_redesign-top-level 2022-10-16 18:56:57 -07:00
Marwan Abbas f699e3323c fixed DRC error and connections to spare logic block 2022-10-17 03:56:34 +02:00
marwaneltoukhy 7ec1eeb010 Merge branch 'caravel_redesign' into caravel_redesign-top-level 2022-10-16 18:39:39 -07:00
Marwan Abbas 35ec52aa72
Merge pull request #260 from efabless/fix_top_buffers_again 
More changes to the GPIO buffer cell
 2022-10-17 03:35:25 +02:00
Tim Edwards 9f54b2ecec Added a gate-level version of gpio_signal_buffering derived from 
the RTL, but cleaned up for macro definitions;  this can be used
for LVS.  The decap cells were hand-edited in because there is
no way to devine them from the RTL source.
 2022-10-16 21:20:12 -04:00
RTimothyEdwards 36c6c73787 Apply automatic changes to Manifest and README.rst 2022-10-17 01:10:28 +00:00
Tim Edwards 69d353f65c Corrected the verilog and the layout for the caravan version of the 
signal buffering (verilog was missing one of the buffers, and the
layout had some of the labels at the top accidentally erased).
 2022-10-16 21:06:27 -04:00
Marwan Abbas fed2eeb4ab fixed DRC error and connected wrapper 2022-10-17 02:39:32 +02:00
marwaneltoukhy 65a49d5b1d Apply automatic changes to Manifest and README.rst 2022-10-16 23:19:00 +00:00
Marwan Abbas 37d2a9d463 connected rest of buffers to power 2022-10-17 01:15:46 +02:00
kareefardi 84d1627151 Apply automatic changes to Manifest and README.rst 2022-10-16 22:48:34 +00:00
kareem 736e58186e Merge branch 'caravel_redesign-top-level' of github.com:efabless/caravel into caravel_redesign-top-level 2022-10-16 15:45:57 -07:00
kareem 2409207178 reharden: caravel 
~ add non functional blocks - like caravel_motto
 2022-10-16 15:44:27 -07:00
Tim Edwards f7e2dc80a6 Made a minor correction to the layout to remove an extra unused 
buffer.  This does not affect ongoing top-level routing work, but
is needed for LVS.
 2022-10-16 17:57:14 -04:00
Passant 9251af196f update STA script to add reports to `./signoff/<design_name>/primetime-signoff/` 
update STA script to report coverage and timing summary
 2022-10-16 14:49:54 -07:00
Passant ae6356cf2b update caravel top-level power routing [wip] 2022-10-16 14:43:38 -07:00
Marwan Abbas 04a55c695f
Merge pull request #252 from efabless/fix_top_buffers_again 
Adjustments to the top level buffering cells
 2022-10-16 23:38:13 +02:00
kareem 704f19b6c7 reharden: caravel 
~ correct placement for spare_logic_block
~ add changes from buffering macro
 2022-10-16 12:56:41 -07:00
kareem 3dc3aa5e8d Merge remote-tracking branch 'origin/fix_top_buffers_again' into caravel_redesign-top-level 2022-10-16 11:42:44 -07:00
Tim Edwards 41775aedfd Changed the LEF views to restrict the pins to the route endpoints 
using the (accidentally undocumented) "-pinonly" option.
 2022-10-16 14:40:50 -04:00
kareem 7ff92e121f Merge remote-tracking branch 'origin/fix_top_buffers_again' into caravel_redesign-top-level 2022-10-16 11:18:54 -07:00
Tim Edwards 48ae31205c Another change to the pin endpoint positions to make sure that they 
have at least 0.28um spacing to the next wire.  Not sure that this
is going to solve the router errors, though.
 2022-10-16 14:15:12 -04:00
Marwan Abbas 4a7031c479
Merge pull request #258 from efabless/cocotb 
Cocotb tests and script updates
 2022-10-16 19:10:49 +02:00
Marwan Abbas 3a0e92381a
Merge pull request #257 from efabless/revert_dd482cb0994d38556c1c317ada54b36e33b0df63 
removing the unpowered buff_flash_clkrst
 2022-10-16 19:09:29 +02:00
kareem 2a3493ed65 Merge branch 'fix_top_buffers_again' into caravel_redesign-top-level 2022-10-16 10:03:54 -07:00
kareem 2c2db061c4 Merge branch 'fix_top_buffers_again' of github.com:efabless/caravel into fix_top_buffers_again 2022-10-16 10:02:38 -07:00
M0stafaRady 0542485ae9 remove file buff_flash_clkrst.nl.v 2022-10-16 09:57:54 -07:00
M0stafaRady 8526aadd4a Revert "remove unpowered netlist" 
This reverts commit dd482cb099.
 2022-10-16 09:56:24 -07:00
RTimothyEdwards b98db2dd4d Apply automatic changes to Manifest and README.rst 2022-10-16 16:53:57 +00:00
Tim Edwards c5e7c67d60 Once again. . . Rewrote the RTL verilog so that only signals 
being buffered pass through the buffer macros.  Removed the
straight-through signals from the layout, and renumbered the
vectors in the buffer cells, which no longer match the numbering
at the top level (unfortunately).
 2022-10-16 12:49:44 -04:00
kareem b9a2e697d5 Merge branch 'fix_top_buffers_again' into caravel_redesign-top-level 2022-10-16 08:00:37 -07:00
kareem e1c7fc2a15 Merge branch 'fix_top_buffers_again' of github.com:efabless/caravel into fix_top_buffers_again 2022-10-16 08:00:13 -07:00
Tim Edwards 589f351dcb Additional modification to move pins up into an uncongested area 
above housekeeping, because the upper GPIO pins are in the wrong
place relative to the new GPIO signal routing below the SoC.
Added pins for the pass-through connections.  Unconnected/
unrouted OEB pins are still not present and probably should be
removed from the RTL.
 2022-10-16 10:52:53 -04:00
kareem 38e78abfd5 Merge branch 'fix_top_buffers_again' into caravel_redesign-top-level 2022-10-16 07:24:15 -07:00
Tim Edwards 43b8f9d4fe Merge branch 'caravel_redesign' into fix_top_buffers_again 
Updating to the most recent caravel_redesign branch version.
 2022-10-16 10:05:36 -04:00
kareem aa2dfe9421 Merge branch 'fix_top_buffers_again' of github.com:efabless/caravel into fix_top_buffers_again 2022-10-16 07:01:55 -07:00
kareem fc0701003c reharden: caravel 
- based on second iteration of the buffer macro
- change config with updated placement of spare logic macros
and power routing cell
 2022-10-16 06:58:46 -07:00
Tim Edwards dcc3c56b83 Some additional corrections to the gpio_signal_buffering cells. 
Corrected one instance where a buffer had incorrectly been replaced
with a decap cell.  Moved the left-hand side in by 0.6um to clear
the chip_io connections on the left-hand side.  Corrected a small
DRC error in a route position at the bottom.
 2022-10-16 09:50:20 -04:00
kareem f5a8382395 Merge branch 'caravel_redesign' into fix_top_buffers_again 2022-10-16 05:55:23 -07:00
M0stafaRady 8aaeb5bad8 rearrange testlist to test most number of features as quickly as possible 2022-10-16 05:43:04 -07:00