10 Commits

Author	SHA1	Message	Date
kareem	e5d9788a43	reharden!: digital_pll ... ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched	2022-10-17 10:56:01 -07:00
kareem	3e3bd111c1	~ correct paths refereces in mag and maglef files from openlane	2022-10-15 04:06:07 -07:00
kareem	59743f4832	change buf16 to clkbuf16 and reimplement	2022-10-13 06:54:55 -07:00
kareem	0eed96f33f	reharden: digital_pll ... ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables	2022-10-13 06:21:08 -07:00
manarabdelaty	966b1f22bb	[DATA] Update digital_pll	2021-12-07 13:19:02 +02:00
manarabdelaty	0067bd5b7c	[DATA] Update caravel_clocking/digital_pll/housekeeping	2021-12-02 21:09:43 +02:00
Tim Edwards	f67f7b6daf	Corrected bad paths on two layouts in mag/ and most of the layouts ... in maglef/, all of which were erroneously pointing to paths in either OpenLane or the user's home directory path.	2021-11-26 20:00:47 -05:00
manarabdelaty	37a07e291b	[DATA] Update digital_pll pin placement to have it align with the HK	2021-11-19 01:28:40 +02:00
manarabdelaty	72b2c724c9	[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz	2021-11-15 15:50:43 +02:00
manarabdelaty	bee7b4ed78	Add initial config for the digital_pll	2021-11-08 13:34:59 +02:00