Commit Graph

14 Commits

Author SHA1 Message Date
kareem 59743f4832 change buf16 to clkbuf16 and reimplement 2022-10-13 06:54:55 -07:00
kareem 0eed96f33f reharden: digital_pll
~ reimplement digital_pll using updated RTL
~ changes in config to generate same PDN
~ change deprecated variables
2022-10-13 06:21:08 -07:00
Tim Edwards 1b3fe4379c Corrected the placement of the isosub layer in the layouts so that
it is exactly overlapping;  this resolves issues with LVS.  Also:
Corrected the references to the OpenLane/ path in the .mag files
by changing them to the canonical $PDKPATH reference.
2021-12-24 22:22:23 -05:00
manarabdelaty 966b1f22bb [DATA] Update digital_pll 2021-12-07 13:19:02 +02:00
manarabdelaty 0067bd5b7c [DATA] Update caravel_clocking/digital_pll/housekeeping 2021-12-02 21:09:43 +02:00
Tim Edwards e2ee74c591 Changed "simple_por" in both caravel and caravan to be an abstract
view pointing to the contents of ../gds/ so that when the assembled
chip's GDS is generated with "cif *hier write disable", the POR
will continue to have the GDS with the proper hierarchical processing.
2021-11-27 11:51:30 -05:00
Tim Edwards be98da0fe6 Added spare logic block to caravel layout and verilog GL, wired
it to the power supply, and checked top-level LVS.
2021-11-24 16:50:22 -05:00
Tim Edwards 08a2c90940 Made updates to correct LVS errors in caravan. Found one major error in the RTL
verilog for both caravel and caravan.  Hand-edited the RTL and GL netlists to
correct this;  still need to correct the layouts.  The error causes the user1
side clock, load, and reset buffers to drive the user2 side as well as the user1
side, making a huge mess of the routing.  Will route this by hand.
2021-11-22 22:35:52 -05:00
Tim Edwards 515b5a54f2 Updates for LVS. Only LVS issue remaining for caravel is how to get the
ground domains to extract independently.
2021-11-22 12:00:55 -05:00
Tim Edwards 6eb8bb54de Several more LVS corrections, including fixing a label in chip_io that
got removed from its net by a chang in the LEF view of an I/O pad, and
a lack of declaration of an array to attach to pwr_ctrl_out in the
verilog, which is valid verilog but netgen can't know the bus size
without the no-connect net being declared.  The remaining issue has to
do with separation of ground domains in the mgmt_protect block.
2021-11-21 22:58:39 -05:00
manarabdelaty 37a07e291b [DATA] Update digital_pll pin placement to have it align with the HK 2021-11-19 01:28:40 +02:00
manarabdelaty 72b2c724c9 [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 15:50:43 +02:00
manarabdelaty bee7b4ed78 Add initial config for the digital_pll 2021-11-08 13:34:59 +02:00
Tim Edwards a7148378a0 Added as many of the magic database layout files as are expected to remain
unchanged between the caravel and caravel_openframe repositories.
2021-10-26 10:27:03 -04:00