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fix power pins assignment of clockp buffers again

This commit is contained in:
kareem 2022-10-13 11:02:35 -07:00
parent 633a204cdc
commit d5379ab6f9
1 changed files with 1 additions and 1 deletions
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2
verilog/rtl/digital_pll.v
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@ -76,7 +76,7 @@ module digital_pll(
.VPWR(VPWR), .VPWR(VPWR),
.VGND(VGND), .VGND(VGND),
.VPB(VPWR), .VPB(VPWR),
.VNB(vssd), .VNB(VGND),
`endif `endif
.A(clockp_buffer_in[0]), .A(clockp_buffer_in[0]),
.X(clockp[0]) .X(clockp[0])