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caravel
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Merge branch 'main' of https://github.com/efabless/caravel_openframe into main

This commit is contained in:
manarabdelaty 2021-11-17 16:43:59 +02:00
parent 1f55f46596 5f1a0029f5
commit 979d34b7a9
1 changed files with 7 additions and 7 deletions
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14
verilog/rtl/caravan.v
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@ -665,11 +665,11 @@ module caravan (
caravel_clocking clocking( caravel_clocking clocking(
`ifdef USE_POWER_PINS `ifdef USE_POWER_PINS
.vdd1v8(VPWR), .vdd1v8(vccd_core),
.vss(VGND), .vss(vssd_core),
`endif `endif
.ext_clk_sel(ext_clk_sel), .ext_clk_sel(ext_clk_sel),
.ext_clk(clock), .ext_clk(clock_core),
.pll_clk(pll_clk), .pll_clk(pll_clk),
.pll_clk90(pll_clk90), .pll_clk90(pll_clk90),
.resetb(resetb), .resetb(resetb),
@ -685,8 +685,8 @@ module caravan (
digital_pll pll ( digital_pll pll (
`ifdef USE_POWER_PINS `ifdef USE_POWER_PINS
.VPWR(VPWR), .VPWR(vccd_core),
.VGND(VGND), .VGND(vssd_core),
`endif `endif
.resetb(resetb), .resetb(resetb),
.enable(spi_pll_ena), .enable(spi_pll_ena),
@ -701,8 +701,8 @@ module caravan (
housekeeping housekeeping ( housekeeping housekeeping (
`ifdef USE_POWER_PINS `ifdef USE_POWER_PINS
.vdd(VPWR), .vdd(vccd_core),
.vss(VGND), .vss(vssd_core),
`endif `endif
.wb_clk_i(caravel_clk), .wb_clk_i(caravel_clk),