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caravel
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Corrected the rstb_l signal in both caravan and caravel, and corrected 

the clock_core signal in caravan.
This commit is contained in:
Tim Edwards 2021-11-22 13:25:35 -05:00
parent 515b5a54f2
commit 1e14d3a4c5
2 changed files with 5 additions and 5 deletions
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6
verilog/rtl/caravan.v
View File

@ -673,7 +673,7 @@ module caravan (
.ext_clk(clock_core),
.pll_clk(pll_clk),
.pll_clk90(pll_clk90),
.resetb(resetb),
.resetb(rstb_l),
.sel(spi_pll_sel),
.sel2(spi_pll90_sel),
.ext_reset(ext_reset), // From housekeeping SPI
@ -689,9 +689,9 @@ module caravan (
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.resetb(resetb),
.resetb(rstb_l),
.enable(spi_pll_ena),
.osc(clock),
.osc(clock_core),
.clockp({pll_clk, pll_clk90}),
.div(spi_pll_div),
.dco(spi_pll_dco_ena),

4
verilog/rtl/caravel.v
View File

@ -616,7 +616,7 @@ module caravel (
.ext_clk(clock_core),
.pll_clk(pll_clk),
.pll_clk90(pll_clk90),
.resetb(rstb_h),
.resetb(rstb_l),
.sel(spi_pll_sel),
.sel2(spi_pll90_sel),
.ext_reset(ext_reset), // From housekeeping SPI
@ -632,7 +632,7 @@ module caravel (
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.resetb(rstb_h),
.resetb(rstb_l),
.enable(spi_pll_ena),
.osc(clock_core),
.clockp({pll_clk, pll_clk90}),