From 1e14d3a4c517f9e2c755a40eba95bd157b632a4b Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Mon, 22 Nov 2021 13:25:35 -0500 Subject: [PATCH] Corrected the rstb_l signal in both caravan and caravel, and corrected the clock_core signal in caravan. --- verilog/rtl/caravan.v | 6 +++--- verilog/rtl/caravel.v | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v index a0d895b6..19943db8 100644 --- a/verilog/rtl/caravan.v +++ b/verilog/rtl/caravan.v @@ -673,7 +673,7 @@ module caravan ( .ext_clk(clock_core), .pll_clk(pll_clk), .pll_clk90(pll_clk90), - .resetb(resetb), + .resetb(rstb_l), .sel(spi_pll_sel), .sel2(spi_pll90_sel), .ext_reset(ext_reset), // From housekeeping SPI @@ -689,9 +689,9 @@ module caravan ( .VPWR(vccd_core), .VGND(vssd_core), `endif - .resetb(resetb), + .resetb(rstb_l), .enable(spi_pll_ena), - .osc(clock), + .osc(clock_core), .clockp({pll_clk, pll_clk90}), .div(spi_pll_div), .dco(spi_pll_dco_ena), diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index 3a3a45aa..dc3c04db 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v @@ -616,7 +616,7 @@ module caravel ( .ext_clk(clock_core), .pll_clk(pll_clk), .pll_clk90(pll_clk90), - .resetb(rstb_h), + .resetb(rstb_l), .sel(spi_pll_sel), .sel2(spi_pll90_sel), .ext_reset(ext_reset), // From housekeeping SPI @@ -632,7 +632,7 @@ module caravel ( .VPWR(vccd_core), .VGND(vssd_core), `endif - .resetb(rstb_h), + .resetb(rstb_l), .enable(spi_pll_ena), .osc(clock_core), .clockp({pll_clk, pll_clk90}),