diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v
index a0d895b6..19943db8 100644
--- a/verilog/rtl/caravan.v
+++ b/verilog/rtl/caravan.v
@@ -673,7 +673,7 @@ module caravan (
 	.ext_clk(clock_core),
 	.pll_clk(pll_clk),
 	.pll_clk90(pll_clk90),
-	.resetb(resetb),
+	.resetb(rstb_l),
 	.sel(spi_pll_sel),
 	.sel2(spi_pll90_sel),
 	.ext_reset(ext_reset),  // From housekeeping SPI
@@ -689,9 +689,9 @@ module caravan (
 	    .VPWR(vccd_core),
 	    .VGND(vssd_core),
 	`endif
-	.resetb(resetb),
+	.resetb(rstb_l),
 	.enable(spi_pll_ena),
-	.osc(clock),
+	.osc(clock_core),
 	.clockp({pll_clk, pll_clk90}),
 	.div(spi_pll_div),
 	.dco(spi_pll_dco_ena),
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 3a3a45aa..dc3c04db 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -616,7 +616,7 @@ module caravel (
         .ext_clk(clock_core),
         .pll_clk(pll_clk),
         .pll_clk90(pll_clk90),
-        .resetb(rstb_h),
+        .resetb(rstb_l),
         .sel(spi_pll_sel),
         .sel2(spi_pll90_sel),
         .ext_reset(ext_reset),  // From housekeeping SPI
@@ -632,7 +632,7 @@ module caravel (
 		.VPWR(vccd_core),
 		.VGND(vssd_core),
     `endif
-        .resetb(rstb_h),
+        .resetb(rstb_l),
         .enable(spi_pll_ena),
         .osc(clock_core),
         .clockp({pll_clk, pll_clk90}),