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fix bug assert csb before reset for the GL sim to work

This commit is contained in:
M0stafaRady 2022-10-01 12:36:02 -07:00
parent 53e868abdf
commit 199d5c0f5c
2 changed files with 5 additions and 3 deletions
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6
verilog/dv/cocotb/caravel.py
View File

@ -51,14 +51,16 @@ class Caravel_env:
"""start carvel by insert power then reset""" """start carvel by insert power then reset"""
async def start_up(self): async def start_up(self):
await self.power_up() await self.power_up()
await self.disable_csb()
await self.reset() await self.reset()
await self.disable_bins() await self.disable_bins()
await self.disable_csb()
common.fill_macros(self.dut.macros) # get macros value common.fill_macros(self.dut.macros) # get macros value
async def disable_bins(self): async def disable_bins(self):
for i in range(38): for i in range(38):
common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0) if i == 3:
continue
common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0)
"""setup the vdd and vcc power bins""" """setup the vdd and vcc power bins"""
async def power_up(self): async def power_up(self):

2
verilog/dv/cocotb/caravel_tests.py
View File

@ -32,7 +32,7 @@ from tests.mem.mem_stress import *
from tests.irq.IRQ_external import * from tests.irq.IRQ_external import *
from tests.irq.IRQ_timer import * from tests.irq.IRQ_timer import *
from tests.irq.IRQ_uart import * from tests.irq.IRQ_uart import *
from tests.gpio.gpio_all_o import * from tests.gpio.gpio import *
from tests.mgmt_gpio.mgmt_gpio import * from tests.mgmt_gpio.mgmt_gpio import *
from tests.timer.timer import * from tests.timer.timer import *
from tests.uart.uart import * from tests.uart.uart import *