mirror of https://github.com/efabless/caravel.git
47 lines
1.5 KiB
Python
47 lines
1.5 KiB
Python
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import random
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import cocotb
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from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
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import cocotb.log
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from cpu import RiskV
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from defsParser import Regs
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from cocotb.result import TestSuccess
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from tests.common_functions.test_functions import *
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from tests.bitbang.bitbang_functions import *
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from caravel import GPIO_MODE
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reg = Regs()
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"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
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@cocotb.test()
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@repot_test
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async def temp_partial(dut):
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caravelEnv = await test_configure(dut,timeout_cycles=70000)
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# Apply data 0x1809 (management standard output) to first block of
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# user 1 and user 2 (GPIO 0 and 37) bits 0, 1, 9, and 12 are "1" (data go in backwards)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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while True:
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if cpu.read_debug_reg2() == 0xAA:
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break
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await ClockCycles(caravelEnv.clk,1)
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cpu.cpu_force_reset()
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await ClockCycles(caravelEnv.clk,100)
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await cpu.drive_data2address(reg.get_addr('reg_wb_enable'),1)
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await cpu.drive_data2address(reg.get_addr('reg_debug_1'),0xAA)
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# await cpu.drive_data2address(reg.get_addr('reg_debug_2'),0xBB)
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await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0)
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# await ClockCycles(caravelEnv.clk,100)
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cpu.cpu_release_reset()
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while True:
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if cpu.read_debug_reg2() == 0xBB:
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break
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await ClockCycles(caravelEnv.clk,1)
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await ClockCycles(caravelEnv.clk,100)
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