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riscv
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caravel
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d12fac2ad1
caravel
/
verilog
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M0stafaRady
d12fac2ad1
update run script to delete vcs files before test run
2022-10-01 12:28:52 -07:00
..
dv
update run script to delete vcs files before test run
2022-10-01 12:28:52 -07:00
gl
reharden!: gpio_control_block
2022-09-27 07:09:26 -07:00
rtl
Add RTL for 2 debug regs used to test and located inside user_project_wrapper
2022-09-30 03:52:34 -07:00
stubs
[DATA] Add spare_logic_block
2021-11-24 20:36:23 +02:00