mirror of https://github.com/efabless/caravel.git
104 lines
2.7 KiB
Tcl
104 lines
2.7 KiB
Tcl
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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set script_dir [file dirname [file normalize [info script]]]
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set ::env(DESIGN_NAME) gpio_control_block
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set ::env(VERILOG_FILES) "\
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$script_dir/../../verilog/rtl/defines.v\
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$script_dir/../../verilog/rtl/gpio_control_block.v"
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set ::env(CLOCK_PORT) "serial_clock"
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set ::env(CLOCK_PERIOD) "25"
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set ::env(VDD_NETS) "vccd vccd1"
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set ::env(GND_NETS) "vssd vssd1"
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## Synthesis
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set ::env(SYNTH_READ_BLACKBOX_LIB) 1
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set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
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## Floorplan
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set ::env(FP_SIZING) absolute
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set ::env(DIE_AREA) "0 0 170 70"
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set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
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set ::env(FP_IO_VEXTEND) 20
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set ::env(FP_IO_HLENGTH) 100
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set ::env(RIGHT_MARGIN_MULT) 262
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set ::env(LEFT_MARGIN_MULT) 10
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set ::env(TOP_MARGIN_MULT) 4
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set ::env(BOTTOM_MARGIN_MULT) 4
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set ::env(CELL_PAD) 0
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## PDN
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set ::env(PDN_CFG) $script_dir/pdn.tcl
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set ::env(FP_PDN_AUTO_ADJUST) 0
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set ::env(FP_PDN_CORE_RING) 1
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set ::env(FP_PDN_VWIDTH) 1.6
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set ::env(FP_PDN_HWIDTH) 1.6
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set ::env(FP_HORIZONTAL_HALO) 2
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set ::env(FP_VERTICAL_HALO) 2
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set ::env(FP_PDN_HOFFSET) 1.5
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set ::env(FP_PDN_VOFFSET) 8.5
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set ::env(FP_PDN_HPITCH) 15.5
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set ::env(FP_PDN_VPITCH) 15.5
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set ::env(FP_PDN_VSPACING) 3.4
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set ::env(FP_PDN_HSPACING) 3.4
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set ::env(FP_PDN_CORE_RING_VOFFSET) 2
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set ::env(FP_PDN_CORE_RING_HOFFSET) 2
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## Placement
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set ::env(PL_TARGET_DENSITY) 0.898
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# for some reason resizer is leaving a floating net after running repair_tie_fanout command
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set ::env(PL_RESZIER_REPIAR_TIE_FANOUT) 0
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# mgmt_gpio_in is driven by a tristate cell
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set ::env(DONT_BUFFER_PORTS) "mgmt_gpio_in"
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## Routing
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set ::env(GLB_RT_MINLAYER) 2
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set ::env(GLB_RT_MAXLAYER) 4
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set ::env(GLB_RT_ADJUSTMENT) 0.05
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# Add obstructions on the areas that will lie underneath the padframe
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set ::env(GLB_RT_OBS) "\
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met5 67 0 170 70,
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met4 67 0 170 70,
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met2 120 0 170 70,
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met1 120 0 170 70"
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## Internal macros
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set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
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set ::env(VERILOG_FILES_BLACKBOX) "\
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$script_dir/../../verilog/rtl/gpio_logic_high.v"
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set ::env(EXTRA_LEFS) "\
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$script_dir/../../lef/gpio_logic_high.lef"
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set ::env(EXTRA_GDS_FILES) "\
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$script_dir/../../gds/gpio_logic_high.gds"
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