2021-11-08 05:34:59 -06:00
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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set script_dir [file dirname [file normalize [info script]]]
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set ::env(DESIGN_NAME) digital_pll
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set ::env(DESIGN_IS_CORE) 1
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set ::env(VERILOG_FILES) $script_dir/../../verilog/rtl/digital_pll.v
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set ::env(CLOCK_PORT) ""
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set ::env(CLOCK_TREE_SYNTH) 0
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# Synthesis
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set ::env(SYNTH_READ_BLACKBOX_LIB) 1
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set ::env(SYNTH_MAX_FANOUT) 6
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set ::env(SYNTH_BUFFERING) 0
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set ::env(SYNTH_SIZING) 0
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2021-11-15 07:50:43 -06:00
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set ::env(BASE_SDC_FILE) $script_dir/base.sdc
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2021-11-08 05:34:59 -06:00
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## Floorplan
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set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
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set ::env(FP_SIZING) absolute
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set ::env(DIE_AREA) "0 0 75 75"
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set ::env(TOP_MARGIN_MULT) 2
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set ::env(BOTTOM_MARGIN_MULT) 2
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set ::env(CELL_PAD) 0
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## PDN
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set ::env(FP_PDN_VPITCH) 40
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set ::env(FP_PDN_HPITCH) 40
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## Placement
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set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
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set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
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set ::env(PL_TARGET_DENSITY) 0.82
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## Routing
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set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
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set ::env(GLB_RT_ADJUSTMENT) 0
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## Diode Insertion
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set ::env(DIODE_INSERTION_STRATEGY) "4"
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