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riscv
/
caravel
mirror of
https://github.com/efabless/caravel.git
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64bdd6230d
caravel
/
openlane
/
digital_pll
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manarabdelaty
72b2c724c9
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 15:50:43 +02:00
..
base.sdc
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 15:50:43 +02:00
config.tcl
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 15:50:43 +02:00
pin_order.cfg
Add initial config for the digital_pll
2021-11-08 13:34:59 +02:00