mirror of https://github.com/efabless/caravel.git
201 lines
7.5 KiB
Python
201 lines
7.5 KiB
Python
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from cgitb import handler
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import random
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
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import cocotb.log
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import cocotb.simulator
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from cocotb_coverage.coverage import *
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from cocotb.binary import BinaryValue
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import caravel
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from logic_analyzer import LA
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from caravel import GPIO_MODE, Caravel_env
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from wb_models.housekeepingWB.housekeepingWB import HK_whiteBox
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import common
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import logging
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from cpu import RiskV
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from cocotb.log import SimTimeContextFilter
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from cocotb.log import SimLogFormatter
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from defsParser import Regs
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from tests.common_functions.Timeout import Timeout
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from cocotb.result import TestSuccess
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import inspect
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import os
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# tests
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from tests.bitbang.bitbang_tests import *
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from tests.bitbang.bitbang_tests_cpu import *
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from tests.housekeeping.housekeeping_regs.housekeeping_regs_tests import *
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from tests.temp_partial_test.partial import *
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from tests.hello_world.helloWorld import *
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from tests.cpu.cpu_stress import *
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from tests.mem.mem_stress import *
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from tests.irq.IRQ_external import *
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from tests.irq.IRQ_timer import *
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from tests.irq.IRQ_uart import *
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from tests.gpio.gpio_all_o import *
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from tests.mgmt_gpio.mgmt_gpio import *
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from tests.timer.timer import *
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from tests.uart.uart import *
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# archive tests
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@cocotb.test()
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async def cpu_drive(dut):
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TestName = inspect.stack()[0][3]
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if not os.path.exists(f'sim/{TestName}'):
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os.mkdir(f'sim/{TestName}') # create test folder
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cocotb.log.setLevel(logging.INFO)
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handler = logging.FileHandler(f"sim/{TestName}/{TestName}.log",mode='w')
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handler.addFilter(SimTimeContextFilter())
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handler.setFormatter(SimLogFormatter())
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cocotb.log.addHandler(handler)
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caravelEnv = caravel.Caravel_env(dut)
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Timeout(caravelEnv.clk,1000000,0.1)
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la = LA(dut)
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clock = Clock(caravelEnv.clk, 12.5, units="ns") # Create a 10ns period clock on port clk
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cocotb.start_soon(clock.start()) # Start the clock
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await caravelEnv.start_up()
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hk = HK_whiteBox(dut)
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reg = Regs()
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time_out_count =0
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await ClockCycles(caravelEnv.clk, 100)
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address = reg.get_addr('reg_wb_enable')
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await cpu.drive_data2address(address,1)
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address = reg.get_addr('reg_debug_2')
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await cpu.drive_data2address(address,0xdFF0)
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await ClockCycles(caravelEnv.clk, 10)
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cpu.cpu_release_reset()
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await ClockCycles(caravelEnv.clk, 10)
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raise TestSuccess(f" TEST {TestName} passed")
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while True:
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await ClockCycles(caravelEnv.clk, 1)
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if (cpu.read_debug_reg1() == 0xFFF0):
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break
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cocotb.log.info(f"[TEST][cpu_drive] debug reg1 = 0xFFF0")
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await ClockCycles(caravelEnv.clk, 10)
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address = reg.get_addr('reg_debug_2')
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await cpu.drive_data2address(address,0xdFF0)
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await ClockCycles(caravelEnv.clk, 50)
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# address = reg.get_addr('reg_mprj_io_0')
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# await cpu.drive_data2address(address,0x0c03)
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cocotb.log.info(f"[TEST][cpu_drive] wait debug reg1 = 0xddd0")
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while True:
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await ClockCycles(caravelEnv.clk, 1)
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if (cpu.read_debug_reg1() == 0xddd0):
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break
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cocotb.log.info(f"[TEST][cpu_drive] debug reg1 = 0xddd0")
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await ClockCycles(caravelEnv.clk, 10)
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caravelEnv.print_gpios_HW_val()
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coverage_db.export_to_yaml(filename="coverage.yalm")
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@cocotb.test()
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async def spi_drive(dut):
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cocotb.log.setLevel(logging.INFO)
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handler = logging.FileHandler(f"test.log",mode='w')
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handler.addFilter(SimTimeContextFilter())
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handler.setFormatter(SimLogFormatter())
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cocotb.log.addHandler(handler)
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caravelEnv = caravel.Caravel_env(dut)
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la = LA(dut)
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clock = Clock(caravelEnv.clk, 12.5, units="ns") # Create a 10ns period clock on port clk
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cocotb.start_soon(clock.start()) # Start the clock
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await caravelEnv.start_up()
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hk = HK_whiteBox(dut,True)
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caravelEnv.enable_csb()
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await ClockCycles(caravelEnv.clk,1)
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# caravelEnv.configure_gpios_regs([[tuple(range(0,6)),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT]])
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await ClockCycles(caravelEnv.clk,1)
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await caravelEnv.hk_write_byte(0x40) # read command
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# await caravelEnv.hk_write_byte(0x80) # command write
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await caravelEnv.hk_write_byte(0x0) # address
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# await caravelEnv.hk_write_byte(0x03) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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read_data = await caravelEnv.hk_read_byte() # read value
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print(read_data)
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read_data = await caravelEnv.hk_read_byte() # read value
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print(read_data)
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read_data = await caravelEnv.hk_read_byte() # read value
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print(read_data)
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read_data = await caravelEnv.hk_read_byte() # read value
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print(read_data)
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read_data = await caravelEnv.hk_read_byte() # read value
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print(read_data)
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read_data = await caravelEnv.hk_read_byte() # read value
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print(read_data)
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read_data = await caravelEnv.hk_read_byte() # read value
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print(read_data)
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read_data = await caravelEnv.hk_read_byte(True) # read value
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caravelEnv.disable_csb()
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await ClockCycles(caravelEnv.clk,1)
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caravelEnv.enable_csb()
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await ClockCycles(caravelEnv.clk,1)
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# caravelEnv.configure_gpios_regs([[tuple(range(0,6)),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT]])
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await ClockCycles(caravelEnv.clk,1)
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await caravelEnv.hk_write_byte(0x40) # read command
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# await caravelEnv.hk_write_byte(0x80) # command write
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await caravelEnv.hk_write_byte(0x8) # address
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# await caravelEnv.hk_write_byte(0x03) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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# await caravelEnv.hk_write_byte(0xaa) # data
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read_data = await caravelEnv.hk_read_byte() # read value
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read_data = await caravelEnv.hk_read_byte() # read value
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read_data = await caravelEnv.hk_read_byte() # read value
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read_data = await caravelEnv.hk_read_byte() # read value
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read_data = await caravelEnv.hk_read_byte() # read value
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read_data = await caravelEnv.hk_read_byte() # read value
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read_data = await caravelEnv.hk_read_byte() # read value
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read_data = await caravelEnv.hk_read_byte() # read value
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# caravelEnv.drive_gpio_in([5,5],1)
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await ClockCycles(caravelEnv.clk,40)
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coverage_db.export_to_yaml(filename="coverage.yml")
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coverage_db.export_to_xml(filename="coverage.xml")
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return
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