This website requires JavaScript.
Explore
Help
Sign In
riscv
/
caravel
mirror of
https://github.com/efabless/caravel.git
Watch
1
Star
0
Fork
You've already forked caravel
0
Code
Issues
Projects
Releases
Wiki
Activity
53e868abdf
caravel
/
verilog
History
M0stafaRady
53e868abdf
add clock to the output od configuration function
2022-10-01 12:34:53 -07:00
..
dv
add clock to the output od configuration function
2022-10-01 12:34:53 -07:00
gl
reharden!: gpio_control_block
2022-09-27 07:09:26 -07:00
rtl
Add RTL for 2 debug regs used to test and located inside user_project_wrapper
2022-09-30 03:52:34 -07:00
stubs
[DATA] Add spare_logic_block
2021-11-24 20:36:23 +02:00