caravel/manifest

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489e60b851555f9238e3f9949c01b95fbad13565 verilog/rtl/__openframe_project_wrapper.v
2021-12-16 16:26:20 -06:00
535d0592c0b1349489b6b86fd5449f9d1d81482e verilog/rtl/__uprj_analog_netlists.v
87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v
729a8ce3c67c5197578ecc31db960c91ce437b27 verilog/rtl/__user_analog_project_wrapper.v
79cdb50a7dd60f69b63c0b6440b0dea35386387d verilog/rtl/__user_project_gpio_example.v
5f8e2d6670ce912bc209201d23430f62730e2627 verilog/rtl/__user_project_la_example.v
cc82a78753f5f5d0a1519bd81adbcff8a4296d91 verilog/rtl/__user_project_wrapper.v
3c8c04f53b2848dc46132cda82c614e06e56571b verilog/rtl/buff_flash_clkrst.v
14064261ec18d633a5d72b45b2347c388f2f446f verilog/rtl/caravan.v
864365067a3fbb8fe3354d94d94c7b8469999850 verilog/rtl/caravan_core.v
e68fd2e085679d0f61040115fdd1d50651705d3a verilog/rtl/caravan_logo.v
d265ea6bf861e3f5c1b1b984ae057dbaed995008 verilog/rtl/caravan_motto.v
baf7cf0e8a8a712621aed75aff98198a663db43b verilog/rtl/caravan_netlists.v
2021-12-16 16:26:20 -06:00
a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
b532b4c6315c29fd19fe38ac221b6fc41e6f5ecb verilog/rtl/caravan_power_routing.v
fa26aa34b4b382aacad9b7ac07a36b17172a401f verilog/rtl/caravel.v
3a9c60ba878b7f96824b4b81373e7994765d8410 verilog/rtl/caravel_clocking.v
51094e5b152b6c1f4babe8af998321dc4e909a03 verilog/rtl/caravel_core.v
625c9f974f1a3c9bd2eca5449a89a7bfb8f69fe8 verilog/rtl/caravel_logo.v
1bbaa93405d4cb51429eacea4da40014231b11ed verilog/rtl/caravel_motto.v
ae07f0d87e69f4dd2026ed841e3a962facac847b verilog/rtl/caravel_openframe.v
d97cb60c8d125d6098111d4f0aa00410515770eb verilog/rtl/caravel_power_routing.v
bc1e961e41d1d3a383a018279a08bf4108911f53 verilog/rtl/chip_io.v
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
f2242e1f295ee5efeacea51698f706a2cfd97c28 verilog/rtl/chip_io_alt.v
f97affcdbf268c61ada91eed6a2238e52e1b9889 verilog/rtl/chip_io_openframe.v
2021-12-16 16:26:20 -06:00
126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v
941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v
58fd210a64e502fb231d843eada4052f923d788d verilog/rtl/copyright_block.v
c254b1c442ca54e018d548d96d2ad0bb122a1203 verilog/rtl/copyright_block_a.v
653b230c7cbf092a6210ba7820bc942f312e53f3 verilog/rtl/debug_regs.v
2a7b5d508735fd485f8adcb3f8766ea3830091c2 verilog/rtl/digital_pll.v
2021-12-16 16:26:20 -06:00
ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
f59fbff4794516ddae686d0e9c785aafebdd2224 verilog/rtl/empty_macro.v
51d906134dabd5bcc9c84324f639230a76bf3d25 verilog/rtl/gpio_control_block.v
bdccd8cd65212a8000e0cc0a247231ead65398cc verilog/rtl/gpio_defaults_block.v
2021-12-16 16:26:20 -06:00
32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v
406b6eba38e0a7e8ff561dc4e5395dbefc9c175c verilog/rtl/gpio_signal_buffering.v
45ea4a2d466d6d70e9e86011a62c1bd3f706ef99 verilog/rtl/gpio_signal_buffering_alt.v
7ba9d7552eb3bbe4c7c11e2b8464be3c09d91e0b verilog/rtl/housekeeping.v
811b213541ad0a7429c3c933417d1bbbe49a7ab5 verilog/rtl/housekeeping_alt.v
34c6ab585986a00216c72f2f1fea0e5a8523867b verilog/rtl/housekeeping_spi.v
9fa366d3ac47b18c175131396248e7e7c81e3eb1 verilog/rtl/manual_power_connections.v
0a00fd77505b29c1367b2c21d0bbc940fc50ab01 verilog/rtl/mgmt_protect.v
2021-12-16 16:26:20 -06:00
3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v
9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v
c96ba94e5779ea6afe452d89632eaada73e26aab verilog/rtl/mprj_io.v
e0c6ead5e35c1ba01d923c482e953c2af9691524 verilog/rtl/mprj_io_buffer.v
2021-12-16 16:26:20 -06:00
3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v
5287821a0ed1994850a978ef0cd024fac51fb6e8 verilog/rtl/open_source.v
33c8fc54298e5425875aaab8c139074ec7d0e9e9 verilog/rtl/openframe_netlists.v
4edbfd0ad80b69a799a399ffc717b560fcae615b verilog/rtl/pads.v
2021-12-16 16:26:20 -06:00
669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v
739ca5ed63a513d2e4c9bf3ecfad32d9fa527518 verilog/rtl/simple_por.v
b9d6114a5067a04dd59cdd46fb988591c16743ce verilog/rtl/spare_logic_block.v
036dc8e9066082b2e133dc7b72fd3ad5a52f254b verilog/rtl/toplevel_cocotb.v
2021-12-16 16:26:20 -06:00
8f0bec01c914efe790a09ffe62bbfe0781069e35 verilog/rtl/xres_buf.v
256190717faa72005cf7656d8443c4c0693b3f78 scripts/set_user_id.py
731116709a44d13225170acc83cd34ff9e00fa39 scripts/generate_fill.py
dff8adfb05bedf96f86e16a18ce3cd5818d6fb78 scripts/compositor.py