Apply automatic changes to Manifest and README.rst

manifest

@@ -1,6 +1,6 @@
 535d0592c0b1349489b6b86fd5449f9d1d81482e  verilog/rtl/__uprj_analog_netlists.v
 87735eb5981740ca4d4b48e6b0321c8bb0023800  verilog/rtl/__uprj_netlists.v
-cf40562ae6508f3dc5e81420e31f7b5886dc3c8f  verilog/rtl/__user_analog_project_wrapper.v
+729a8ce3c67c5197578ecc31db960c91ce437b27  verilog/rtl/__user_analog_project_wrapper.v
 79cdb50a7dd60f69b63c0b6440b0dea35386387d  verilog/rtl/__user_project_gpio_example.v
 5f8e2d6670ce912bc209201d23430f62730e2627  verilog/rtl/__user_project_la_example.v
 cc82a78753f5f5d0a1519bd81adbcff8a4296d91  verilog/rtl/__user_project_wrapper.v
@@ -27,12 +27,12 @@ f2242e1f295ee5efeacea51698f706a2cfd97c28  verilog/rtl/chip_io_alt.v
 ce49f9af199b5f16d2c39c417d58e5890bc7bab2  verilog/rtl/digital_pll_controller.v
 f59fbff4794516ddae686d0e9c785aafebdd2224  verilog/rtl/empty_macro.v
 51d906134dabd5bcc9c84324f639230a76bf3d25  verilog/rtl/gpio_control_block.v
-6aae2132de98430b8195c4f32a9da6329b86b024  verilog/rtl/gpio_defaults_block.v
+bdccd8cd65212a8000e0cc0a247231ead65398cc  verilog/rtl/gpio_defaults_block.v
 32d395d5936632f3c92a0de4867d6dd7cd4af1bb  verilog/rtl/gpio_logic_high.v
 406b6eba38e0a7e8ff561dc4e5395dbefc9c175c  verilog/rtl/gpio_signal_buffering.v
 45ea4a2d466d6d70e9e86011a62c1bd3f706ef99  verilog/rtl/gpio_signal_buffering_alt.v
 7ba9d7552eb3bbe4c7c11e2b8464be3c09d91e0b  verilog/rtl/housekeeping.v
-5963b6d10f61b0224fa4f783d1147e587cf571d5  verilog/rtl/housekeeping_alt.v
+811b213541ad0a7429c3c933417d1bbbe49a7ab5  verilog/rtl/housekeeping_alt.v
 34c6ab585986a00216c72f2f1fea0e5a8523867b  verilog/rtl/housekeeping_spi.v
 9fa366d3ac47b18c175131396248e7e7c81e3eb1  verilog/rtl/manual_power_connections.v
 0a00fd77505b29c1367b2c21d0bbc940fc50ab01  verilog/rtl/mgmt_protect.v
@@ -44,7 +44,7 @@ e0c6ead5e35c1ba01d923c482e953c2af9691524  verilog/rtl/mprj_io_buffer.v
 5287821a0ed1994850a978ef0cd024fac51fb6e8  verilog/rtl/open_source.v
 4edbfd0ad80b69a799a399ffc717b560fcae615b  verilog/rtl/pads.v
 669d16642d5dd5f6824812754db20db98c9fe17b  verilog/rtl/ring_osc2x13.v
-6f802b6ab7e6502160adfe41e313958b86d2c277  verilog/rtl/simple_por.v
+739ca5ed63a513d2e4c9bf3ecfad32d9fa527518  verilog/rtl/simple_por.v
 b9d6114a5067a04dd59cdd46fb988591c16743ce  verilog/rtl/spare_logic_block.v
 8f0bec01c914efe790a09ffe62bbfe0781069e35  verilog/rtl/xres_buf.v
 256190717faa72005cf7656d8443c4c0693b3f78  scripts/set_user_id.py