riscv
/
caravel
mirror of https://github.com/efabless/caravel.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
caravel/scripts/run_caravel_lvs.sh

31 lines
766 B
Bash
Raw Normal View History

Corrected an error in verilog/gl/chip_io_alt.v, which was missing connections to the core side VCCD1 and VSSD1 on the clamped3 pads. Also added scripts for running LVS on chip_io to the mag/ directory, and revised the scripts so that they will only re-run extraction if there is no netlist file in the mag/ directory.
2021-12-07 09:06:35 -06:00
#!/bin/bash
Numerous bug fixes, ending in clean full LVS for both caravel and caravan. (#76) * (1) Modified the .magicrc file to set a default for PDK if not set in the environment. (2) Fixed the user ID programming layout to not leave holes behind when the script moves the vias around (similar to the handling of the GPIO defaults block). (3) Added substrate isolation to gpio_control_block and fixed the path references to the standard cells. (4) Fixed the four missing routes on the Caravan top level. (5) Reinstated the large rendered labels for the pads on both caravel and caravan. (6) Corrected the top level gate-level netlist for caravan to add the missing pins to the management core wrapper. (7) Did the same for the caravan top level RTL. (8) Created scripts to run full LVS including extracting the management core wrapper and reading all gate-level verilog submodules. (9) Moved all of the LVS scripts to the scripts directory. * Apply automatic changes to Manifest and README.rst * Made the changes from pull request #73 as they did not get merged successfully, and if merged now they will generate conflicts with this pull request in scripts/set_user_id.py. So it's easier to just manually add them to this pull request. * Apply automatic changes to Manifest and README.rst Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-04-19 21:05:27 -05:00
# Run top-level LVS on caravel. The extraction in magic does not include the SoC,
# which is abstracted.
Modifications done as part of LVS on the caravel top level.
2021-11-21 21:07:16 -06:00
#
Corrected a statement in the LVS scripts in the mag/ directory that is Makefile syntax, not bash syntax, and will cause the script to produce an incorrect LVS result without generating a syntax error.
2021-12-17 21:27:32 -06:00
echo ${PDK_ROOT:=/usr/share/pdk} > /dev/null
Added other blocks that were modified to put in the isolated substrate regions, although this does not completely resolve the substrate-related LVS error.
2022-04-09 13:29:19 -05:00
echo ${PDK:=sky130A} > /dev/null
Revised the LVS run scripts to use $PDK_ROOT instead of a hard- coded path.
2021-12-07 09:32:22 -06:00
Numerous bug fixes, ending in clean full LVS for both caravel and caravan. (#76) * (1) Modified the .magicrc file to set a default for PDK if not set in the environment. (2) Fixed the user ID programming layout to not leave holes behind when the script moves the vias around (similar to the handling of the GPIO defaults block). (3) Added substrate isolation to gpio_control_block and fixed the path references to the standard cells. (4) Fixed the four missing routes on the Caravan top level. (5) Reinstated the large rendered labels for the pads on both caravel and caravan. (6) Corrected the top level gate-level netlist for caravan to add the missing pins to the management core wrapper. (7) Did the same for the caravan top level RTL. (8) Created scripts to run full LVS including extracting the management core wrapper and reading all gate-level verilog submodules. (9) Moved all of the LVS scripts to the scripts directory. * Apply automatic changes to Manifest and README.rst * Made the changes from pull request #73 as they did not get merged successfully, and if merged now they will generate conflicts with this pull request in scripts/set_user_id.py. So it's easier to just manually add them to this pull request. * Apply automatic changes to Manifest and README.rst Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-04-19 21:05:27 -05:00
cd ../mag
Introduction of PDK variable (#39) * added PDK_VARIENT variable * changed variable name to PDK * resolve issue Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-08 11:05:58 -05:00
magic -dnull -noconsole -rcfile $PDK_ROOT/$PDK/libs.tech/magic/$PDK.magicrc << EOF
Reworked part of the layouts of both caravel and caravan to move the clocking subcircuit from inside the pad area near the "clock" pin to under the DLL. This prevents the DLL from having its outputs travel all the way across the chip to reach the clocking cell and then have the multiplexed clock travel all the way back, especially as the DLL outputs are high-speed signals (up to 150 MHz).
2021-12-02 19:45:39 -06:00
drc off
crashbackups stop
load caravel
select top cell
expand
issue-105: caravel & caravan.mag: relabel top-level v*_core power nets (label PLUS underlying met5); (#110) tweak blackbox lvs scripts for very fast extract; update spi/lvs/*.spice. The .spice (once propagated to caravel-lite AND caravel-lite embed in mpw_precheck docker) will pass the consistency check. Co-authored-by: Risto Bell <rb@efabless.com>
2022-08-27 01:03:00 -05:00
extract no all ;# <-- large speed-up
Reworked part of the layouts of both caravel and caravan to move the clocking subcircuit from inside the pad area near the "clock" pin to under the DLL. This prevents the DLL from having its outputs travel all the way across the chip to reach the clocking cell and then have the multiplexed clock travel all the way back, especially as the DLL outputs are high-speed signals (up to 150 MHz).
2021-12-02 19:45:39 -06:00
extract do local
extract all
ext2spice lvs
ext2spice
EOF
Changed the user project wrapper and user analog project wrapper to be abstract views, and modified the LVS scripts accordingly (they no longer need a special version of the netgen setup script). LVS was verified on both caravel and caravan using this setup.
2021-12-07 21:21:49 -06:00
rm -f *.ext
Reworked part of the layouts of both caravel and caravan to move the clocking subcircuit from inside the pad area near the "clock" pin to under the DLL. This prevents the DLL from having its outputs travel all the way across the chip to reach the clocking cell and then have the multiplexed clock travel all the way back, especially as the DLL outputs are high-speed signals (up to 150 MHz).
2021-12-02 19:45:39 -06:00
Modifications done as part of LVS on the caravel top level.
2021-11-21 21:07:16 -06:00
export NETGEN_COLUMNS=60
Numerous bug fixes, ending in clean full LVS for both caravel and caravan. (#76) * (1) Modified the .magicrc file to set a default for PDK if not set in the environment. (2) Fixed the user ID programming layout to not leave holes behind when the script moves the vias around (similar to the handling of the GPIO defaults block). (3) Added substrate isolation to gpio_control_block and fixed the path references to the standard cells. (4) Fixed the four missing routes on the Caravan top level. (5) Reinstated the large rendered labels for the pads on both caravel and caravan. (6) Corrected the top level gate-level netlist for caravan to add the missing pins to the management core wrapper. (7) Did the same for the caravan top level RTL. (8) Created scripts to run full LVS including extracting the management core wrapper and reading all gate-level verilog submodules. (9) Moved all of the LVS scripts to the scripts directory. * Apply automatic changes to Manifest and README.rst * Made the changes from pull request #73 as they did not get merged successfully, and if merged now they will generate conflicts with this pull request in scripts/set_user_id.py. So it's easier to just manually add them to this pull request. * Apply automatic changes to Manifest and README.rst Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-04-19 21:05:27 -05:00
netgen -batch lvs "caravel.spice caravel" "../verilog/gl/caravel.v caravel" \
$PDK_ROOT/$PDK/libs.tech/netgen/${PDK}_setup.tcl caravel_comp.out
issue-105: caravel & caravan.mag: relabel top-level v*_core power nets (label PLUS underlying met5); (#110) tweak blackbox lvs scripts for very fast extract; update spi/lvs/*.spice. The .spice (once propagated to caravel-lite AND caravel-lite embed in mpw_precheck docker) will pass the consistency check. Co-authored-by: Risto Bell <rb@efabless.com>
2022-08-27 01:03:00 -05:00
# mv caravel.spice ../spi/lvs/caravel_lvs.spice
mv caravel.spice ../spi/lvs/caravel.spice
Numerous bug fixes, ending in clean full LVS for both caravel and caravan. (#76) * (1) Modified the .magicrc file to set a default for PDK if not set in the environment. (2) Fixed the user ID programming layout to not leave holes behind when the script moves the vias around (similar to the handling of the GPIO defaults block). (3) Added substrate isolation to gpio_control_block and fixed the path references to the standard cells. (4) Fixed the four missing routes on the Caravan top level. (5) Reinstated the large rendered labels for the pads on both caravel and caravan. (6) Corrected the top level gate-level netlist for caravan to add the missing pins to the management core wrapper. (7) Did the same for the caravan top level RTL. (8) Created scripts to run full LVS including extracting the management core wrapper and reading all gate-level verilog submodules. (9) Moved all of the LVS scripts to the scripts directory. * Apply automatic changes to Manifest and README.rst * Made the changes from pull request #73 as they did not get merged successfully, and if merged now they will generate conflicts with this pull request in scripts/set_user_id.py. So it's easier to just manually add them to this pull request. * Apply automatic changes to Manifest and README.rst Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-04-19 21:05:27 -05:00
mv caravel_comp.out ../signoff/
exit 0