mirror of https://github.com/efabless/caravel.git
84 lines
3.3 KiB
Python
84 lines
3.3 KiB
Python
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import random
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
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import cocotb.log
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import cocotb.simulator
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from cocotb.handle import SimHandleBase
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from cocotb.handle import Force
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from cocotb_coverage.coverage import *
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from cocotb.binary import BinaryValue
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import enum
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from cocotb.handle import (
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ConstantObject,
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HierarchyArrayObject,
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HierarchyObject,
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ModifiableObject,
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NonHierarchyIndexableObject,
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SimHandle,
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)
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from itertools import groupby, product
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import interfaces.common as common
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from interfaces.common import GPIO_MODE
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from interfaces.common import MASK_GPIO_CTRL
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from interfaces.common import Macros
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class LA:
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def __init__(self,dut:SimHandleBase):
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self.dut = dut
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self.clk = dut.clock_tb
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self.core_hdl = dut.uut.soc.core
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""" Configure the value of LA probes [0:127]
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writing 1 to any bit means bit acts as outputs from the cpu
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writing 0 to any bit means bit acts as inputs to the cpu """
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async def configure_la_en(self, bits,data):
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self.__drive_la_iena(bits,data)
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self.__drive_la_oenb(bits,data)
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await ClockCycles(self.clk, 1)
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def __drive_la_iena(self, bits,data):
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iena , n_bits = common.signal_value_size(self.core_hdl.la_ien_storage)
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cocotb.log.debug(f' [LA] before change iena with {iena} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]')
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iena[n_bits-1-bits[0]:n_bits-1-bits[1]] = data
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self.core_hdl.la_ien_storage.value = iena
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cocotb.log.info(f' [LA] drive reg_la_iena with {hex(iena)}')
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def __drive_la_oenb(self, bits,data):
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oenb , n_bits = common.signal_value_size(self.core_hdl.la_oe_storage)
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cocotb.log.debug(f' [LA] before change oenb with {oenb} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]')
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oenb[n_bits-1-bits[0]:n_bits-1-bits[1]] = data
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self.core_hdl.la_oe_storage.value = oenb
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cocotb.log.info(f' [LA] drive reg_la_oenb with {hex(oenb)}')
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""" update the value of LA data input from cpu to user project """
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def drive_la_data_to_user(self,bits,data):
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la , n_bits = common.signal_value_size(self.core_hdl.la_out_storage)
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cocotb.log.debug(f' [LA] before la data update with LA ={la} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]')
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la[n_bits-1-bits[0]:n_bits-1-bits[1]] = data
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self.core_hdl.la_out_storage.value = la
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cocotb.log.info(f' [LA] drive_la_data_to_user: drive data {hex(la)} to user project')
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"""return the value of LA data output from user project tp cpu"""
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def check_la_user_out(self):
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LA_out = self.core_hdl.la_input.value
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if(LA_out.is_resolvable):
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cocotb.log.info(f' [LA] Monitor : reg_la_data_out from user = {hex(LA_out)}')
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else:
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cocotb.log.info(f' [LA] Monitor : reg_la_data_out from user = {LA_out}')
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return LA_out
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"""return the value of LA data output from user project tp cpu"""
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def check_la_ctrl_reg(self):
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LA_out = self.dut.uut.la_oenb_mprj.value
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if(LA_out.is_resolvable):
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cocotb.log.info(f' [LA] Monitor : reg_la_data_out from user = {hex(LA_out)}')
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else:
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cocotb.log.info(f' [LA] Monitor : reg_la_data_out from user = {LA_out}')
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return LA_out
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