buggy tutorials...
This commit is contained in:
Olivier Sirol
parent
92da76f9fa
commit
5e99ddbb74
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@ -1,6 +1,5 @@
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#ALLIANCE_TOP = /users/soft5/newlabo/Solaris
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ASIMUT = $(ALLIANCE_TOP)/bin/asimut
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GENLIB = $(ALLIANCE_TOP)/bin/genlib -v
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GENLIB = $(ALLIANCE_TOP)/bin/genlib -v -k
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SCR = $(ALLIANCE_TOP)/bin/scr
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RING = $(ALLIANCE_TOP)/bin/ring
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LYNX = $(ALLIANCE_TOP)/bin/lynx
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@ -9,6 +8,7 @@ YAGLE = $(ALLIANCE_TOP)/bin/yagle
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PROOF = $(ALLIANCE_TOP)/bin/proof
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DRUC = $(ALLIANCE_TOP)/bin/druc
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GRAAL = $(ALLIANCE_TOP)/bin/graal
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DREAL = $(ALLIANCE_TOP)/bin/dreal
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S2R = $(ALLIANCE_TOP)/bin/s2r
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# ###
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@ -23,7 +23,7 @@ all: specifications.pat addaccu.proof addaccu.cif
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@echo "## ##"
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@echo "################################################"
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@echo " "
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@echo "Please run 'dreal -l addaccu' to see the layout."
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@echo "Run 'make dreal' to see the layout."
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@echo " "
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@ -85,7 +85,7 @@ core.ap : core.vst
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MBK_IN_PH=ap ;\
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MBK_OUT_PH=ap ;\
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MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sclib:$(ALLIANCE_TOP)/cells/padlib ;\
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SCR_SCLIB=1 ;\
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SCR_SCLIB=1 ;\
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export MBK_IN_LO MBK_IN_PH MBK_OUT_PH MBK_CATA_LIB SCR_SCLIB ;\
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$(SCR) -p -r core
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@ -144,7 +144,7 @@ addaccu.al : addaccu.ap
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# ###---------------------------------------------------------###
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addaccu.lvx : addaccu.al addaccu.vst
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$(LVX) vst al addaccu > addaccu.lvx
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$(LVX) vst al addaccu addaccu > addaccu.lvx
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cat addaccu.lvx
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# ###---------------------------------------------------------###
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@ -241,3 +241,16 @@ graal : addaccu.ap
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export MBK_IN_PH RDS_TECHNO_NAME MBK_CATA_LIB ;\
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$(GRAAL) -l addaccu
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# ###---------------------------------------------------------###
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# look at the circuit under dreal #
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# ###---------------------------------------------------------###
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dreal : addaccu.cif
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MBK_IN_PH=ap ;\
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MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sclib:$(ALLIANCE_TOP)/cells/padlib ;\
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RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/prol05.rds ;\
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RDS_OUT=cif ;\
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RDS_IN=cif ;\
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export MBK_IN_PH RDS_IN RDS_OUT RDS_TECHNO_NAME MBK_CATA_LIB ;\
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$(DREAL) -l addaccu
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@ -180,9 +180,10 @@ heart.ap : asimut_vst
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MBK_IN_LO=vst ;\
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MBK_WORK_LIB=. ;\
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MBK_CATA_LIB=.:$(ALLIANCE_TOP)/cells/sclib:$(ALLIANCE_TOP)/cells/padlib;\
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export MBK_IN_PH MBK_OUT_PH MBK_IN_LO MBK_WORK_LIB MBK_CATA_LIB;\
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SCR_SCLIB=1 ;\
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export MBK_IN_PH MBK_OUT_PH MBK_IN_LO MBK_WORK_LIB MBK_CATA_LIB SCR_SCLIB ;\
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$(SCR) -p -r heart;\
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$(GRAAL) -l heart
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# $(GRAAL) -l heart
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#################################################################
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# ASIMUT #
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@ -1,520 +0,0 @@
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-- VHDL structural description generated from `accu`
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-- date : Sun Sep 27 12:27:24 1998
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-- Entity Declaration
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ENTITY accu IS
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PORT (
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alu_out : in BIT_VECTOR (3 DOWNTO 0); -- alu_out
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q0 : in BIT; -- q0
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q3 : in BIT; -- q3
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fonc : in BIT; -- fonc
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test : in BIT; -- test
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fonc_mode : linkage BIT; -- fonc_mode
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scin : in BIT; -- scin
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scout : out BIT; -- scout
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f0 : out BIT; -- f0
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f3 : out BIT; -- f3
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decald : out BIT; -- decald
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decalg : out BIT; -- decalg
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q : linkage BIT_VECTOR (3 DOWNTO 0); -- q
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i : in BIT_VECTOR (8 DOWNTO 6); -- i
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ck : in BIT; -- ck
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END accu;
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-- Architecture Declaration
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ARCHITECTURE VST OF accu IS
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COMPONENT n1_y
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port (
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i : in BIT; -- i
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f : out BIT; -- f
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END COMPONENT;
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COMPONENT b1_y
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port (
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i : in BIT; -- i
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t : out BIT; -- t
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END COMPONENT;
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COMPONENT a3_y
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port (
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i0 : in BIT; -- i0
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i1 : in BIT; -- i1
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i2 : in BIT; -- i2
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t : out BIT; -- t
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END COMPONENT;
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COMPONENT o3_y
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port (
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i0 : in BIT; -- i0
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i1 : in BIT; -- i1
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i2 : in BIT; -- i2
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t : out BIT; -- t
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END COMPONENT;
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COMPONENT a2_y
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port (
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i0 : in BIT; -- i0
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i1 : in BIT; -- i1
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t : out BIT; -- t
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END COMPONENT;
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COMPONENT o2_y
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port (
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i0 : in BIT; -- i0
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i1 : in BIT; -- i1
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t : out BIT; -- t
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END COMPONENT;
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COMPONENT ms2_y
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port (
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di : in BIT; -- di
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si : in BIT; -- si
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se : in BIT; -- se
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l : in BIT; -- l
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t : out BIT; -- t
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END COMPONENT;
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SIGNAL a210s : BIT; -- a210s
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SIGNAL a211s : BIT; -- a211s
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SIGNAL a212s : BIT; -- a212s
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SIGNAL a213s : BIT; -- a213s
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SIGNAL a214s : BIT; -- a214s
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SIGNAL a216s : BIT; -- a216s
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SIGNAL a217s : BIT; -- a217s
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SIGNAL a218s : BIT; -- a218s
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SIGNAL a219s : BIT; -- a219s
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SIGNAL a220s : BIT; -- a220s
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SIGNAL a221s : BIT; -- a221s
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SIGNAL a222s : BIT; -- a222s
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SIGNAL a223s : BIT; -- a223s
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SIGNAL a224s : BIT; -- a224s
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SIGNAL a225s : BIT; -- a225s
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SIGNAL a226s : BIT; -- a226s
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SIGNAL a227s : BIT; -- a227s
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SIGNAL a231s : BIT; -- a231s
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SIGNAL a27s : BIT; -- a27s
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SIGNAL a28s : BIT; -- a28s
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SIGNAL a29s : BIT; -- a29s
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SIGNAL ckin : BIT; -- ckin
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SIGNAL decalda : BIT; -- decalda
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SIGNAL decalga : BIT; -- decalga
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SIGNAL decaln : BIT; -- decaln
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SIGNAL insh0 : BIT; -- insh0
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SIGNAL insh1 : BIT; -- insh1
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SIGNAL insh2 : BIT; -- insh2
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SIGNAL insh3 : BIT; -- insh3
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SIGNAL n14s : BIT; -- n14s
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SIGNAL n15s : BIT; -- n15s
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SIGNAL ni6 : BIT; -- ni6
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SIGNAL ni7 : BIT; -- ni7
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SIGNAL o21s : BIT; -- o21s
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SIGNAL selalu : BIT; -- selalu
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SIGNAL shacc0 : BIT; -- shacc0
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SIGNAL shacc1 : BIT; -- shacc1
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SIGNAL shacc2 : BIT; -- shacc2
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SIGNAL shacc3 : BIT; -- shacc3
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SIGNAL test_mode : BIT; -- test_mode
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SIGNAL w : BIT; -- w
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SIGNAL waccu : BIT; -- waccu
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BEGIN
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n11sa : n1_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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f => decaln,
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i => i(8));
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n12sa : n1_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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f => ni7,
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i => i(7));
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n13sa : n1_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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f => ni6,
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i => i(6));
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n14sa : n1_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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f => n14s,
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i => fonc);
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n15sa : n1_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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f => n15s,
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i => test);
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bdecald : b1_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => decald,
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i => decalda);
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bdecalg : b1_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => decalg,
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i => decalga);
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a21sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => decalda,
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i1 => ni7,
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i0 => i(8));
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a22sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => decalga,
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i1 => i(7),
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i0 => i(8));
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a31sa : a3_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => selalu,
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i2 => ni6,
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i1 => ni7,
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i0 => decaln);
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o21sa : o2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => o21s,
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i1 => ni7,
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i0 => i(8));
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a24sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => fonc_mode,
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i1 => n15s,
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i0 => fonc);
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a25sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => test_mode,
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i1 => n14s,
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i0 => test);
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a26sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => waccu,
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i1 => ni6,
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i0 => o21s);
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a27sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => a27s,
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i1 => selalu,
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i0 => alu_out(3));
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a28sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => a28s,
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i1 => selalu,
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i0 => alu_out(2));
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a29sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => a29s,
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i1 => selalu,
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i0 => alu_out(1));
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a210sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => a210s,
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i1 => selalu,
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i0 => alu_out(0));
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a211sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => a211s,
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i1 => i(8),
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i0 => q(3));
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a212sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => a212s,
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i1 => i(8),
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i0 => q(2));
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a213sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => a213s,
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i1 => i(8),
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i0 => q(1));
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a214sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => a214s,
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i1 => i(8),
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i0 => q(0));
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o22sa : o2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => insh3,
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i1 => a211s,
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i0 => a27s);
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o23sa : o2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => insh2,
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i1 => a212s,
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i0 => a28s);
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o24sa : o2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => insh1,
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i1 => a213s,
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i0 => a29s);
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o25sa : o2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => insh0,
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i1 => a214s,
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i0 => a210s);
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a215sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => f3,
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i1 => insh3,
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i0 => decalga);
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a228sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => f0,
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i1 => insh0,
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i0 => decalda);
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a216sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => a216s,
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i1 => decalda,
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i0 => q3);
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a217sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => a217s,
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i1 => decaln,
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i0 => insh3);
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a218sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => a218s,
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i1 => decalga,
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i0 => insh2);
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a219sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => a219s,
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i1 => decalda,
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i0 => insh3);
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a220sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => a220s,
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i1 => decaln,
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i0 => insh2);
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a221sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => a221s,
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i1 => decalga,
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i0 => insh1);
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a222sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => a222s,
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i1 => decalda,
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i0 => insh2);
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a223sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => a223s,
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i1 => decaln,
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i0 => insh1);
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a224sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => a224s,
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i1 => decalga,
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i0 => insh0);
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a225sa : a2_y
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PORT MAP (
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vss => vss,
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vdd => vdd,
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t => a225s,
|
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i1 => decalda,
|
||||
i0 => insh1);
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a226sa : a2_y
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PORT MAP (
|
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vss => vss,
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vdd => vdd,
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t => a226s,
|
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i1 => decaln,
|
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i0 => insh0);
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a227sa : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => a227s,
|
||||
i1 => decalga,
|
||||
i0 => q0);
|
||||
o31sa : o3_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => shacc3,
|
||||
i2 => a218s,
|
||||
i1 => a217s,
|
||||
i0 => a216s);
|
||||
o32sa : o3_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => shacc2,
|
||||
i2 => a221s,
|
||||
i1 => a220s,
|
||||
i0 => a219s);
|
||||
o33sa : o3_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => shacc1,
|
||||
i2 => a224s,
|
||||
i1 => a223s,
|
||||
i0 => a222s);
|
||||
o34sa : o3_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => shacc0,
|
||||
i2 => a227s,
|
||||
i1 => a226s,
|
||||
i0 => a225s);
|
||||
a229sa : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => ckin,
|
||||
i1 => w,
|
||||
i0 => ck);
|
||||
a230sa : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => scout,
|
||||
i1 => q(3),
|
||||
i0 => test_mode);
|
||||
a231sa : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => a231s,
|
||||
i1 => waccu,
|
||||
i0 => fonc_mode);
|
||||
o26sa : o2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => w,
|
||||
i1 => a231s,
|
||||
i0 => test_mode);
|
||||
m3 : ms2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => q(3),
|
||||
l => ckin,
|
||||
se => test_mode,
|
||||
si => q(2),
|
||||
di => shacc3);
|
||||
m2 : ms2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => q(2),
|
||||
l => ckin,
|
||||
se => test_mode,
|
||||
si => q(1),
|
||||
di => shacc2);
|
||||
m1 : ms2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => q(1),
|
||||
l => ckin,
|
||||
se => test_mode,
|
||||
si => q(0),
|
||||
di => shacc1);
|
||||
m0 : ms2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => q(0),
|
||||
l => ckin,
|
||||
se => test_mode,
|
||||
si => scin,
|
||||
di => shacc0);
|
||||
|
||||
end VST;
|
||||
|
|
@ -1,776 +0,0 @@
|
|||
-- VHDL structural description generated from `alu`
|
||||
-- date : Sun Sep 27 12:27:24 1998
|
||||
|
||||
|
||||
-- Entity Declaration
|
||||
|
||||
ENTITY alu IS
|
||||
PORT (
|
||||
r : in BIT_VECTOR (3 DOWNTO 0); -- r
|
||||
s : in BIT_VECTOR (3 DOWNTO 0); -- s
|
||||
alu_out : out BIT_VECTOR (3 DOWNTO 0); -- alu_out
|
||||
cin : in BIT; -- cin
|
||||
cout : out BIT; -- cout
|
||||
np : out BIT; -- np
|
||||
ng : out BIT; -- ng
|
||||
signe : out BIT; -- signe
|
||||
zero : out BIT; -- zero
|
||||
ovr : out BIT; -- ovr
|
||||
i : in BIT_VECTOR (5 DOWNTO 3); -- i
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END alu;
|
||||
|
||||
-- Architecture Declaration
|
||||
|
||||
ARCHITECTURE VST OF alu IS
|
||||
COMPONENT na3_y
|
||||
port (
|
||||
i0 : in BIT; -- i0
|
||||
i1 : in BIT; -- i1
|
||||
i2 : in BIT; -- i2
|
||||
f : out BIT; -- f
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT nxr2_y
|
||||
port (
|
||||
i0 : in BIT; -- i0
|
||||
i1 : in BIT; -- i1
|
||||
f : out BIT; -- f
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT np1_y
|
||||
port (
|
||||
i : in BIT; -- i
|
||||
f : out BIT; -- f
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT no3_y
|
||||
port (
|
||||
i0 : in BIT; -- i0
|
||||
i1 : in BIT; -- i1
|
||||
i2 : in BIT; -- i2
|
||||
f : out BIT; -- f
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT na2_y
|
||||
port (
|
||||
i0 : in BIT; -- i0
|
||||
i1 : in BIT; -- i1
|
||||
f : out BIT; -- f
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT no2_y
|
||||
port (
|
||||
i0 : in BIT; -- i0
|
||||
i1 : in BIT; -- i1
|
||||
f : out BIT; -- f
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT xr2_y
|
||||
port (
|
||||
i0 : in BIT; -- i0
|
||||
i1 : in BIT; -- i1
|
||||
t : out BIT; -- t
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT n1_y
|
||||
port (
|
||||
i : in BIT; -- i
|
||||
f : out BIT; -- f
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT a2_y
|
||||
port (
|
||||
i0 : in BIT; -- i0
|
||||
i1 : in BIT; -- i1
|
||||
t : out BIT; -- t
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
SIGNAL cout0 : BIT; -- cout0
|
||||
SIGNAL cout1 : BIT; -- cout1
|
||||
SIGNAL cout2 : BIT; -- cout2
|
||||
SIGNAL couta : BIT; -- couta
|
||||
SIGNAL fb0 : BIT; -- fb0
|
||||
SIGNAL fb1 : BIT; -- fb1
|
||||
SIGNAL fb2 : BIT; -- fb2
|
||||
SIGNAL flag : BIT; -- flag
|
||||
SIGNAL flag1 : BIT; -- flag1
|
||||
SIGNAL g : BIT; -- g
|
||||
SIGNAL gb0 : BIT; -- gb0
|
||||
SIGNAL gb1 : BIT; -- gb1
|
||||
SIGNAL gb2 : BIT; -- gb2
|
||||
SIGNAL gb3 : BIT; -- gb3
|
||||
SIGNAL genf : BIT; -- genf
|
||||
SIGNAL n0 : BIT; -- n0
|
||||
SIGNAL n1 : BIT; -- n1
|
||||
SIGNAL n2 : BIT; -- n2
|
||||
SIGNAL n3 : BIT; -- n3
|
||||
SIGNAL n4 : BIT; -- n4
|
||||
SIGNAL na0_csb : BIT; -- na0_csb
|
||||
SIGNAL na1_csb : BIT; -- na1_csb
|
||||
SIGNAL na20 : BIT; -- na20
|
||||
SIGNAL na21 : BIT; -- na21
|
||||
SIGNAL na22 : BIT; -- na22
|
||||
SIGNAL na23 : BIT; -- na23
|
||||
SIGNAL na_csh : BIT; -- na_csh
|
||||
SIGNAL ngb0 : BIT; -- ngb0
|
||||
SIGNAL ngb3 : BIT; -- ngb3
|
||||
SIGNAL ngen : BIT; -- ngen
|
||||
SIGNAL ni5 : BIT; -- ni5
|
||||
SIGNAL nn0 : BIT; -- nn0
|
||||
SIGNAL nn1 : BIT; -- nn1
|
||||
SIGNAL nn3 : BIT; -- nn3
|
||||
SIGNAL no20 : BIT; -- no20
|
||||
SIGNAL no21 : BIT; -- no21
|
||||
SIGNAL no22 : BIT; -- no22
|
||||
SIGNAL no23 : BIT; -- no23
|
||||
SIGNAL no2_csh : BIT; -- no2_csh
|
||||
SIGNAL no30 : BIT; -- no30
|
||||
SIGNAL no30_csh : BIT; -- no30_csh
|
||||
SIGNAL no31 : BIT; -- no31
|
||||
SIGNAL no31_csh : BIT; -- no31_csh
|
||||
SIGNAL no32 : BIT; -- no32
|
||||
SIGNAL no32_csh : BIT; -- no32_csh
|
||||
SIGNAL no33 : BIT; -- no33
|
||||
SIGNAL no40 : BIT; -- no40
|
||||
SIGNAL no41 : BIT; -- no41
|
||||
SIGNAL no42 : BIT; -- no42
|
||||
SIGNAL no43 : BIT; -- no43
|
||||
SIGNAL not0 : BIT; -- not0
|
||||
SIGNAL not1 : BIT; -- not1
|
||||
SIGNAL not2 : BIT; -- not2
|
||||
SIGNAL not3 : BIT; -- not3
|
||||
SIGNAL npb0 : BIT; -- npb0
|
||||
SIGNAL nprop : BIT; -- nprop
|
||||
SIGNAL p : BIT; -- p
|
||||
SIGNAL pb0 : BIT; -- pb0
|
||||
SIGNAL pb1 : BIT; -- pb1
|
||||
SIGNAL pb2 : BIT; -- pb2
|
||||
SIGNAL pb3 : BIT; -- pb3
|
||||
SIGNAL propf : BIT; -- propf
|
||||
SIGNAL signea : BIT; -- signea
|
||||
SIGNAL x00 : BIT; -- x00
|
||||
SIGNAL x01 : BIT; -- x01
|
||||
SIGNAL x02 : BIT; -- x02
|
||||
SIGNAL x03 : BIT; -- x03
|
||||
SIGNAL x10 : BIT; -- x10
|
||||
SIGNAL x11 : BIT; -- x11
|
||||
SIGNAL x12 : BIT; -- x12
|
||||
SIGNAL x13 : BIT; -- x13
|
||||
SIGNAL x20 : BIT; -- x20
|
||||
SIGNAL x21 : BIT; -- x21
|
||||
SIGNAL x22 : BIT; -- x22
|
||||
SIGNAL x23 : BIT; -- x23
|
||||
|
||||
BEGIN
|
||||
|
||||
xor0_a0 : xr2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => x00,
|
||||
i1 => n0,
|
||||
i0 => r(0));
|
||||
xor1_a0 : xr2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => x10,
|
||||
i1 => n1,
|
||||
i0 => s(0));
|
||||
nand0_a0 : na2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => gb0,
|
||||
i1 => x10,
|
||||
i0 => x00);
|
||||
nor1_a0 : no2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => pb0,
|
||||
i1 => x10,
|
||||
i0 => x00);
|
||||
nand1_a0 : na2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => cout0,
|
||||
i1 => na20,
|
||||
i0 => gb0);
|
||||
not_a0 : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => not0,
|
||||
i => pb0);
|
||||
nand2_a0 : na2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => na20,
|
||||
i1 => cin,
|
||||
i0 => not0);
|
||||
nor2_a0 : no2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => no20,
|
||||
i1 => gb0,
|
||||
i0 => n2);
|
||||
nor3_a0 : no2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => no30,
|
||||
i1 => pb0,
|
||||
i0 => n3);
|
||||
nor4_a0 : no2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => no40,
|
||||
i1 => cin,
|
||||
i0 => n4);
|
||||
xor2_a0 : xr2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => x20,
|
||||
i1 => no30,
|
||||
i0 => no20);
|
||||
xor3_a0 : xr2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => fb0,
|
||||
i1 => no40,
|
||||
i0 => x20);
|
||||
xor0_a1 : xr2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => x01,
|
||||
i1 => n0,
|
||||
i0 => r(1));
|
||||
xor1_a1 : xr2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => x11,
|
||||
i1 => n1,
|
||||
i0 => s(1));
|
||||
nand0_a1 : na2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => gb1,
|
||||
i1 => x11,
|
||||
i0 => x01);
|
||||
nor1_a1 : no2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => pb1,
|
||||
i1 => x11,
|
||||
i0 => x01);
|
||||
nand1_a1 : na2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => cout1,
|
||||
i1 => na21,
|
||||
i0 => gb1);
|
||||
not_a1 : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => not1,
|
||||
i => pb1);
|
||||
nand2_a1 : na2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => na21,
|
||||
i1 => cout0,
|
||||
i0 => not1);
|
||||
nor2_a1 : no2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => no21,
|
||||
i1 => gb1,
|
||||
i0 => n2);
|
||||
nor3_a1 : no2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => no31,
|
||||
i1 => pb1,
|
||||
i0 => n3);
|
||||
nor4_a1 : no2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => no41,
|
||||
i1 => cout0,
|
||||
i0 => n4);
|
||||
xor2_a1 : xr2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => x21,
|
||||
i1 => no31,
|
||||
i0 => no21);
|
||||
xor3_a1 : xr2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => fb1,
|
||||
i1 => no41,
|
||||
i0 => x21);
|
||||
xor0_a2 : xr2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => x02,
|
||||
i1 => n0,
|
||||
i0 => r(2));
|
||||
xor1_a2 : xr2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => x12,
|
||||
i1 => n1,
|
||||
i0 => s(2));
|
||||
nand0_a2 : na2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => gb2,
|
||||
i1 => x12,
|
||||
i0 => x02);
|
||||
nor1_a2 : no2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => pb2,
|
||||
i1 => x12,
|
||||
i0 => x02);
|
||||
nand1_a2 : na2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => cout2,
|
||||
i1 => na22,
|
||||
i0 => gb2);
|
||||
not_a2 : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => not2,
|
||||
i => pb2);
|
||||
nand2_a2 : na2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => na22,
|
||||
i1 => cout1,
|
||||
i0 => not2);
|
||||
nor2_a2 : no2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => no22,
|
||||
i1 => gb2,
|
||||
i0 => n2);
|
||||
nor3_a2 : no2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => no32,
|
||||
i1 => pb2,
|
||||
i0 => n3);
|
||||
nor4_a2 : no2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => no42,
|
||||
i1 => cout1,
|
||||
i0 => n4);
|
||||
xor2_a2 : xr2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => x22,
|
||||
i1 => no32,
|
||||
i0 => no22);
|
||||
xor3_a2 : xr2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => fb2,
|
||||
i1 => no42,
|
||||
i0 => x22);
|
||||
xor0_a3 : xr2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => x03,
|
||||
i1 => n0,
|
||||
i0 => r(3));
|
||||
xor1_a3 : xr2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => x13,
|
||||
i1 => n1,
|
||||
i0 => s(3));
|
||||
nand0_a3 : na2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => gb3,
|
||||
i1 => x13,
|
||||
i0 => x03);
|
||||
nor1_a3 : no2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => pb3,
|
||||
i1 => x13,
|
||||
i0 => x03);
|
||||
nand1_a3 : na2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => couta,
|
||||
i1 => na23,
|
||||
i0 => gb3);
|
||||
not_a3 : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => not3,
|
||||
i => pb3);
|
||||
nand2_a3 : na2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => na23,
|
||||
i1 => cout2,
|
||||
i0 => not3);
|
||||
nor2_a3 : no2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => no23,
|
||||
i1 => gb3,
|
||||
i0 => n2);
|
||||
nor3_a3 : no2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => no33,
|
||||
i1 => pb3,
|
||||
i0 => n3);
|
||||
nor4_a3 : no2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => no43,
|
||||
i1 => cout2,
|
||||
i0 => n4);
|
||||
xor2_a3 : xr2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => x23,
|
||||
i1 => no33,
|
||||
i0 => no23);
|
||||
xor3_a3 : xr2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => signea,
|
||||
i1 => no43,
|
||||
i0 => x23);
|
||||
not5_d : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => ni5,
|
||||
i => i(5));
|
||||
nand3_d : na3_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => nn3,
|
||||
i2 => ni5,
|
||||
i1 => i(4),
|
||||
i0 => i(3));
|
||||
nor_d : no2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => n2,
|
||||
i1 => ni5,
|
||||
i0 => i(4));
|
||||
nxor4_d : nxr2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => nn1,
|
||||
i1 => i(5),
|
||||
i0 => i(4));
|
||||
nxor3_d : nxr2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => nn0,
|
||||
i1 => i(5),
|
||||
i0 => i(3));
|
||||
nand_d : na2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => n4,
|
||||
i1 => nn3,
|
||||
i0 => ni5);
|
||||
not0_d : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => n3,
|
||||
i => nn3);
|
||||
notp4_d : np1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => n1,
|
||||
i => nn1);
|
||||
notp3_d : np1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => n0,
|
||||
i => nn0);
|
||||
naflag1 : na2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => flag1,
|
||||
i1 => i(3),
|
||||
i0 => i(4));
|
||||
naflag : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => flag,
|
||||
i1 => flag1,
|
||||
i0 => ni5);
|
||||
not0_csh : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => npb0,
|
||||
i => pb0);
|
||||
not1_csh : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => ngb0,
|
||||
i => gb0);
|
||||
not2_csh : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => ngb3,
|
||||
i => gb3);
|
||||
npf : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => propf,
|
||||
i => nprop);
|
||||
npg : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => genf,
|
||||
i => ngen);
|
||||
npflag : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => p,
|
||||
i1 => flag,
|
||||
i0 => propf);
|
||||
ngflag : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => g,
|
||||
i1 => flag,
|
||||
i0 => genf);
|
||||
nor0_csh : no3_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => no30_csh,
|
||||
i2 => pb1,
|
||||
i1 => pb2,
|
||||
i0 => pb3);
|
||||
nor1_csh : no3_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => no31_csh,
|
||||
i2 => pb3,
|
||||
i1 => pb2,
|
||||
i0 => gb1);
|
||||
nor2_csh : no3_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => no32_csh,
|
||||
i2 => ngb3,
|
||||
i1 => no31_csh,
|
||||
i0 => no2_csh);
|
||||
nand0_csh : na2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => nprop,
|
||||
i1 => no30_csh,
|
||||
i0 => npb0);
|
||||
nand1_csh : na2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => na_csh,
|
||||
i1 => no30_csh,
|
||||
i0 => ngb0);
|
||||
nor_csh : no2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => no2_csh,
|
||||
i1 => pb3,
|
||||
i0 => gb2);
|
||||
and_csh : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => ngen,
|
||||
i1 => no32_csh,
|
||||
i0 => na_csh);
|
||||
nand0_csb : na2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => na0_csb,
|
||||
i1 => fb1,
|
||||
i0 => fb0);
|
||||
nand1_csb : na2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => na1_csb,
|
||||
i1 => signea,
|
||||
i0 => fb2);
|
||||
nor_csb : no2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => zero,
|
||||
i1 => na1_csb,
|
||||
i0 => na0_csb);
|
||||
xor_csb : xr2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => ovr,
|
||||
i1 => couta,
|
||||
i0 => cout2);
|
||||
not0_csb : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => alu_out(0),
|
||||
i => fb0);
|
||||
not1_csb : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => alu_out(1),
|
||||
i => fb1);
|
||||
not2_csb : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => alu_out(2),
|
||||
i => fb2);
|
||||
not3_csb : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => alu_out(3),
|
||||
i => signea);
|
||||
not4_csb : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => signe,
|
||||
i => signea);
|
||||
not0_p : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => np,
|
||||
i => p);
|
||||
not0_g : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => ng,
|
||||
i => g);
|
||||
coutflag : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => cout,
|
||||
i1 => flag,
|
||||
i0 => couta);
|
||||
|
||||
end VST;
|
||||
|
|
@ -1 +0,0 @@
|
|||
asimut_first done
|
||||
|
|
@ -1 +0,0 @@
|
|||
asimut_vbe done
|
||||
|
|
@ -1 +0,0 @@
|
|||
asimut_vst done
|
||||
|
|
@ -236,10 +236,10 @@ LOINS ("a2_y","a231sa","fonc_mode","waccu","a231s","vdd","vss",0);
|
|||
LOINS ("o2_y","o26sa","test_mode","a231s","w","vdd","vss",0);
|
||||
|
||||
|
||||
LOINS ("ms2_y","m3","shacc3","q[2]","test_mode","ckin","q[3]","vdd","vss",0);
|
||||
LOINS ("ms2_y","m2","shacc2","q[1]","test_mode","ckin","q[2]","vdd","vss",0);
|
||||
LOINS ("ms2_y","m1","shacc1","q[0]","test_mode","ckin","q[1]","vdd","vss",0);
|
||||
LOINS ("ms2_y","m0","shacc0","scin","test_mode","ckin","q[0]","vdd","vss",0);
|
||||
LOINS ("ms2dp2_y","m3","shacc3","q[2]","test_mode","ckin","q[3]","vdd","vss",0);
|
||||
LOINS ("ms2dp2_y","m2","shacc2","q[1]","test_mode","ckin","q[2]","vdd","vss",0);
|
||||
LOINS ("ms2dp2_y","m1","shacc1","q[0]","test_mode","ckin","q[1]","vdd","vss",0);
|
||||
LOINS ("ms2dp2_y","m0","shacc0","scin","test_mode","ckin","q[0]","vdd","vss",0);
|
||||
|
||||
SAVE_LOFIG();
|
||||
|
||||
|
|
@ -522,76 +522,76 @@ LOINS ("a2_y","c1","enable","b1","ck1","vdd","vss",0);
|
|||
/* building of the "memory-space" */
|
||||
|
||||
/* bit slice 3 */
|
||||
LOINS ("ms_y","m_16_3","shram3","ck16","s316","vdd","vss",0);
|
||||
LOINS ("ms_y","m_15_3","shram3","ck15","s315","vdd","vss",0);
|
||||
LOINS ("ms_y","m_14_3","shram3","ck14","s314","vdd","vss",0);
|
||||
LOINS ("ms_y","m_13_3","shram3","ck13","s313","vdd","vss",0);
|
||||
LOINS ("ms_y","m_12_3","shram3","ck12","s312","vdd","vss",0);
|
||||
LOINS ("ms_y","m_11_3","shram3","ck11","s311","vdd","vss",0);
|
||||
LOINS ("ms_y","m_10_3","shram3","ck10","s310","vdd","vss",0);
|
||||
LOINS ("ms_y","m_9_3","shram3","ck9","s39","vdd","vss",0);
|
||||
LOINS ("ms_y","m_8_3","shram3","ck8","s38","vdd","vss",0);
|
||||
LOINS ("ms_y","m_7_3","shram3","ck7","s37","vdd","vss",0);
|
||||
LOINS ("ms_y","m_6_3","shram3","ck6","s36","vdd","vss",0);
|
||||
LOINS ("ms_y","m_5_3","shram3","ck5","s35","vdd","vss",0);
|
||||
LOINS ("ms_y","m_4_3","shram3","ck4","s34","vdd","vss",0);
|
||||
LOINS ("ms_y","m_3_3","shram3","ck3","s33","vdd","vss",0);
|
||||
LOINS ("ms_y","m_2_3","shram3","ck2","s32","vdd","vss",0);
|
||||
LOINS ("ms_y","m_1_3","shram3","ck1","s31","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_16_3","shram3","ck16","s316","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_15_3","shram3","ck15","s315","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_14_3","shram3","ck14","s314","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_13_3","shram3","ck13","s313","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_12_3","shram3","ck12","s312","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_11_3","shram3","ck11","s311","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_10_3","shram3","ck10","s310","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_9_3","shram3","ck9","s39","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_8_3","shram3","ck8","s38","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_7_3","shram3","ck7","s37","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_6_3","shram3","ck6","s36","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_5_3","shram3","ck5","s35","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_4_3","shram3","ck4","s34","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_3_3","shram3","ck3","s33","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_2_3","shram3","ck2","s32","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_1_3","shram3","ck1","s31","vdd","vss",0);
|
||||
|
||||
/* bit slice 2 */
|
||||
LOINS ("ms_y","m_16_2","shram2","ck16","s216","vdd","vss",0);
|
||||
LOINS ("ms_y","m_15_2","shram2","ck15","s215","vdd","vss",0);
|
||||
LOINS ("ms_y","m_14_2","shram2","ck14","s214","vdd","vss",0);
|
||||
LOINS ("ms_y","m_13_2","shram2","ck13","s213","vdd","vss",0);
|
||||
LOINS ("ms_y","m_12_2","shram2","ck12","s212","vdd","vss",0);
|
||||
LOINS ("ms_y","m_11_2","shram2","ck11","s211","vdd","vss",0);
|
||||
LOINS ("ms_y","m_10_2","shram2","ck10","s210","vdd","vss",0);
|
||||
LOINS ("ms_y","m_9_2","shram2","ck9","s29","vdd","vss",0);
|
||||
LOINS ("ms_y","m_8_2","shram2","ck8","s28","vdd","vss",0);
|
||||
LOINS ("ms_y","m_7_2","shram2","ck7","s27","vdd","vss",0);
|
||||
LOINS ("ms_y","m_6_2","shram2","ck6","s26","vdd","vss",0);
|
||||
LOINS ("ms_y","m_5_2","shram2","ck5","s25","vdd","vss",0);
|
||||
LOINS ("ms_y","m_4_2","shram2","ck4","s24","vdd","vss",0);
|
||||
LOINS ("ms_y","m_3_2","shram2","ck3","s23","vdd","vss",0);
|
||||
LOINS ("ms_y","m_2_2","shram2","ck2","s22","vdd","vss",0);
|
||||
LOINS ("ms_y","m_1_2","shram2","ck1","s21","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_16_2","shram2","ck16","s216","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_15_2","shram2","ck15","s215","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_14_2","shram2","ck14","s214","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_13_2","shram2","ck13","s213","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_12_2","shram2","ck12","s212","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_11_2","shram2","ck11","s211","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_10_2","shram2","ck10","s210","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_9_2","shram2","ck9","s29","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_8_2","shram2","ck8","s28","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_7_2","shram2","ck7","s27","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_6_2","shram2","ck6","s26","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_5_2","shram2","ck5","s25","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_4_2","shram2","ck4","s24","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_3_2","shram2","ck3","s23","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_2_2","shram2","ck2","s22","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_1_2","shram2","ck1","s21","vdd","vss",0);
|
||||
|
||||
/* bit slice 1 */
|
||||
LOINS ("ms_y","m_16_1","shram1","ck16","s116","vdd","vss",0);
|
||||
LOINS ("ms_y","m_15_1","shram1","ck15","s115","vdd","vss",0);
|
||||
LOINS ("ms_y","m_14_1","shram1","ck14","s114","vdd","vss",0);
|
||||
LOINS ("ms_y","m_13_1","shram1","ck13","s113","vdd","vss",0);
|
||||
LOINS ("ms_y","m_12_1","shram1","ck12","s112","vdd","vss",0);
|
||||
LOINS ("ms_y","m_11_1","shram1","ck11","s111","vdd","vss",0);
|
||||
LOINS ("ms_y","m_10_1","shram1","ck10","s110","vdd","vss",0);
|
||||
LOINS ("ms_y","m_9_1","shram1","ck9","s19","vdd","vss",0);
|
||||
LOINS ("ms_y","m_8_1","shram1","ck8","s18","vdd","vss",0);
|
||||
LOINS ("ms_y","m_7_1","shram1","ck7","s17","vdd","vss",0);
|
||||
LOINS ("ms_y","m_6_1","shram1","ck6","s16","vdd","vss",0);
|
||||
LOINS ("ms_y","m_5_1","shram1","ck5","s15","vdd","vss",0);
|
||||
LOINS ("ms_y","m_4_1","shram1","ck4","s14","vdd","vss",0);
|
||||
LOINS ("ms_y","m_3_1","shram1","ck3","s13","vdd","vss",0);
|
||||
LOINS ("ms_y","m_2_1","shram1","ck2","s12","vdd","vss",0);
|
||||
LOINS ("ms_y","m_1_1","shram1","ck1","s11","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_16_1","shram1","ck16","s116","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_15_1","shram1","ck15","s115","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_14_1","shram1","ck14","s114","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_13_1","shram1","ck13","s113","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_12_1","shram1","ck12","s112","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_11_1","shram1","ck11","s111","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_10_1","shram1","ck10","s110","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_9_1","shram1","ck9","s19","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_8_1","shram1","ck8","s18","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_7_1","shram1","ck7","s17","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_6_1","shram1","ck6","s16","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_5_1","shram1","ck5","s15","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_4_1","shram1","ck4","s14","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_3_1","shram1","ck3","s13","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_2_1","shram1","ck2","s12","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_1_1","shram1","ck1","s11","vdd","vss",0);
|
||||
|
||||
/* bit slice 0 */
|
||||
LOINS ("ms_y","m_16_0","shram0","ck16","s016","vdd","vss",0);
|
||||
LOINS ("ms_y","m_15_0","shram0","ck15","s015","vdd","vss",0);
|
||||
LOINS ("ms_y","m_14_0","shram0","ck14","s014","vdd","vss",0);
|
||||
LOINS ("ms_y","m_13_0","shram0","ck13","s013","vdd","vss",0);
|
||||
LOINS ("ms_y","m_12_0","shram0","ck12","s012","vdd","vss",0);
|
||||
LOINS ("ms_y","m_11_0","shram0","ck11","s011","vdd","vss",0);
|
||||
LOINS ("ms_y","m_10_0","shram0","ck10","s010","vdd","vss",0);
|
||||
LOINS ("ms_y","m_9_0","shram0","ck9","s09","vdd","vss",0);
|
||||
LOINS ("ms_y","m_8_0","shram0","ck8","s08","vdd","vss",0);
|
||||
LOINS ("ms_y","m_7_0","shram0","ck7","s07","vdd","vss",0);
|
||||
LOINS ("ms_y","m_6_0","shram0","ck6","s06","vdd","vss",0);
|
||||
LOINS ("ms_y","m_5_0","shram0","ck5","s05","vdd","vss",0);
|
||||
LOINS ("ms_y","m_4_0","shram0","ck4","s04","vdd","vss",0);
|
||||
LOINS ("ms_y","m_3_0","shram0","ck3","s03","vdd","vss",0);
|
||||
LOINS ("ms_y","m_2_0","shram0","ck2","s02","vdd","vss",0);
|
||||
LOINS ("ms_y","m_1_0","shram0","ck1","s01","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_16_0","shram0","ck16","s016","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_15_0","shram0","ck15","s015","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_14_0","shram0","ck14","s014","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_13_0","shram0","ck13","s013","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_12_0","shram0","ck12","s012","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_11_0","shram0","ck11","s011","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_10_0","shram0","ck10","s010","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_9_0","shram0","ck9","s09","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_8_0","shram0","ck8","s08","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_7_0","shram0","ck7","s07","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_6_0","shram0","ck6","s06","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_5_0","shram0","ck5","s05","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_4_0","shram0","ck4","s04","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_3_0","shram0","ck3","s03","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_2_0","shram0","ck2","s02","vdd","vss",0);
|
||||
LOINS ("msdp2_y","m_1_0","shram0","ck1","s01","vdd","vss",0);
|
||||
|
||||
/* reading of the a-addressed word */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,708 +0,0 @@
|
|||
-- VHDL structural description generated from `chip`
|
||||
-- date : Sun Sep 27 12:27:25 1998
|
||||
|
||||
|
||||
-- Entity Declaration
|
||||
|
||||
ENTITY chip IS
|
||||
PORT (
|
||||
a : in BIT_VECTOR (3 DOWNTO 0); -- a
|
||||
b : in BIT_VECTOR (3 DOWNTO 0); -- b
|
||||
d : in BIT_VECTOR (3 DOWNTO 0); -- d
|
||||
cin : linkage BIT; -- cin
|
||||
cout : linkage BIT; -- cout
|
||||
np : out BIT; -- np
|
||||
ng : out BIT; -- ng
|
||||
signe : linkage BIT; -- signe
|
||||
zero : out BIT; -- zero
|
||||
ovr : out BIT; -- ovr
|
||||
i : in BIT_VECTOR (8 DOWNTO 0); -- i
|
||||
q0 : linkage BIT; -- q0
|
||||
q3 : linkage BIT; -- q3
|
||||
r0 : linkage BIT; -- r0
|
||||
r3 : linkage BIT; -- r3
|
||||
noe : in BIT; -- noe
|
||||
fonc : in BIT; -- fonc
|
||||
test : in BIT; -- test
|
||||
scin : in BIT; -- scin
|
||||
scout : out BIT; -- scout
|
||||
cke : in BIT; -- cke
|
||||
vdde : in BIT; -- vdde
|
||||
vsse : in BIT; -- vsse
|
||||
vddi : in BIT; -- vddi
|
||||
vssi : in BIT; -- vssi
|
||||
y : linkage BIT_VECTOR (3 DOWNTO 0) -- y
|
||||
);
|
||||
END chip;
|
||||
|
||||
-- Architecture Declaration
|
||||
|
||||
ARCHITECTURE VST OF chip IS
|
||||
COMPONENT pvdde_sp
|
||||
port (
|
||||
ck : in BIT; -- ck
|
||||
vdde : in BIT; -- vdde
|
||||
vddi : in BIT; -- vddi
|
||||
vsse : in BIT; -- vsse
|
||||
vssi : in BIT -- vssi
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT pvsse_sp
|
||||
port (
|
||||
ck : in BIT; -- ck
|
||||
vdde : in BIT; -- vdde
|
||||
vddi : in BIT; -- vddi
|
||||
vsse : in BIT; -- vsse
|
||||
vssi : in BIT -- vssi
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT pvsseck_sp
|
||||
port (
|
||||
cko : linkage BIT; -- cko
|
||||
ck : in BIT; -- ck
|
||||
vdde : in BIT; -- vdde
|
||||
vddi : in BIT; -- vddi
|
||||
vsse : in BIT; -- vsse
|
||||
vssi : in BIT -- vssi
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT pvddi_sp
|
||||
port (
|
||||
ck : in BIT; -- ck
|
||||
vdde : in BIT; -- vdde
|
||||
vddi : in BIT; -- vddi
|
||||
vsse : in BIT; -- vsse
|
||||
vssi : in BIT -- vssi
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT pvssi_sp
|
||||
port (
|
||||
ck : in BIT; -- ck
|
||||
vdde : in BIT; -- vdde
|
||||
vddi : in BIT; -- vddi
|
||||
vsse : in BIT; -- vsse
|
||||
vssi : in BIT -- vssi
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT po_sp
|
||||
port (
|
||||
i : in BIT; -- i
|
||||
pad : out BIT; -- pad
|
||||
ck : in BIT; -- ck
|
||||
vdde : in BIT; -- vdde
|
||||
vddi : in BIT; -- vddi
|
||||
vsse : in BIT; -- vsse
|
||||
vssi : in BIT -- vssi
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT piot_sp
|
||||
port (
|
||||
i : in BIT; -- i
|
||||
b : in BIT; -- b
|
||||
t : out BIT; -- t
|
||||
pad : linkage BIT; -- pad
|
||||
ck : in BIT; -- ck
|
||||
vdde : in BIT; -- vdde
|
||||
vddi : in BIT; -- vddi
|
||||
vsse : in BIT; -- vsse
|
||||
vssi : in BIT -- vssi
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT pi_sp
|
||||
port (
|
||||
pad : in BIT; -- pad
|
||||
t : out BIT; -- t
|
||||
ck : in BIT; -- ck
|
||||
vdde : in BIT; -- vdde
|
||||
vddi : in BIT; -- vddi
|
||||
vsse : in BIT; -- vsse
|
||||
vssi : in BIT -- vssi
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT pck_sp
|
||||
port (
|
||||
pad : in BIT; -- pad
|
||||
ck : out BIT; -- ck
|
||||
vdde : in BIT; -- vdde
|
||||
vddi : in BIT; -- vddi
|
||||
vsse : in BIT; -- vsse
|
||||
vssi : in BIT -- vssi
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT pot_sp
|
||||
port (
|
||||
i : in BIT; -- i
|
||||
b : in BIT; -- b
|
||||
pad : linkage BIT; -- pad
|
||||
ck : in BIT; -- ck
|
||||
vdde : in BIT; -- vdde
|
||||
vddi : in BIT; -- vddi
|
||||
vsse : in BIT; -- vsse
|
||||
vssi : in BIT -- vssi
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT heart
|
||||
port (
|
||||
a : in BIT_VECTOR(3 DOWNTO 0); -- a
|
||||
b : in BIT_VECTOR(3 DOWNTO 0); -- b
|
||||
d : in BIT_VECTOR(3 DOWNTO 0); -- d
|
||||
cin : linkage BIT; -- cin
|
||||
cout : linkage BIT; -- cout
|
||||
np : out BIT; -- np
|
||||
ng : out BIT; -- ng
|
||||
signe : linkage BIT; -- signe
|
||||
zero : out BIT; -- zero
|
||||
ovr : out BIT; -- ovr
|
||||
i : in BIT_VECTOR(8 DOWNTO 0); -- i
|
||||
q0 : in BIT; -- q0
|
||||
q3 : in BIT; -- q3
|
||||
f0 : out BIT; -- f0
|
||||
f3 : out BIT; -- f3
|
||||
fonc : in BIT; -- fonc
|
||||
test : in BIT; -- test
|
||||
scin : in BIT; -- scin
|
||||
scout : out BIT; -- scout
|
||||
decald : out BIT; -- decald
|
||||
decalg : out BIT; -- decalg
|
||||
decaldr : out BIT; -- decaldr
|
||||
decalgr : out BIT; -- decalgr
|
||||
r0 : in BIT; -- r0
|
||||
r3 : in BIT; -- r3
|
||||
s0 : out BIT; -- s0
|
||||
s3 : out BIT; -- s3
|
||||
ck : in BIT; -- ck
|
||||
y : out BIT_VECTOR(3 DOWNTO 0); -- y
|
||||
noe : in BIT; -- noe
|
||||
oe : out BIT; -- oe
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
SIGNAL ai_0 : BIT; -- ai 0
|
||||
SIGNAL ai_1 : BIT; -- ai 1
|
||||
SIGNAL ai_2 : BIT; -- ai 2
|
||||
SIGNAL ai_3 : BIT; -- ai 3
|
||||
SIGNAL bi_0 : BIT; -- bi 0
|
||||
SIGNAL bi_1 : BIT; -- bi 1
|
||||
SIGNAL bi_2 : BIT; -- bi 2
|
||||
SIGNAL bi_3 : BIT; -- bi 3
|
||||
SIGNAL cini : BIT; -- cini
|
||||
SIGNAL ck : BIT; -- ck
|
||||
SIGNAL cko : BIT; -- cko
|
||||
SIGNAL coutc : BIT; -- coutc
|
||||
SIGNAL decaldc : BIT; -- decaldc
|
||||
SIGNAL decaldrc : BIT; -- decaldrc
|
||||
SIGNAL decalgc : BIT; -- decalgc
|
||||
SIGNAL decalgrc : BIT; -- decalgrc
|
||||
SIGNAL di_0 : BIT; -- di 0
|
||||
SIGNAL di_1 : BIT; -- di 1
|
||||
SIGNAL di_2 : BIT; -- di 2
|
||||
SIGNAL di_3 : BIT; -- di 3
|
||||
SIGNAL f0c : BIT; -- f0c
|
||||
SIGNAL f3c : BIT; -- f3c
|
||||
SIGNAL fonci : BIT; -- fonci
|
||||
SIGNAL ii_0 : BIT; -- ii 0
|
||||
SIGNAL ii_1 : BIT; -- ii 1
|
||||
SIGNAL ii_2 : BIT; -- ii 2
|
||||
SIGNAL ii_3 : BIT; -- ii 3
|
||||
SIGNAL ii_4 : BIT; -- ii 4
|
||||
SIGNAL ii_5 : BIT; -- ii 5
|
||||
SIGNAL ii_6 : BIT; -- ii 6
|
||||
SIGNAL ii_7 : BIT; -- ii 7
|
||||
SIGNAL ii_8 : BIT; -- ii 8
|
||||
SIGNAL ngc : BIT; -- ngc
|
||||
SIGNAL noei : BIT; -- noei
|
||||
SIGNAL npc : BIT; -- npc
|
||||
SIGNAL oec : BIT; -- oec
|
||||
SIGNAL ovrc : BIT; -- ovrc
|
||||
SIGNAL q0i : BIT; -- q0i
|
||||
SIGNAL q3i : BIT; -- q3i
|
||||
SIGNAL r0i : BIT; -- r0i
|
||||
SIGNAL r3i : BIT; -- r3i
|
||||
SIGNAL s0c : BIT; -- s0c
|
||||
SIGNAL s3c : BIT; -- s3c
|
||||
SIGNAL scini : BIT; -- scini
|
||||
SIGNAL scoutc : BIT; -- scoutc
|
||||
SIGNAL signec : BIT; -- signec
|
||||
SIGNAL testi : BIT; -- testi
|
||||
SIGNAL yc_0 : BIT; -- yc 0
|
||||
SIGNAL yc_1 : BIT; -- yc 1
|
||||
SIGNAL yc_2 : BIT; -- yc 2
|
||||
SIGNAL yc_3 : BIT; -- yc 3
|
||||
SIGNAL zeroc : BIT; -- zeroc
|
||||
|
||||
BEGIN
|
||||
|
||||
vdde_p0 : pvdde_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck);
|
||||
vsse_p0 : pvsse_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck);
|
||||
vsse_ck : pvsseck_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
cko => cko);
|
||||
vddi_p1 : pvddi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck);
|
||||
vssi_p1 : pvssi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck);
|
||||
a3 : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => ai_3,
|
||||
pad => a(3));
|
||||
a2 : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => ai_2,
|
||||
pad => a(2));
|
||||
a1 : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => ai_1,
|
||||
pad => a(1));
|
||||
a0 : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => ai_0,
|
||||
pad => a(0));
|
||||
b3 : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => bi_3,
|
||||
pad => b(3));
|
||||
b2 : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => bi_2,
|
||||
pad => b(2));
|
||||
b1 : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => bi_1,
|
||||
pad => b(1));
|
||||
b0 : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => bi_0,
|
||||
pad => b(0));
|
||||
d3 : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => di_3,
|
||||
pad => d(3));
|
||||
d2 : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => di_2,
|
||||
pad => d(2));
|
||||
d1 : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => di_1,
|
||||
pad => d(1));
|
||||
d0 : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => di_0,
|
||||
pad => d(0));
|
||||
cin : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => cini,
|
||||
pad => cin);
|
||||
scout : po_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
pad => scout,
|
||||
i => scoutc);
|
||||
cout : po_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
pad => cout,
|
||||
i => coutc);
|
||||
np : po_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
pad => np,
|
||||
i => npc);
|
||||
ng : po_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
pad => ng,
|
||||
i => ngc);
|
||||
signe : po_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
pad => signe,
|
||||
i => signec);
|
||||
zero : po_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
pad => zero,
|
||||
i => zeroc);
|
||||
ovr : po_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
pad => ovr,
|
||||
i => ovrc);
|
||||
q0 : piot_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
pad => q0,
|
||||
t => q0i,
|
||||
b => decaldc,
|
||||
i => f0c);
|
||||
q3 : piot_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
pad => q3,
|
||||
t => q3i,
|
||||
b => decalgc,
|
||||
i => f3c);
|
||||
r0 : piot_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
pad => r0,
|
||||
t => r0i,
|
||||
b => decaldrc,
|
||||
i => s0c);
|
||||
r3 : piot_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
pad => r3,
|
||||
t => r3i,
|
||||
b => decalgrc,
|
||||
i => s3c);
|
||||
noe : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => noei,
|
||||
pad => noe);
|
||||
fonc : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => fonci,
|
||||
pad => fonc);
|
||||
test : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => testi,
|
||||
pad => test);
|
||||
scin : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => scini,
|
||||
pad => scin);
|
||||
i8 : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => ii_8,
|
||||
pad => i(8));
|
||||
i7 : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => ii_7,
|
||||
pad => i(7));
|
||||
i6 : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => ii_6,
|
||||
pad => i(6));
|
||||
i5 : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => ii_5,
|
||||
pad => i(5));
|
||||
i4 : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => ii_4,
|
||||
pad => i(4));
|
||||
i3 : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => ii_3,
|
||||
pad => i(3));
|
||||
i2 : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => ii_2,
|
||||
pad => i(2));
|
||||
i1 : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => ii_1,
|
||||
pad => i(1));
|
||||
i0 : pi_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
t => ii_0,
|
||||
pad => i(0));
|
||||
ck : pck_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
pad => cke);
|
||||
y0 : pot_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
pad => y(0),
|
||||
b => oec,
|
||||
i => yc_0);
|
||||
y1 : pot_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
pad => y(1),
|
||||
b => oec,
|
||||
i => yc_1);
|
||||
y2 : pot_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
pad => y(2),
|
||||
b => oec,
|
||||
i => yc_2);
|
||||
y3 : pot_sp
|
||||
PORT MAP (
|
||||
vssi => vssi,
|
||||
vsse => vsse,
|
||||
vddi => vddi,
|
||||
vdde => vdde,
|
||||
ck => ck,
|
||||
pad => y(3),
|
||||
b => oec,
|
||||
i => yc_3);
|
||||
heart : heart
|
||||
PORT MAP (
|
||||
vss => vssi,
|
||||
vdd => vddi,
|
||||
oe => oec,
|
||||
noe => noei,
|
||||
y => yc_3& yc_2& yc_1& yc_0,
|
||||
ck => cko,
|
||||
s3 => s3c,
|
||||
s0 => s0c,
|
||||
r3 => r3i,
|
||||
r0 => r0i,
|
||||
decalgr => decalgrc,
|
||||
decaldr => decaldrc,
|
||||
decalg => decalgc,
|
||||
decald => decaldc,
|
||||
scout => scoutc,
|
||||
scin => scini,
|
||||
test => testi,
|
||||
fonc => fonci,
|
||||
f3 => f3c,
|
||||
f0 => f0c,
|
||||
q3 => q3i,
|
||||
q0 => q0i,
|
||||
i => ii_8& ii_7& ii_6& ii_5& ii_4& ii_3& ii_2& ii_1& ii_0,
|
||||
ovr => ovrc,
|
||||
zero => zeroc,
|
||||
signe => signec,
|
||||
ng => ngc,
|
||||
np => npc,
|
||||
cout => coutc,
|
||||
cin => cini,
|
||||
d => di_3& di_2& di_1& di_0,
|
||||
b => bi_3& bi_2& bi_1& bi_0,
|
||||
a => ai_3& ai_2& ai_1& ai_0);
|
||||
|
||||
end VST;
|
||||
|
|
@ -1 +0,0 @@
|
|||
druc_heart done
|
||||
|
|
@ -1,238 +0,0 @@
|
|||
-- VHDL structural description generated from `heart`
|
||||
-- date : Sun Sep 27 12:27:25 1998
|
||||
|
||||
|
||||
-- Entity Declaration
|
||||
|
||||
ENTITY heart IS
|
||||
PORT (
|
||||
a : in BIT_VECTOR (3 DOWNTO 0); -- a
|
||||
b : in BIT_VECTOR (3 DOWNTO 0); -- b
|
||||
d : in BIT_VECTOR (3 DOWNTO 0); -- d
|
||||
cin : linkage BIT; -- cin
|
||||
cout : linkage BIT; -- cout
|
||||
np : out BIT; -- np
|
||||
ng : out BIT; -- ng
|
||||
signe : linkage BIT; -- signe
|
||||
zero : out BIT; -- zero
|
||||
ovr : out BIT; -- ovr
|
||||
i : in BIT_VECTOR (8 DOWNTO 0); -- i
|
||||
q0 : in BIT; -- q0
|
||||
q3 : in BIT; -- q3
|
||||
f0 : out BIT; -- f0
|
||||
f3 : out BIT; -- f3
|
||||
fonc : in BIT; -- fonc
|
||||
test : in BIT; -- test
|
||||
scin : in BIT; -- scin
|
||||
scout : out BIT; -- scout
|
||||
decald : out BIT; -- decald
|
||||
decalg : out BIT; -- decalg
|
||||
decaldr : out BIT; -- decaldr
|
||||
decalgr : out BIT; -- decalgr
|
||||
r0 : in BIT; -- r0
|
||||
r3 : in BIT; -- r3
|
||||
s0 : out BIT; -- s0
|
||||
s3 : out BIT; -- s3
|
||||
ck : in BIT; -- ck
|
||||
y : out BIT_VECTOR (3 DOWNTO 0); -- y
|
||||
noe : in BIT; -- noe
|
||||
oe : out BIT; -- oe
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END heart;
|
||||
|
||||
-- Architecture Declaration
|
||||
|
||||
ARCHITECTURE VST OF heart IS
|
||||
COMPONENT muxe
|
||||
port (
|
||||
ra : in BIT_VECTOR(3 DOWNTO 0); -- ra
|
||||
rb : in BIT_VECTOR(3 DOWNTO 0); -- rb
|
||||
q : in BIT_VECTOR(3 DOWNTO 0); -- q
|
||||
d : in BIT_VECTOR(3 DOWNTO 0); -- d
|
||||
r : out BIT_VECTOR(3 DOWNTO 0); -- r
|
||||
s : out BIT_VECTOR(3 DOWNTO 0); -- s
|
||||
i : in BIT_VECTOR(2 DOWNTO 0); -- i
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT muxout
|
||||
port (
|
||||
ra : in BIT_VECTOR(3 DOWNTO 0); -- ra
|
||||
alu_out : in BIT_VECTOR(3 DOWNTO 0); -- alu_out
|
||||
noe : in BIT; -- noe
|
||||
oe : out BIT; -- oe
|
||||
y : out BIT_VECTOR(3 DOWNTO 0); -- y
|
||||
i : in BIT_VECTOR(8 DOWNTO 6); -- i
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT alu
|
||||
port (
|
||||
r : in BIT_VECTOR(3 DOWNTO 0); -- r
|
||||
s : in BIT_VECTOR(3 DOWNTO 0); -- s
|
||||
alu_out : out BIT_VECTOR(3 DOWNTO 0); -- alu_out
|
||||
cin : in BIT; -- cin
|
||||
cout : out BIT; -- cout
|
||||
np : out BIT; -- np
|
||||
ng : out BIT; -- ng
|
||||
signe : out BIT; -- signe
|
||||
zero : out BIT; -- zero
|
||||
ovr : out BIT; -- ovr
|
||||
i : in BIT_VECTOR(5 DOWNTO 3); -- i
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT accu
|
||||
port (
|
||||
alu_out : in BIT_VECTOR(3 DOWNTO 0); -- alu_out
|
||||
q0 : in BIT; -- q0
|
||||
q3 : in BIT; -- q3
|
||||
fonc : in BIT; -- fonc
|
||||
test : in BIT; -- test
|
||||
fonc_mode : linkage BIT; -- fonc_mode
|
||||
scin : in BIT; -- scin
|
||||
scout : out BIT; -- scout
|
||||
f0 : out BIT; -- f0
|
||||
f3 : out BIT; -- f3
|
||||
decald : out BIT; -- decald
|
||||
decalg : out BIT; -- decalg
|
||||
q : linkage BIT_VECTOR(3 DOWNTO 0); -- q
|
||||
i : in BIT_VECTOR(8 DOWNTO 6); -- i
|
||||
ck : in BIT; -- ck
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT ram
|
||||
port (
|
||||
a : in BIT_VECTOR(3 DOWNTO 0); -- a
|
||||
b : in BIT_VECTOR(3 DOWNTO 0); -- b
|
||||
alu_out : in BIT_VECTOR(3 DOWNTO 0); -- alu_out
|
||||
fonc_mode : in BIT; -- fonc_mode
|
||||
r0 : in BIT; -- r0
|
||||
r3 : in BIT; -- r3
|
||||
s0 : out BIT; -- s0
|
||||
s3 : out BIT; -- s3
|
||||
decaldr : out BIT; -- decaldr
|
||||
decalgr : out BIT; -- decalgr
|
||||
ra : out BIT_VECTOR(3 DOWNTO 0); -- ra
|
||||
rb : out BIT_VECTOR(3 DOWNTO 0); -- rb
|
||||
i : in BIT_VECTOR(8 DOWNTO 7); -- i
|
||||
ck : in BIT; -- ck
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
SIGNAL alu_out_0 : BIT; -- alu_out 0
|
||||
SIGNAL alu_out_1 : BIT; -- alu_out 1
|
||||
SIGNAL alu_out_2 : BIT; -- alu_out 2
|
||||
SIGNAL alu_out_3 : BIT; -- alu_out 3
|
||||
SIGNAL fonc_mode : BIT; -- fonc_mode
|
||||
SIGNAL q_0 : BIT; -- q 0
|
||||
SIGNAL q_1 : BIT; -- q 1
|
||||
SIGNAL q_2 : BIT; -- q 2
|
||||
SIGNAL q_3 : BIT; -- q 3
|
||||
SIGNAL r_0 : BIT; -- r 0
|
||||
SIGNAL r_1 : BIT; -- r 1
|
||||
SIGNAL r_2 : BIT; -- r 2
|
||||
SIGNAL r_3 : BIT; -- r 3
|
||||
SIGNAL ra_0 : BIT; -- ra 0
|
||||
SIGNAL ra_1 : BIT; -- ra 1
|
||||
SIGNAL ra_2 : BIT; -- ra 2
|
||||
SIGNAL ra_3 : BIT; -- ra 3
|
||||
SIGNAL rb_0 : BIT; -- rb 0
|
||||
SIGNAL rb_1 : BIT; -- rb 1
|
||||
SIGNAL rb_2 : BIT; -- rb 2
|
||||
SIGNAL rb_3 : BIT; -- rb 3
|
||||
SIGNAL s_0 : BIT; -- s 0
|
||||
SIGNAL s_1 : BIT; -- s 1
|
||||
SIGNAL s_2 : BIT; -- s 2
|
||||
SIGNAL s_3 : BIT; -- s 3
|
||||
|
||||
BEGIN
|
||||
|
||||
block1 : muxe
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
i => i(2)& i(1)& i(0),
|
||||
s => s_3& s_2& s_1& s_0,
|
||||
r => r_3& r_2& r_1& r_0,
|
||||
d => d(3)& d(2)& d(1)& d(0),
|
||||
q => q_3& q_2& q_1& q_0,
|
||||
rb => rb_3& rb_2& rb_1& rb_0,
|
||||
ra => ra_3& ra_2& ra_1& ra_0);
|
||||
block2 : muxout
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
i => i(8)& i(7)& i(6),
|
||||
y => y(3)& y(2)& y(1)& y(0),
|
||||
oe => oe,
|
||||
noe => noe,
|
||||
alu_out => alu_out_3& alu_out_2& alu_out_1& alu_out_0,
|
||||
ra => ra_3& ra_2& ra_1& ra_0);
|
||||
block3 : alu
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
i => i(5)& i(4)& i(3),
|
||||
ovr => ovr,
|
||||
zero => zero,
|
||||
signe => signe,
|
||||
ng => ng,
|
||||
np => np,
|
||||
cout => cout,
|
||||
cin => cin,
|
||||
alu_out => alu_out_3& alu_out_2& alu_out_1& alu_out_0,
|
||||
s => s_3& s_2& s_1& s_0,
|
||||
r => r_3& r_2& r_1& r_0);
|
||||
block4 : accu
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
ck => ck,
|
||||
i => i(8)& i(7)& i(6),
|
||||
q => q_3& q_2& q_1& q_0,
|
||||
decalg => decalg,
|
||||
decald => decald,
|
||||
f3 => f3,
|
||||
f0 => f0,
|
||||
scout => scout,
|
||||
scin => scin,
|
||||
fonc_mode => fonc_mode,
|
||||
test => test,
|
||||
fonc => fonc,
|
||||
q3 => q3,
|
||||
q0 => q0,
|
||||
alu_out => alu_out_3& alu_out_2& alu_out_1& alu_out_0);
|
||||
block5 : ram
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
ck => ck,
|
||||
i => i(8)& i(7),
|
||||
rb => rb_3& rb_2& rb_1& rb_0,
|
||||
ra => ra_3& ra_2& ra_1& ra_0,
|
||||
decalgr => decalgr,
|
||||
decaldr => decaldr,
|
||||
s3 => s3,
|
||||
s0 => s0,
|
||||
r3 => r3,
|
||||
r0 => r0,
|
||||
fonc_mode => fonc_mode,
|
||||
alu_out => alu_out_3& alu_out_2& alu_out_1& alu_out_0,
|
||||
b => b(3)& b(2)& b(1)& b(0),
|
||||
a => a(3)& a(2)& a(1)& a(0));
|
||||
|
||||
end VST;
|
||||
|
|
@ -1,365 +0,0 @@
|
|||
-- VHDL structural description generated from `muxe`
|
||||
-- date : Sun Sep 27 12:27:24 1998
|
||||
|
||||
|
||||
-- Entity Declaration
|
||||
|
||||
ENTITY muxe IS
|
||||
PORT (
|
||||
ra : in BIT_VECTOR (3 DOWNTO 0); -- ra
|
||||
rb : in BIT_VECTOR (3 DOWNTO 0); -- rb
|
||||
q : in BIT_VECTOR (3 DOWNTO 0); -- q
|
||||
d : in BIT_VECTOR (3 DOWNTO 0); -- d
|
||||
r : out BIT_VECTOR (3 DOWNTO 0); -- r
|
||||
s : out BIT_VECTOR (3 DOWNTO 0); -- s
|
||||
i : in BIT_VECTOR (2 DOWNTO 0); -- i
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END muxe;
|
||||
|
||||
-- Architecture Declaration
|
||||
|
||||
ARCHITECTURE VST OF muxe IS
|
||||
COMPONENT n1_y
|
||||
port (
|
||||
i : in BIT; -- i
|
||||
f : out BIT; -- f
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT a2_y
|
||||
port (
|
||||
i0 : in BIT; -- i0
|
||||
i1 : in BIT; -- i1
|
||||
t : out BIT; -- t
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT o3_y
|
||||
port (
|
||||
i0 : in BIT; -- i0
|
||||
i1 : in BIT; -- i1
|
||||
i2 : in BIT; -- i2
|
||||
t : out BIT; -- t
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT o2_y
|
||||
port (
|
||||
i0 : in BIT; -- i0
|
||||
i1 : in BIT; -- i1
|
||||
t : out BIT; -- t
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
SIGNAL ni0 : BIT; -- ni0
|
||||
SIGNAL ni1 : BIT; -- ni1
|
||||
SIGNAL ni2 : BIT; -- ni2
|
||||
SIGNAL o21s : BIT; -- o21s
|
||||
SIGNAL o22s : BIT; -- o22s
|
||||
SIGNAL selar : BIT; -- selar
|
||||
SIGNAL selas : BIT; -- selas
|
||||
SIGNAL selbs : BIT; -- selbs
|
||||
SIGNAL seldr : BIT; -- seldr
|
||||
SIGNAL selqs : BIT; -- selqs
|
||||
SIGNAL sra0 : BIT; -- sra0
|
||||
SIGNAL sra1 : BIT; -- sra1
|
||||
SIGNAL sra2 : BIT; -- sra2
|
||||
SIGNAL sra3 : BIT; -- sra3
|
||||
SIGNAL srb0 : BIT; -- srb0
|
||||
SIGNAL srb1 : BIT; -- srb1
|
||||
SIGNAL srb2 : BIT; -- srb2
|
||||
SIGNAL srb3 : BIT; -- srb3
|
||||
SIGNAL srq0 : BIT; -- srq0
|
||||
SIGNAL srq1 : BIT; -- srq1
|
||||
SIGNAL srq2 : BIT; -- srq2
|
||||
SIGNAL srq3 : BIT; -- srq3
|
||||
SIGNAL ssa0 : BIT; -- ssa0
|
||||
SIGNAL ssa1 : BIT; -- ssa1
|
||||
SIGNAL ssa2 : BIT; -- ssa2
|
||||
SIGNAL ssa3 : BIT; -- ssa3
|
||||
SIGNAL ssd0 : BIT; -- ssd0
|
||||
SIGNAL ssd1 : BIT; -- ssd1
|
||||
SIGNAL ssd2 : BIT; -- ssd2
|
||||
SIGNAL ssd3 : BIT; -- ssd3
|
||||
|
||||
BEGIN
|
||||
|
||||
n11me : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => ni2,
|
||||
i => i(2));
|
||||
n12me : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => ni1,
|
||||
i => i(1));
|
||||
n13me : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => ni0,
|
||||
i => i(0));
|
||||
a21me : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => selas,
|
||||
i1 => i(2),
|
||||
i0 => ni1);
|
||||
a22me : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => selbs,
|
||||
i1 => i(0),
|
||||
i0 => ni2);
|
||||
o21me : o2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => o21s,
|
||||
i1 => ni2,
|
||||
i0 => i(1));
|
||||
a23me : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => selar,
|
||||
i1 => ni1,
|
||||
i0 => ni2);
|
||||
o22me : o2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => o22s,
|
||||
i1 => i(0),
|
||||
i0 => i(1));
|
||||
a24me : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => selqs,
|
||||
i1 => ni0,
|
||||
i0 => o21s);
|
||||
a25me : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => seldr,
|
||||
i1 => i(2),
|
||||
i0 => o22s);
|
||||
a26ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => srb0,
|
||||
i1 => selbs,
|
||||
i0 => rb(0));
|
||||
a27ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => srb1,
|
||||
i1 => selbs,
|
||||
i0 => rb(1));
|
||||
a28ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => srb2,
|
||||
i1 => selbs,
|
||||
i0 => rb(2));
|
||||
a29ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => srb3,
|
||||
i1 => selbs,
|
||||
i0 => rb(3));
|
||||
a210ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => sra0,
|
||||
i1 => selas,
|
||||
i0 => ra(0));
|
||||
a211ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => sra1,
|
||||
i1 => selas,
|
||||
i0 => ra(1));
|
||||
a212ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => sra2,
|
||||
i1 => selas,
|
||||
i0 => ra(2));
|
||||
a213ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => sra3,
|
||||
i1 => selas,
|
||||
i0 => ra(3));
|
||||
a214ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => ssa0,
|
||||
i1 => selar,
|
||||
i0 => ra(0));
|
||||
a215ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => ssa1,
|
||||
i1 => selar,
|
||||
i0 => ra(1));
|
||||
a216ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => ssa2,
|
||||
i1 => selar,
|
||||
i0 => ra(2));
|
||||
a217ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => ssa3,
|
||||
i1 => selar,
|
||||
i0 => ra(3));
|
||||
a218ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => srq0,
|
||||
i1 => selqs,
|
||||
i0 => q(0));
|
||||
a219ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => srq1,
|
||||
i1 => selqs,
|
||||
i0 => q(1));
|
||||
a220ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => srq2,
|
||||
i1 => selqs,
|
||||
i0 => q(2));
|
||||
a221ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => srq3,
|
||||
i1 => selqs,
|
||||
i0 => q(3));
|
||||
a222ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => ssd0,
|
||||
i1 => seldr,
|
||||
i0 => d(0));
|
||||
a223ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => ssd1,
|
||||
i1 => seldr,
|
||||
i0 => d(1));
|
||||
a224ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => ssd2,
|
||||
i1 => seldr,
|
||||
i0 => d(2));
|
||||
a225ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => ssd3,
|
||||
i1 => seldr,
|
||||
i0 => d(3));
|
||||
o31ms : o3_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => s(0),
|
||||
i2 => srq0,
|
||||
i1 => sra0,
|
||||
i0 => srb0);
|
||||
o32ms : o3_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => s(1),
|
||||
i2 => srq1,
|
||||
i1 => sra1,
|
||||
i0 => srb1);
|
||||
o33ms : o3_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => s(2),
|
||||
i2 => srq2,
|
||||
i1 => sra2,
|
||||
i0 => srb2);
|
||||
o34ms : o3_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => s(3),
|
||||
i2 => srq3,
|
||||
i1 => sra3,
|
||||
i0 => srb3);
|
||||
o23ms : o2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => r(0),
|
||||
i1 => ssd0,
|
||||
i0 => ssa0);
|
||||
o24ms : o2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => r(1),
|
||||
i1 => ssd1,
|
||||
i0 => ssa1);
|
||||
o25ms : o2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => r(2),
|
||||
i1 => ssd2,
|
||||
i0 => ssa2);
|
||||
o26ms : o2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => r(3),
|
||||
i1 => ssd3,
|
||||
i0 => ssa3);
|
||||
|
||||
end VST;
|
||||
|
|
@ -1,195 +0,0 @@
|
|||
-- VHDL structural description generated from `muxout`
|
||||
-- date : Sun Sep 27 12:27:24 1998
|
||||
|
||||
|
||||
-- Entity Declaration
|
||||
|
||||
ENTITY muxout IS
|
||||
PORT (
|
||||
ra : in BIT_VECTOR (3 DOWNTO 0); -- ra
|
||||
alu_out : in BIT_VECTOR (3 DOWNTO 0); -- alu_out
|
||||
noe : in BIT; -- noe
|
||||
oe : out BIT; -- oe
|
||||
y : out BIT_VECTOR (3 DOWNTO 0); -- y
|
||||
i : in BIT_VECTOR (8 DOWNTO 6); -- i
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END muxout;
|
||||
|
||||
-- Architecture Declaration
|
||||
|
||||
ARCHITECTURE VST OF muxout IS
|
||||
COMPONENT a3_y
|
||||
port (
|
||||
i0 : in BIT; -- i0
|
||||
i1 : in BIT; -- i1
|
||||
i2 : in BIT; -- i2
|
||||
t : out BIT; -- t
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT a2_y
|
||||
port (
|
||||
i0 : in BIT; -- i0
|
||||
i1 : in BIT; -- i1
|
||||
t : out BIT; -- t
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT o2_y
|
||||
port (
|
||||
i0 : in BIT; -- i0
|
||||
i1 : in BIT; -- i1
|
||||
t : out BIT; -- t
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT n1_y
|
||||
port (
|
||||
i : in BIT; -- i
|
||||
f : out BIT; -- f
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
SIGNAL ni6 : BIT; -- ni6
|
||||
SIGNAL ni8 : BIT; -- ni8
|
||||
SIGNAL selaluy : BIT; -- selaluy
|
||||
SIGNAL selray : BIT; -- selray
|
||||
SIGNAL syalu0 : BIT; -- syalu0
|
||||
SIGNAL syalu1 : BIT; -- syalu1
|
||||
SIGNAL syalu2 : BIT; -- syalu2
|
||||
SIGNAL syalu3 : BIT; -- syalu3
|
||||
SIGNAL syra0 : BIT; -- syra0
|
||||
SIGNAL syra1 : BIT; -- syra1
|
||||
SIGNAL syra2 : BIT; -- syra2
|
||||
SIGNAL syra3 : BIT; -- syra3
|
||||
|
||||
BEGIN
|
||||
|
||||
n11ms : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => ni8,
|
||||
i => i(8));
|
||||
n12ms : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => ni6,
|
||||
i => i(6));
|
||||
a31ms : a3_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => selray,
|
||||
i2 => ni8,
|
||||
i1 => ni6,
|
||||
i0 => i(7));
|
||||
n13ms : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => selaluy,
|
||||
i => selray);
|
||||
a21ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => syra0,
|
||||
i1 => selray,
|
||||
i0 => ra(0));
|
||||
a22ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => syra1,
|
||||
i1 => selray,
|
||||
i0 => ra(1));
|
||||
a23ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => syra2,
|
||||
i1 => selray,
|
||||
i0 => ra(2));
|
||||
a24ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => syra3,
|
||||
i1 => selray,
|
||||
i0 => ra(3));
|
||||
a25ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => syalu0,
|
||||
i1 => selaluy,
|
||||
i0 => alu_out(0));
|
||||
a26ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => syalu1,
|
||||
i1 => selaluy,
|
||||
i0 => alu_out(1));
|
||||
a27ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => syalu2,
|
||||
i1 => selaluy,
|
||||
i0 => alu_out(2));
|
||||
a28ms : a2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => syalu3,
|
||||
i1 => selaluy,
|
||||
i0 => alu_out(3));
|
||||
o21ms : o2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => y(0),
|
||||
i1 => syalu0,
|
||||
i0 => syra0);
|
||||
o22ms : o2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => y(1),
|
||||
i1 => syalu1,
|
||||
i0 => syra1);
|
||||
o23ms : o2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => y(2),
|
||||
i1 => syalu2,
|
||||
i0 => syra2);
|
||||
o24ms : o2_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
t => y(3),
|
||||
i1 => syalu3,
|
||||
i0 => syra3);
|
||||
n1oe : n1_y
|
||||
PORT MAP (
|
||||
vss => vss,
|
||||
vdd => vdd,
|
||||
f => oe,
|
||||
i => noe);
|
||||
|
||||
end VST;
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,548 +0,0 @@
|
|||
|
||||
-- description generated by Pat driver v104
|
||||
-- date : Sun Sep 27 12:27:16 1998
|
||||
|
||||
|
||||
-- sequence : pattern
|
||||
|
||||
-- input / output list :
|
||||
in a (3 downto 0) X;;
|
||||
in b (3 downto 0) X;;
|
||||
in d (3 downto 0) X;;
|
||||
in i (8 downto 0) O;;
|
||||
in fonc B;;
|
||||
in test B;;
|
||||
in scin B;;
|
||||
in noe B;;
|
||||
in cke B;;
|
||||
in cin B;;
|
||||
inout r0 B;;
|
||||
inout r3 B;;
|
||||
inout q0 B;;
|
||||
inout q3 B;;
|
||||
out y (3 downto 0) X;;
|
||||
out zero B;;
|
||||
out signe B;;
|
||||
out scout B;;
|
||||
out ovr B;;
|
||||
out np B;;
|
||||
out ng B;;
|
||||
out cout B;;
|
||||
in vdde B;;
|
||||
in vsse B;;
|
||||
in vddi B;;
|
||||
in vssi B;;
|
||||
|
||||
begin
|
||||
|
||||
-- Pattern description :
|
||||
|
||||
-- a b d i f t s n c c r r q q y z s s o n n c v v v v
|
||||
-- o e c o k i 0 3 0 3 e i c v p g o d s d s
|
||||
-- n s i e e n r g o r u d s d s
|
||||
-- c t n o n u t e e i i
|
||||
-- e t
|
||||
|
||||
accu_0 : 0 0 5 007 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 0 5 007 1 0 0 0 1 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 0 5 007 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 0 5 462 1 0 0 0 0 0 ?1 1 ?1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 0 5 462 1 0 0 0 1 0 ?1 1 ?1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 0 5 462 1 0 0 0 0 0 ?0 1 ?0 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 1 5 462 1 0 0 0 0 0 ?0 0 ?0 0 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 1 5 462 1 0 0 0 1 0 ?0 0 ?0 0 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 1 5 462 1 0 0 0 0 0 ?1 0 ?1 0 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 2 5 432 1 0 0 0 0 0 ?1 1 ?1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 2 5 432 1 0 0 0 1 0 ?1 1 ?1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 2 5 432 1 0 0 0 0 0 ?0 1 ?0 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 3 5 432 1 0 0 0 0 0 ?0 0 ?0 0 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 3 5 432 1 0 0 0 1 0 ?0 0 ?0 0 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 3 5 432 1 0 0 0 0 0 ?1 0 ?1 0 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 1 4 5 564 1 0 0 0 0 0 ?1 1 ?1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 1 4 5 564 1 0 0 0 1 0 ?1 1 ?1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 1 4 5 564 1 0 0 0 0 0 ?1 1 ?1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 2 5 5 564 1 0 0 0 0 0 ?0 0 ?1 0 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 2 5 5 564 1 0 0 0 1 0 ?0 0 ?1 0 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 2 5 5 564 1 0 0 0 0 0 ?0 0 ?1 0 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 3 6 5 534 1 0 0 0 0 0 ?1 1 ?1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 3 6 5 534 1 0 0 0 1 0 ?1 1 ?1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 3 6 5 534 1 0 0 0 0 0 ?1 1 ?1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 7 5 534 1 0 0 0 0 0 ?0 0 ?1 0 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 7 5 534 1 0 0 0 1 0 ?0 0 ?1 0 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 7 5 534 1 0 0 0 0 0 ?0 0 ?1 0 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 0 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 0 5 163 1 0 0 0 1 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 0 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 1 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 1 5 163 1 0 0 0 1 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 1 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 2 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 2 5 163 1 0 0 0 1 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 2 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 3 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 3 5 163 1 0 0 0 1 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 3 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 4 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 4 5 163 1 0 0 0 1 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 4 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 5 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 5 5 163 1 0 0 0 1 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 5 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 6 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 6 5 163 1 0 0 0 1 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 6 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 7 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 7 5 163 1 0 0 0 1 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 7 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 7 5 034 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 7 5 034 1 0 0 0 1 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 7 5 034 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 0 5 662 1 0 0 0 0 0 1 ?1 1 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 0 5 662 1 0 0 0 1 0 1 ?1 1 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 0 5 662 1 0 0 0 0 0 1 ?0 1 ?0 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 1 5 662 1 0 0 0 0 0 0 ?0 0 ?0 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 1 5 662 1 0 0 0 1 0 0 ?0 0 ?0 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 1 5 662 1 0 0 0 0 0 0 ?1 0 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 2 5 632 1 0 0 0 0 0 1 ?1 1 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 2 5 632 1 0 0 0 1 0 1 ?1 1 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 2 5 632 1 0 0 0 0 0 1 ?0 1 ?0 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 3 5 632 1 0 0 0 0 0 0 ?0 0 ?0 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 3 5 632 1 0 0 0 1 0 0 ?0 0 ?0 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 0 3 5 632 1 0 0 0 0 0 0 ?1 0 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 1 4 5 764 1 0 0 0 0 0 1 ?1 1 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 1 4 5 764 1 0 0 0 1 0 1 ?1 1 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 1 4 5 764 1 0 0 0 0 0 1 ?1 1 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 2 5 5 764 1 0 0 0 0 0 0 ?0 0 ?1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 2 5 5 764 1 0 0 0 1 0 0 ?0 0 ?1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 2 5 5 764 1 0 0 0 0 0 0 ?0 0 ?1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 3 6 5 734 1 0 0 0 0 0 1 ?1 1 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 3 6 5 734 1 0 0 0 1 0 1 ?1 1 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 3 6 5 734 1 0 0 0 0 0 1 ?1 1 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 7 5 734 1 0 0 0 0 0 0 ?0 0 ?1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 7 5 734 1 0 0 0 1 0 0 ?0 0 ?1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 7 5 734 1 0 0 0 0 0 0 ?0 0 ?1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 0 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 0 5 163 1 0 0 0 1 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 0 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 1 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 1 5 163 1 0 0 0 1 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 1 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 2 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 2 5 163 1 0 0 0 1 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 2 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 3 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 3 5 163 1 0 0 0 1 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 3 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 4 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 4 5 163 1 0 0 0 1 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: 4 4 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
: f f 0 151 1 0 0 0 1 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f 0 151 1 0 0 0 0 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f 0 153 1 0 0 0 0 1 1 1 1 1 ?f ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f 0 153 1 0 0 0 1 1 1 1 1 1 ?f ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f 0 153 1 0 0 0 0 1 1 1 1 1 ?f ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f 0 161 1 0 0 0 0 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f 0 161 1 0 0 0 1 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f 0 161 1 0 0 0 0 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f 0 163 1 0 0 0 0 1 1 1 1 1 ?f ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f 0 163 1 0 0 0 1 1 1 1 1 1 ?f ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f 0 163 1 0 0 0 0 1 1 1 1 1 ?f ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f 0 171 1 0 0 0 0 1 1 1 1 1 ?f ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f 0 171 1 0 0 0 1 1 1 1 1 1 ?f ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f 0 171 1 0 0 0 0 1 1 1 1 1 ?f ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f 0 173 1 0 0 0 0 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f 0 173 1 0 0 0 1 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f 0 173 1 0 0 0 0 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
scan_471 : f f e 067 1 0 0 0 0 1 1 1 1 1 ?e ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 067 1 0 0 0 1 1 1 1 1 1 ?e ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 067 1 0 0 0 0 1 1 1 1 1 ?e ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 1 0 0 0 0 1 1 1 1 1 ?e ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 1 0 0 0 1 1 1 1 1 1 ?e ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 1 0 0 0 0 1 1 1 1 1 ?e ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 0 0 0 1 1 1 1 1 ?e ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 0 0 1 1 1 1 1 1 ?e ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 0 0 0 1 1 1 1 1 ?c ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 1 0 0 1 1 1 1 1 ?c ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 1 0 1 1 1 1 1 1 ?c ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 1 0 0 1 1 1 1 1 ?9 ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 0 0 0 1 1 1 1 1 ?9 ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 0 0 1 1 1 1 1 1 ?9 ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 0 0 0 1 1 1 1 1 ?2 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 0 0 0 1 1 1 1 1 ?2 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 0 0 1 1 1 1 1 1 ?2 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 0 0 0 1 1 1 1 1 ?4 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 0 0 0 1 1 1 1 1 ?4 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 0 0 1 1 1 1 1 1 ?4 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 0 0 0 1 1 1 1 1 ?8 ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 0 0 0 1 1 1 1 1 ?8 ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 0 0 1 1 1 1 1 1 ?8 ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 0 0 0 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 0 0 0 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 0 0 1 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 0 0 0 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
high_z_498 : f f e 162 0 1 0 1 0 1 1 1 1 1 ?f ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 0 1 1 1 1 1 1 1 ?f ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
: f f e 162 0 1 0 1 0 1 1 1 1 1 ?f ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ;
|
||||
|
||||
end;
|
||||
Loading…
Reference in New Issue