From 5e99ddbb74771fb759791603df2192681505daa1 Mon Sep 17 00:00:00 2001 From: Olivier Sirol Date: Wed, 19 Jan 2000 17:05:19 +0000 Subject: [PATCH] buggy tutorials... --- alliance/share/tutorials/addaccu/Makefile | 23 +- alliance/share/tutorials/amd2901/Makefile | 5 +- alliance/share/tutorials/amd2901/accu.vst | 520 --- alliance/share/tutorials/amd2901/alu.vst | 776 ----- alliance/share/tutorials/amd2901/asimut_first | 1 - alliance/share/tutorials/amd2901/asimut_vbe | 1 - alliance/share/tutorials/amd2901/asimut_vst | 1 - alliance/share/tutorials/amd2901/chip.c | 136 +- alliance/share/tutorials/amd2901/chip.vst | 708 ----- alliance/share/tutorials/amd2901/druc_heart | 1 - alliance/share/tutorials/amd2901/heart.vst | 238 -- alliance/share/tutorials/amd2901/muxe.vst | 365 --- alliance/share/tutorials/amd2901/muxout.vst | 195 -- alliance/share/tutorials/amd2901/ram.vst | 2791 ----------------- .../share/tutorials/amd2901/result_beh.pat | 548 ---- 15 files changed, 89 insertions(+), 6220 deletions(-) delete mode 100644 alliance/share/tutorials/amd2901/accu.vst delete mode 100644 alliance/share/tutorials/amd2901/alu.vst delete mode 100644 alliance/share/tutorials/amd2901/asimut_first delete mode 100644 alliance/share/tutorials/amd2901/asimut_vbe delete mode 100644 alliance/share/tutorials/amd2901/asimut_vst delete mode 100644 alliance/share/tutorials/amd2901/chip.vst delete mode 100644 alliance/share/tutorials/amd2901/druc_heart delete mode 100644 alliance/share/tutorials/amd2901/heart.vst delete mode 100644 alliance/share/tutorials/amd2901/muxe.vst delete mode 100644 alliance/share/tutorials/amd2901/muxout.vst delete mode 100644 alliance/share/tutorials/amd2901/ram.vst delete mode 100644 alliance/share/tutorials/amd2901/result_beh.pat diff --git a/alliance/share/tutorials/addaccu/Makefile b/alliance/share/tutorials/addaccu/Makefile index ce47bb2e..33f2369f 100644 --- a/alliance/share/tutorials/addaccu/Makefile +++ b/alliance/share/tutorials/addaccu/Makefile @@ -1,6 +1,5 @@ -#ALLIANCE_TOP = /users/soft5/newlabo/Solaris ASIMUT = $(ALLIANCE_TOP)/bin/asimut -GENLIB = $(ALLIANCE_TOP)/bin/genlib -v +GENLIB = $(ALLIANCE_TOP)/bin/genlib -v -k SCR = $(ALLIANCE_TOP)/bin/scr RING = $(ALLIANCE_TOP)/bin/ring LYNX = $(ALLIANCE_TOP)/bin/lynx @@ -9,6 +8,7 @@ YAGLE = $(ALLIANCE_TOP)/bin/yagle PROOF = $(ALLIANCE_TOP)/bin/proof DRUC = $(ALLIANCE_TOP)/bin/druc GRAAL = $(ALLIANCE_TOP)/bin/graal +DREAL = $(ALLIANCE_TOP)/bin/dreal S2R = $(ALLIANCE_TOP)/bin/s2r # ### @@ -23,7 +23,7 @@ all: specifications.pat addaccu.proof addaccu.cif @echo "## ##" @echo "################################################" @echo " " - @echo "Please run 'dreal -l addaccu' to see the layout." + @echo "Run 'make dreal' to see the layout." @echo " " @@ -85,7 +85,7 @@ core.ap : core.vst MBK_IN_PH=ap ;\ MBK_OUT_PH=ap ;\ MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sclib:$(ALLIANCE_TOP)/cells/padlib ;\ - SCR_SCLIB=1 ;\ + SCR_SCLIB=1 ;\ export MBK_IN_LO MBK_IN_PH MBK_OUT_PH MBK_CATA_LIB SCR_SCLIB ;\ $(SCR) -p -r core @@ -144,7 +144,7 @@ addaccu.al : addaccu.ap # ###---------------------------------------------------------### addaccu.lvx : addaccu.al addaccu.vst - $(LVX) vst al addaccu > addaccu.lvx + $(LVX) vst al addaccu addaccu > addaccu.lvx cat addaccu.lvx # ###---------------------------------------------------------### @@ -241,3 +241,16 @@ graal : addaccu.ap export MBK_IN_PH RDS_TECHNO_NAME MBK_CATA_LIB ;\ $(GRAAL) -l addaccu +# ###---------------------------------------------------------### +# look at the circuit under dreal # +# ###---------------------------------------------------------### + +dreal : addaccu.cif + MBK_IN_PH=ap ;\ + MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sclib:$(ALLIANCE_TOP)/cells/padlib ;\ + RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/prol05.rds ;\ + RDS_OUT=cif ;\ + RDS_IN=cif ;\ + export MBK_IN_PH RDS_IN RDS_OUT RDS_TECHNO_NAME MBK_CATA_LIB ;\ + $(DREAL) -l addaccu + diff --git a/alliance/share/tutorials/amd2901/Makefile b/alliance/share/tutorials/amd2901/Makefile index 2711ba01..356026db 100644 --- a/alliance/share/tutorials/amd2901/Makefile +++ b/alliance/share/tutorials/amd2901/Makefile @@ -180,9 +180,10 @@ heart.ap : asimut_vst MBK_IN_LO=vst ;\ MBK_WORK_LIB=. ;\ MBK_CATA_LIB=.:$(ALLIANCE_TOP)/cells/sclib:$(ALLIANCE_TOP)/cells/padlib;\ - export MBK_IN_PH MBK_OUT_PH MBK_IN_LO MBK_WORK_LIB MBK_CATA_LIB;\ + SCR_SCLIB=1 ;\ + export MBK_IN_PH MBK_OUT_PH MBK_IN_LO MBK_WORK_LIB MBK_CATA_LIB SCR_SCLIB ;\ $(SCR) -p -r heart;\ - $(GRAAL) -l heart +# $(GRAAL) -l heart ################################################################# # ASIMUT # diff --git a/alliance/share/tutorials/amd2901/accu.vst b/alliance/share/tutorials/amd2901/accu.vst deleted file mode 100644 index 11de6e2f..00000000 --- a/alliance/share/tutorials/amd2901/accu.vst +++ /dev/null @@ -1,520 +0,0 @@ --- VHDL structural description generated from `accu` --- date : Sun Sep 27 12:27:24 1998 - - --- Entity Declaration - -ENTITY accu IS - PORT ( - alu_out : in BIT_VECTOR (3 DOWNTO 0); -- alu_out - q0 : in BIT; -- q0 - q3 : in BIT; -- q3 - fonc : in BIT; -- fonc - test : in BIT; -- test - fonc_mode : linkage BIT; -- fonc_mode - scin : in BIT; -- scin - scout : out BIT; -- scout - f0 : out BIT; -- f0 - f3 : out BIT; -- f3 - decald : out BIT; -- decald - decalg : out BIT; -- decalg - q : linkage BIT_VECTOR (3 DOWNTO 0); -- q - i : in BIT_VECTOR (8 DOWNTO 6); -- i - ck : in BIT; -- ck - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); -END accu; - --- Architecture Declaration - -ARCHITECTURE VST OF accu IS - COMPONENT n1_y - port ( - i : in BIT; -- i - f : out BIT; -- f - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT b1_y - port ( - i : in BIT; -- i - t : out BIT; -- t - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT a3_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - i2 : in BIT; -- i2 - t : out BIT; -- t - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT o3_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - i2 : in BIT; -- i2 - t : out BIT; -- t - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT a2_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - t : out BIT; -- t - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT o2_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - t : out BIT; -- t - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT ms2_y - port ( - di : in BIT; -- di - si : in BIT; -- si - se : in BIT; -- se - l : in BIT; -- l - t : out BIT; -- t - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - SIGNAL a210s : BIT; -- a210s - SIGNAL a211s : BIT; -- a211s - SIGNAL a212s : BIT; -- a212s - SIGNAL a213s : BIT; -- a213s - SIGNAL a214s : BIT; -- a214s - SIGNAL a216s : BIT; -- a216s - SIGNAL a217s : BIT; -- a217s - SIGNAL a218s : BIT; -- a218s - SIGNAL a219s : BIT; -- a219s - SIGNAL a220s : BIT; -- a220s - SIGNAL a221s : BIT; -- a221s - SIGNAL a222s : BIT; -- a222s - SIGNAL a223s : BIT; -- a223s - SIGNAL a224s : BIT; -- a224s - SIGNAL a225s : BIT; -- a225s - SIGNAL a226s : BIT; -- a226s - SIGNAL a227s : BIT; -- a227s - SIGNAL a231s : BIT; -- a231s - SIGNAL a27s : BIT; -- a27s - SIGNAL a28s : BIT; -- a28s - SIGNAL a29s : BIT; -- a29s - SIGNAL ckin : BIT; -- ckin - SIGNAL decalda : BIT; -- decalda - SIGNAL decalga : BIT; -- decalga - SIGNAL decaln : BIT; -- decaln - SIGNAL insh0 : BIT; -- insh0 - SIGNAL insh1 : BIT; -- insh1 - SIGNAL insh2 : BIT; -- insh2 - SIGNAL insh3 : BIT; -- insh3 - SIGNAL n14s : BIT; -- n14s - SIGNAL n15s : BIT; -- n15s - SIGNAL ni6 : BIT; -- ni6 - SIGNAL ni7 : BIT; -- ni7 - SIGNAL o21s : BIT; -- o21s - SIGNAL selalu : BIT; -- selalu - SIGNAL shacc0 : BIT; -- shacc0 - SIGNAL shacc1 : BIT; -- shacc1 - SIGNAL shacc2 : BIT; -- shacc2 - SIGNAL shacc3 : BIT; -- shacc3 - SIGNAL test_mode : BIT; -- test_mode - SIGNAL w : BIT; -- w - SIGNAL waccu : BIT; -- waccu - -BEGIN - - n11sa : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => decaln, - i => i(8)); - n12sa : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => ni7, - i => i(7)); - n13sa : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => ni6, - i => i(6)); - n14sa : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => n14s, - i => fonc); - n15sa : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => n15s, - i => test); - bdecald : b1_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => decald, - i => decalda); - bdecalg : b1_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => decalg, - i => decalga); - a21sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => decalda, - i1 => ni7, - i0 => i(8)); - a22sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => decalga, - i1 => i(7), - i0 => i(8)); - a31sa : a3_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => selalu, - i2 => ni6, - i1 => ni7, - i0 => decaln); - o21sa : o2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => o21s, - i1 => ni7, - i0 => i(8)); - a24sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => fonc_mode, - i1 => n15s, - i0 => fonc); - a25sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => test_mode, - i1 => n14s, - i0 => test); - a26sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => waccu, - i1 => ni6, - i0 => o21s); - a27sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a27s, - i1 => selalu, - i0 => alu_out(3)); - a28sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a28s, - i1 => selalu, - i0 => alu_out(2)); - a29sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a29s, - i1 => selalu, - i0 => alu_out(1)); - a210sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a210s, - i1 => selalu, - i0 => alu_out(0)); - a211sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a211s, - i1 => i(8), - i0 => q(3)); - a212sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a212s, - i1 => i(8), - i0 => q(2)); - a213sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a213s, - i1 => i(8), - i0 => q(1)); - a214sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a214s, - i1 => i(8), - i0 => q(0)); - o22sa : o2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => insh3, - i1 => a211s, - i0 => a27s); - o23sa : o2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => insh2, - i1 => a212s, - i0 => a28s); - o24sa : o2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => insh1, - i1 => a213s, - i0 => a29s); - o25sa : o2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => insh0, - i1 => a214s, - i0 => a210s); - a215sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => f3, - i1 => insh3, - i0 => decalga); - a228sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => f0, - i1 => insh0, - i0 => decalda); - a216sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a216s, - i1 => decalda, - i0 => q3); - a217sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a217s, - i1 => decaln, - i0 => insh3); - a218sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a218s, - i1 => decalga, - i0 => insh2); - a219sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a219s, - i1 => decalda, - i0 => insh3); - a220sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a220s, - i1 => decaln, - i0 => insh2); - a221sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a221s, - i1 => decalga, - i0 => insh1); - a222sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a222s, - i1 => decalda, - i0 => insh2); - a223sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a223s, - i1 => decaln, - i0 => insh1); - a224sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a224s, - i1 => decalga, - i0 => insh0); - a225sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a225s, - i1 => decalda, - i0 => insh1); - a226sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a226s, - i1 => decaln, - i0 => insh0); - a227sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a227s, - i1 => decalga, - i0 => q0); - o31sa : o3_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => shacc3, - i2 => a218s, - i1 => a217s, - i0 => a216s); - o32sa : o3_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => shacc2, - i2 => a221s, - i1 => a220s, - i0 => a219s); - o33sa : o3_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => shacc1, - i2 => a224s, - i1 => a223s, - i0 => a222s); - o34sa : o3_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => shacc0, - i2 => a227s, - i1 => a226s, - i0 => a225s); - a229sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ckin, - i1 => w, - i0 => ck); - a230sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => scout, - i1 => q(3), - i0 => test_mode); - a231sa : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a231s, - i1 => waccu, - i0 => fonc_mode); - o26sa : o2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => w, - i1 => a231s, - i0 => test_mode); - m3 : ms2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => q(3), - l => ckin, - se => test_mode, - si => q(2), - di => shacc3); - m2 : ms2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => q(2), - l => ckin, - se => test_mode, - si => q(1), - di => shacc2); - m1 : ms2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => q(1), - l => ckin, - se => test_mode, - si => q(0), - di => shacc1); - m0 : ms2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => q(0), - l => ckin, - se => test_mode, - si => scin, - di => shacc0); - -end VST; diff --git a/alliance/share/tutorials/amd2901/alu.vst b/alliance/share/tutorials/amd2901/alu.vst deleted file mode 100644 index 5bc30f4e..00000000 --- a/alliance/share/tutorials/amd2901/alu.vst +++ /dev/null @@ -1,776 +0,0 @@ --- VHDL structural description generated from `alu` --- date : Sun Sep 27 12:27:24 1998 - - --- Entity Declaration - -ENTITY alu IS - PORT ( - r : in BIT_VECTOR (3 DOWNTO 0); -- r - s : in BIT_VECTOR (3 DOWNTO 0); -- s - alu_out : out BIT_VECTOR (3 DOWNTO 0); -- alu_out - cin : in BIT; -- cin - cout : out BIT; -- cout - np : out BIT; -- np - ng : out BIT; -- ng - signe : out BIT; -- signe - zero : out BIT; -- zero - ovr : out BIT; -- ovr - i : in BIT_VECTOR (5 DOWNTO 3); -- i - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); -END alu; - --- Architecture Declaration - -ARCHITECTURE VST OF alu IS - COMPONENT na3_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - i2 : in BIT; -- i2 - f : out BIT; -- f - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT nxr2_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - f : out BIT; -- f - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT np1_y - port ( - i : in BIT; -- i - f : out BIT; -- f - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT no3_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - i2 : in BIT; -- i2 - f : out BIT; -- f - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT na2_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - f : out BIT; -- f - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT no2_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - f : out BIT; -- f - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT xr2_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - t : out BIT; -- t - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT n1_y - port ( - i : in BIT; -- i - f : out BIT; -- f - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT a2_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - t : out BIT; -- t - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - SIGNAL cout0 : BIT; -- cout0 - SIGNAL cout1 : BIT; -- cout1 - SIGNAL cout2 : BIT; -- cout2 - SIGNAL couta : BIT; -- couta - SIGNAL fb0 : BIT; -- fb0 - SIGNAL fb1 : BIT; -- fb1 - SIGNAL fb2 : BIT; -- fb2 - SIGNAL flag : BIT; -- flag - SIGNAL flag1 : BIT; -- flag1 - SIGNAL g : BIT; -- g - SIGNAL gb0 : BIT; -- gb0 - SIGNAL gb1 : BIT; -- gb1 - SIGNAL gb2 : BIT; -- gb2 - SIGNAL gb3 : BIT; -- gb3 - SIGNAL genf : BIT; -- genf - SIGNAL n0 : BIT; -- n0 - SIGNAL n1 : BIT; -- n1 - SIGNAL n2 : BIT; -- n2 - SIGNAL n3 : BIT; -- n3 - SIGNAL n4 : BIT; -- n4 - SIGNAL na0_csb : BIT; -- na0_csb - SIGNAL na1_csb : BIT; -- na1_csb - SIGNAL na20 : BIT; -- na20 - SIGNAL na21 : BIT; -- na21 - SIGNAL na22 : BIT; -- na22 - SIGNAL na23 : BIT; -- na23 - SIGNAL na_csh : BIT; -- na_csh - SIGNAL ngb0 : BIT; -- ngb0 - SIGNAL ngb3 : BIT; -- ngb3 - SIGNAL ngen : BIT; -- ngen - SIGNAL ni5 : BIT; -- ni5 - SIGNAL nn0 : BIT; -- nn0 - SIGNAL nn1 : BIT; -- nn1 - SIGNAL nn3 : BIT; -- nn3 - SIGNAL no20 : BIT; -- no20 - SIGNAL no21 : BIT; -- no21 - SIGNAL no22 : BIT; -- no22 - SIGNAL no23 : BIT; -- no23 - SIGNAL no2_csh : BIT; -- no2_csh - SIGNAL no30 : BIT; -- no30 - SIGNAL no30_csh : BIT; -- no30_csh - SIGNAL no31 : BIT; -- no31 - SIGNAL no31_csh : BIT; -- no31_csh - SIGNAL no32 : BIT; -- no32 - SIGNAL no32_csh : BIT; -- no32_csh - SIGNAL no33 : BIT; -- no33 - SIGNAL no40 : BIT; -- no40 - SIGNAL no41 : BIT; -- no41 - SIGNAL no42 : BIT; -- no42 - SIGNAL no43 : BIT; -- no43 - SIGNAL not0 : BIT; -- not0 - SIGNAL not1 : BIT; -- not1 - SIGNAL not2 : BIT; -- not2 - SIGNAL not3 : BIT; -- not3 - SIGNAL npb0 : BIT; -- npb0 - SIGNAL nprop : BIT; -- nprop - SIGNAL p : BIT; -- p - SIGNAL pb0 : BIT; -- pb0 - SIGNAL pb1 : BIT; -- pb1 - SIGNAL pb2 : BIT; -- pb2 - SIGNAL pb3 : BIT; -- pb3 - SIGNAL propf : BIT; -- propf - SIGNAL signea : BIT; -- signea - SIGNAL x00 : BIT; -- x00 - SIGNAL x01 : BIT; -- x01 - SIGNAL x02 : BIT; -- x02 - SIGNAL x03 : BIT; -- x03 - SIGNAL x10 : BIT; -- x10 - SIGNAL x11 : BIT; -- x11 - SIGNAL x12 : BIT; -- x12 - SIGNAL x13 : BIT; -- x13 - SIGNAL x20 : BIT; -- x20 - SIGNAL x21 : BIT; -- x21 - SIGNAL x22 : BIT; -- x22 - SIGNAL x23 : BIT; -- x23 - -BEGIN - - xor0_a0 : xr2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => x00, - i1 => n0, - i0 => r(0)); - xor1_a0 : xr2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => x10, - i1 => n1, - i0 => s(0)); - nand0_a0 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => gb0, - i1 => x10, - i0 => x00); - nor1_a0 : no2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => pb0, - i1 => x10, - i0 => x00); - nand1_a0 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => cout0, - i1 => na20, - i0 => gb0); - not_a0 : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => not0, - i => pb0); - nand2_a0 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => na20, - i1 => cin, - i0 => not0); - nor2_a0 : no2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => no20, - i1 => gb0, - i0 => n2); - nor3_a0 : no2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => no30, - i1 => pb0, - i0 => n3); - nor4_a0 : no2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => no40, - i1 => cin, - i0 => n4); - xor2_a0 : xr2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => x20, - i1 => no30, - i0 => no20); - xor3_a0 : xr2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => fb0, - i1 => no40, - i0 => x20); - xor0_a1 : xr2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => x01, - i1 => n0, - i0 => r(1)); - xor1_a1 : xr2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => x11, - i1 => n1, - i0 => s(1)); - nand0_a1 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => gb1, - i1 => x11, - i0 => x01); - nor1_a1 : no2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => pb1, - i1 => x11, - i0 => x01); - nand1_a1 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => cout1, - i1 => na21, - i0 => gb1); - not_a1 : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => not1, - i => pb1); - nand2_a1 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => na21, - i1 => cout0, - i0 => not1); - nor2_a1 : no2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => no21, - i1 => gb1, - i0 => n2); - nor3_a1 : no2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => no31, - i1 => pb1, - i0 => n3); - nor4_a1 : no2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => no41, - i1 => cout0, - i0 => n4); - xor2_a1 : xr2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => x21, - i1 => no31, - i0 => no21); - xor3_a1 : xr2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => fb1, - i1 => no41, - i0 => x21); - xor0_a2 : xr2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => x02, - i1 => n0, - i0 => r(2)); - xor1_a2 : xr2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => x12, - i1 => n1, - i0 => s(2)); - nand0_a2 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => gb2, - i1 => x12, - i0 => x02); - nor1_a2 : no2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => pb2, - i1 => x12, - i0 => x02); - nand1_a2 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => cout2, - i1 => na22, - i0 => gb2); - not_a2 : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => not2, - i => pb2); - nand2_a2 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => na22, - i1 => cout1, - i0 => not2); - nor2_a2 : no2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => no22, - i1 => gb2, - i0 => n2); - nor3_a2 : no2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => no32, - i1 => pb2, - i0 => n3); - nor4_a2 : no2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => no42, - i1 => cout1, - i0 => n4); - xor2_a2 : xr2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => x22, - i1 => no32, - i0 => no22); - xor3_a2 : xr2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => fb2, - i1 => no42, - i0 => x22); - xor0_a3 : xr2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => x03, - i1 => n0, - i0 => r(3)); - xor1_a3 : xr2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => x13, - i1 => n1, - i0 => s(3)); - nand0_a3 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => gb3, - i1 => x13, - i0 => x03); - nor1_a3 : no2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => pb3, - i1 => x13, - i0 => x03); - nand1_a3 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => couta, - i1 => na23, - i0 => gb3); - not_a3 : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => not3, - i => pb3); - nand2_a3 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => na23, - i1 => cout2, - i0 => not3); - nor2_a3 : no2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => no23, - i1 => gb3, - i0 => n2); - nor3_a3 : no2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => no33, - i1 => pb3, - i0 => n3); - nor4_a3 : no2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => no43, - i1 => cout2, - i0 => n4); - xor2_a3 : xr2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => x23, - i1 => no33, - i0 => no23); - xor3_a3 : xr2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => signea, - i1 => no43, - i0 => x23); - not5_d : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => ni5, - i => i(5)); - nand3_d : na3_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => nn3, - i2 => ni5, - i1 => i(4), - i0 => i(3)); - nor_d : no2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => n2, - i1 => ni5, - i0 => i(4)); - nxor4_d : nxr2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => nn1, - i1 => i(5), - i0 => i(4)); - nxor3_d : nxr2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => nn0, - i1 => i(5), - i0 => i(3)); - nand_d : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => n4, - i1 => nn3, - i0 => ni5); - not0_d : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => n3, - i => nn3); - notp4_d : np1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => n1, - i => nn1); - notp3_d : np1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => n0, - i => nn0); - naflag1 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => flag1, - i1 => i(3), - i0 => i(4)); - naflag : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => flag, - i1 => flag1, - i0 => ni5); - not0_csh : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => npb0, - i => pb0); - not1_csh : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => ngb0, - i => gb0); - not2_csh : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => ngb3, - i => gb3); - npf : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => propf, - i => nprop); - npg : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => genf, - i => ngen); - npflag : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => p, - i1 => flag, - i0 => propf); - ngflag : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => g, - i1 => flag, - i0 => genf); - nor0_csh : no3_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => no30_csh, - i2 => pb1, - i1 => pb2, - i0 => pb3); - nor1_csh : no3_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => no31_csh, - i2 => pb3, - i1 => pb2, - i0 => gb1); - nor2_csh : no3_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => no32_csh, - i2 => ngb3, - i1 => no31_csh, - i0 => no2_csh); - nand0_csh : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => nprop, - i1 => no30_csh, - i0 => npb0); - nand1_csh : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => na_csh, - i1 => no30_csh, - i0 => ngb0); - nor_csh : no2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => no2_csh, - i1 => pb3, - i0 => gb2); - and_csh : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ngen, - i1 => no32_csh, - i0 => na_csh); - nand0_csb : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => na0_csb, - i1 => fb1, - i0 => fb0); - nand1_csb : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => na1_csb, - i1 => signea, - i0 => fb2); - nor_csb : no2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => zero, - i1 => na1_csb, - i0 => na0_csb); - xor_csb : xr2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ovr, - i1 => couta, - i0 => cout2); - not0_csb : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => alu_out(0), - i => fb0); - not1_csb : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => alu_out(1), - i => fb1); - not2_csb : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => alu_out(2), - i => fb2); - not3_csb : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => alu_out(3), - i => signea); - not4_csb : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => signe, - i => signea); - not0_p : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => np, - i => p); - not0_g : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => ng, - i => g); - coutflag : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => cout, - i1 => flag, - i0 => couta); - -end VST; diff --git a/alliance/share/tutorials/amd2901/asimut_first b/alliance/share/tutorials/amd2901/asimut_first deleted file mode 100644 index 94710aca..00000000 --- a/alliance/share/tutorials/amd2901/asimut_first +++ /dev/null @@ -1 +0,0 @@ -asimut_first done diff --git a/alliance/share/tutorials/amd2901/asimut_vbe b/alliance/share/tutorials/amd2901/asimut_vbe deleted file mode 100644 index c7e4d903..00000000 --- a/alliance/share/tutorials/amd2901/asimut_vbe +++ /dev/null @@ -1 +0,0 @@ -asimut_vbe done diff --git a/alliance/share/tutorials/amd2901/asimut_vst b/alliance/share/tutorials/amd2901/asimut_vst deleted file mode 100644 index 8dd42e16..00000000 --- a/alliance/share/tutorials/amd2901/asimut_vst +++ /dev/null @@ -1 +0,0 @@ -asimut_vst done diff --git a/alliance/share/tutorials/amd2901/chip.c b/alliance/share/tutorials/amd2901/chip.c index 45d91a6a..1cbba7bf 100644 --- a/alliance/share/tutorials/amd2901/chip.c +++ b/alliance/share/tutorials/amd2901/chip.c @@ -236,10 +236,10 @@ LOINS ("a2_y","a231sa","fonc_mode","waccu","a231s","vdd","vss",0); LOINS ("o2_y","o26sa","test_mode","a231s","w","vdd","vss",0); -LOINS ("ms2_y","m3","shacc3","q[2]","test_mode","ckin","q[3]","vdd","vss",0); -LOINS ("ms2_y","m2","shacc2","q[1]","test_mode","ckin","q[2]","vdd","vss",0); -LOINS ("ms2_y","m1","shacc1","q[0]","test_mode","ckin","q[1]","vdd","vss",0); -LOINS ("ms2_y","m0","shacc0","scin","test_mode","ckin","q[0]","vdd","vss",0); +LOINS ("ms2dp2_y","m3","shacc3","q[2]","test_mode","ckin","q[3]","vdd","vss",0); +LOINS ("ms2dp2_y","m2","shacc2","q[1]","test_mode","ckin","q[2]","vdd","vss",0); +LOINS ("ms2dp2_y","m1","shacc1","q[0]","test_mode","ckin","q[1]","vdd","vss",0); +LOINS ("ms2dp2_y","m0","shacc0","scin","test_mode","ckin","q[0]","vdd","vss",0); SAVE_LOFIG(); @@ -522,76 +522,76 @@ LOINS ("a2_y","c1","enable","b1","ck1","vdd","vss",0); /* building of the "memory-space" */ /* bit slice 3 */ -LOINS ("ms_y","m_16_3","shram3","ck16","s316","vdd","vss",0); -LOINS ("ms_y","m_15_3","shram3","ck15","s315","vdd","vss",0); -LOINS ("ms_y","m_14_3","shram3","ck14","s314","vdd","vss",0); -LOINS ("ms_y","m_13_3","shram3","ck13","s313","vdd","vss",0); -LOINS ("ms_y","m_12_3","shram3","ck12","s312","vdd","vss",0); -LOINS ("ms_y","m_11_3","shram3","ck11","s311","vdd","vss",0); -LOINS ("ms_y","m_10_3","shram3","ck10","s310","vdd","vss",0); -LOINS ("ms_y","m_9_3","shram3","ck9","s39","vdd","vss",0); -LOINS ("ms_y","m_8_3","shram3","ck8","s38","vdd","vss",0); -LOINS ("ms_y","m_7_3","shram3","ck7","s37","vdd","vss",0); -LOINS ("ms_y","m_6_3","shram3","ck6","s36","vdd","vss",0); -LOINS ("ms_y","m_5_3","shram3","ck5","s35","vdd","vss",0); -LOINS ("ms_y","m_4_3","shram3","ck4","s34","vdd","vss",0); -LOINS ("ms_y","m_3_3","shram3","ck3","s33","vdd","vss",0); -LOINS ("ms_y","m_2_3","shram3","ck2","s32","vdd","vss",0); -LOINS ("ms_y","m_1_3","shram3","ck1","s31","vdd","vss",0); +LOINS ("msdp2_y","m_16_3","shram3","ck16","s316","vdd","vss",0); +LOINS ("msdp2_y","m_15_3","shram3","ck15","s315","vdd","vss",0); +LOINS ("msdp2_y","m_14_3","shram3","ck14","s314","vdd","vss",0); +LOINS ("msdp2_y","m_13_3","shram3","ck13","s313","vdd","vss",0); +LOINS ("msdp2_y","m_12_3","shram3","ck12","s312","vdd","vss",0); +LOINS ("msdp2_y","m_11_3","shram3","ck11","s311","vdd","vss",0); +LOINS ("msdp2_y","m_10_3","shram3","ck10","s310","vdd","vss",0); +LOINS ("msdp2_y","m_9_3","shram3","ck9","s39","vdd","vss",0); +LOINS ("msdp2_y","m_8_3","shram3","ck8","s38","vdd","vss",0); +LOINS ("msdp2_y","m_7_3","shram3","ck7","s37","vdd","vss",0); +LOINS ("msdp2_y","m_6_3","shram3","ck6","s36","vdd","vss",0); +LOINS ("msdp2_y","m_5_3","shram3","ck5","s35","vdd","vss",0); +LOINS ("msdp2_y","m_4_3","shram3","ck4","s34","vdd","vss",0); +LOINS ("msdp2_y","m_3_3","shram3","ck3","s33","vdd","vss",0); +LOINS ("msdp2_y","m_2_3","shram3","ck2","s32","vdd","vss",0); +LOINS ("msdp2_y","m_1_3","shram3","ck1","s31","vdd","vss",0); /* bit slice 2 */ -LOINS ("ms_y","m_16_2","shram2","ck16","s216","vdd","vss",0); -LOINS ("ms_y","m_15_2","shram2","ck15","s215","vdd","vss",0); -LOINS ("ms_y","m_14_2","shram2","ck14","s214","vdd","vss",0); -LOINS ("ms_y","m_13_2","shram2","ck13","s213","vdd","vss",0); -LOINS ("ms_y","m_12_2","shram2","ck12","s212","vdd","vss",0); -LOINS ("ms_y","m_11_2","shram2","ck11","s211","vdd","vss",0); -LOINS ("ms_y","m_10_2","shram2","ck10","s210","vdd","vss",0); -LOINS ("ms_y","m_9_2","shram2","ck9","s29","vdd","vss",0); -LOINS ("ms_y","m_8_2","shram2","ck8","s28","vdd","vss",0); -LOINS ("ms_y","m_7_2","shram2","ck7","s27","vdd","vss",0); -LOINS ("ms_y","m_6_2","shram2","ck6","s26","vdd","vss",0); -LOINS ("ms_y","m_5_2","shram2","ck5","s25","vdd","vss",0); -LOINS ("ms_y","m_4_2","shram2","ck4","s24","vdd","vss",0); -LOINS ("ms_y","m_3_2","shram2","ck3","s23","vdd","vss",0); -LOINS ("ms_y","m_2_2","shram2","ck2","s22","vdd","vss",0); -LOINS ("ms_y","m_1_2","shram2","ck1","s21","vdd","vss",0); +LOINS ("msdp2_y","m_16_2","shram2","ck16","s216","vdd","vss",0); +LOINS ("msdp2_y","m_15_2","shram2","ck15","s215","vdd","vss",0); +LOINS ("msdp2_y","m_14_2","shram2","ck14","s214","vdd","vss",0); +LOINS ("msdp2_y","m_13_2","shram2","ck13","s213","vdd","vss",0); +LOINS ("msdp2_y","m_12_2","shram2","ck12","s212","vdd","vss",0); +LOINS ("msdp2_y","m_11_2","shram2","ck11","s211","vdd","vss",0); +LOINS ("msdp2_y","m_10_2","shram2","ck10","s210","vdd","vss",0); +LOINS ("msdp2_y","m_9_2","shram2","ck9","s29","vdd","vss",0); +LOINS ("msdp2_y","m_8_2","shram2","ck8","s28","vdd","vss",0); +LOINS ("msdp2_y","m_7_2","shram2","ck7","s27","vdd","vss",0); +LOINS ("msdp2_y","m_6_2","shram2","ck6","s26","vdd","vss",0); +LOINS ("msdp2_y","m_5_2","shram2","ck5","s25","vdd","vss",0); +LOINS ("msdp2_y","m_4_2","shram2","ck4","s24","vdd","vss",0); +LOINS ("msdp2_y","m_3_2","shram2","ck3","s23","vdd","vss",0); +LOINS ("msdp2_y","m_2_2","shram2","ck2","s22","vdd","vss",0); +LOINS ("msdp2_y","m_1_2","shram2","ck1","s21","vdd","vss",0); /* bit slice 1 */ -LOINS ("ms_y","m_16_1","shram1","ck16","s116","vdd","vss",0); -LOINS ("ms_y","m_15_1","shram1","ck15","s115","vdd","vss",0); -LOINS ("ms_y","m_14_1","shram1","ck14","s114","vdd","vss",0); -LOINS ("ms_y","m_13_1","shram1","ck13","s113","vdd","vss",0); -LOINS ("ms_y","m_12_1","shram1","ck12","s112","vdd","vss",0); -LOINS ("ms_y","m_11_1","shram1","ck11","s111","vdd","vss",0); -LOINS ("ms_y","m_10_1","shram1","ck10","s110","vdd","vss",0); -LOINS ("ms_y","m_9_1","shram1","ck9","s19","vdd","vss",0); -LOINS ("ms_y","m_8_1","shram1","ck8","s18","vdd","vss",0); -LOINS ("ms_y","m_7_1","shram1","ck7","s17","vdd","vss",0); -LOINS ("ms_y","m_6_1","shram1","ck6","s16","vdd","vss",0); -LOINS ("ms_y","m_5_1","shram1","ck5","s15","vdd","vss",0); -LOINS ("ms_y","m_4_1","shram1","ck4","s14","vdd","vss",0); -LOINS ("ms_y","m_3_1","shram1","ck3","s13","vdd","vss",0); -LOINS ("ms_y","m_2_1","shram1","ck2","s12","vdd","vss",0); -LOINS ("ms_y","m_1_1","shram1","ck1","s11","vdd","vss",0); +LOINS ("msdp2_y","m_16_1","shram1","ck16","s116","vdd","vss",0); +LOINS ("msdp2_y","m_15_1","shram1","ck15","s115","vdd","vss",0); +LOINS ("msdp2_y","m_14_1","shram1","ck14","s114","vdd","vss",0); +LOINS ("msdp2_y","m_13_1","shram1","ck13","s113","vdd","vss",0); +LOINS ("msdp2_y","m_12_1","shram1","ck12","s112","vdd","vss",0); +LOINS ("msdp2_y","m_11_1","shram1","ck11","s111","vdd","vss",0); +LOINS ("msdp2_y","m_10_1","shram1","ck10","s110","vdd","vss",0); +LOINS ("msdp2_y","m_9_1","shram1","ck9","s19","vdd","vss",0); +LOINS ("msdp2_y","m_8_1","shram1","ck8","s18","vdd","vss",0); +LOINS ("msdp2_y","m_7_1","shram1","ck7","s17","vdd","vss",0); +LOINS ("msdp2_y","m_6_1","shram1","ck6","s16","vdd","vss",0); +LOINS ("msdp2_y","m_5_1","shram1","ck5","s15","vdd","vss",0); +LOINS ("msdp2_y","m_4_1","shram1","ck4","s14","vdd","vss",0); +LOINS ("msdp2_y","m_3_1","shram1","ck3","s13","vdd","vss",0); +LOINS ("msdp2_y","m_2_1","shram1","ck2","s12","vdd","vss",0); +LOINS ("msdp2_y","m_1_1","shram1","ck1","s11","vdd","vss",0); /* bit slice 0 */ -LOINS ("ms_y","m_16_0","shram0","ck16","s016","vdd","vss",0); -LOINS ("ms_y","m_15_0","shram0","ck15","s015","vdd","vss",0); -LOINS ("ms_y","m_14_0","shram0","ck14","s014","vdd","vss",0); -LOINS ("ms_y","m_13_0","shram0","ck13","s013","vdd","vss",0); -LOINS ("ms_y","m_12_0","shram0","ck12","s012","vdd","vss",0); -LOINS ("ms_y","m_11_0","shram0","ck11","s011","vdd","vss",0); -LOINS ("ms_y","m_10_0","shram0","ck10","s010","vdd","vss",0); -LOINS ("ms_y","m_9_0","shram0","ck9","s09","vdd","vss",0); -LOINS ("ms_y","m_8_0","shram0","ck8","s08","vdd","vss",0); -LOINS ("ms_y","m_7_0","shram0","ck7","s07","vdd","vss",0); -LOINS ("ms_y","m_6_0","shram0","ck6","s06","vdd","vss",0); -LOINS ("ms_y","m_5_0","shram0","ck5","s05","vdd","vss",0); -LOINS ("ms_y","m_4_0","shram0","ck4","s04","vdd","vss",0); -LOINS ("ms_y","m_3_0","shram0","ck3","s03","vdd","vss",0); -LOINS ("ms_y","m_2_0","shram0","ck2","s02","vdd","vss",0); -LOINS ("ms_y","m_1_0","shram0","ck1","s01","vdd","vss",0); +LOINS ("msdp2_y","m_16_0","shram0","ck16","s016","vdd","vss",0); +LOINS ("msdp2_y","m_15_0","shram0","ck15","s015","vdd","vss",0); +LOINS ("msdp2_y","m_14_0","shram0","ck14","s014","vdd","vss",0); +LOINS ("msdp2_y","m_13_0","shram0","ck13","s013","vdd","vss",0); +LOINS ("msdp2_y","m_12_0","shram0","ck12","s012","vdd","vss",0); +LOINS ("msdp2_y","m_11_0","shram0","ck11","s011","vdd","vss",0); +LOINS ("msdp2_y","m_10_0","shram0","ck10","s010","vdd","vss",0); +LOINS ("msdp2_y","m_9_0","shram0","ck9","s09","vdd","vss",0); +LOINS ("msdp2_y","m_8_0","shram0","ck8","s08","vdd","vss",0); +LOINS ("msdp2_y","m_7_0","shram0","ck7","s07","vdd","vss",0); +LOINS ("msdp2_y","m_6_0","shram0","ck6","s06","vdd","vss",0); +LOINS ("msdp2_y","m_5_0","shram0","ck5","s05","vdd","vss",0); +LOINS ("msdp2_y","m_4_0","shram0","ck4","s04","vdd","vss",0); +LOINS ("msdp2_y","m_3_0","shram0","ck3","s03","vdd","vss",0); +LOINS ("msdp2_y","m_2_0","shram0","ck2","s02","vdd","vss",0); +LOINS ("msdp2_y","m_1_0","shram0","ck1","s01","vdd","vss",0); /* reading of the a-addressed word */ diff --git a/alliance/share/tutorials/amd2901/chip.vst b/alliance/share/tutorials/amd2901/chip.vst deleted file mode 100644 index b1d5dc2f..00000000 --- a/alliance/share/tutorials/amd2901/chip.vst +++ /dev/null @@ -1,708 +0,0 @@ --- VHDL structural description generated from `chip` --- date : Sun Sep 27 12:27:25 1998 - - --- Entity Declaration - -ENTITY chip IS - PORT ( - a : in BIT_VECTOR (3 DOWNTO 0); -- a - b : in BIT_VECTOR (3 DOWNTO 0); -- b - d : in BIT_VECTOR (3 DOWNTO 0); -- d - cin : linkage BIT; -- cin - cout : linkage BIT; -- cout - np : out BIT; -- np - ng : out BIT; -- ng - signe : linkage BIT; -- signe - zero : out BIT; -- zero - ovr : out BIT; -- ovr - i : in BIT_VECTOR (8 DOWNTO 0); -- i - q0 : linkage BIT; -- q0 - q3 : linkage BIT; -- q3 - r0 : linkage BIT; -- r0 - r3 : linkage BIT; -- r3 - noe : in BIT; -- noe - fonc : in BIT; -- fonc - test : in BIT; -- test - scin : in BIT; -- scin - scout : out BIT; -- scout - cke : in BIT; -- cke - vdde : in BIT; -- vdde - vsse : in BIT; -- vsse - vddi : in BIT; -- vddi - vssi : in BIT; -- vssi - y : linkage BIT_VECTOR (3 DOWNTO 0) -- y - ); -END chip; - --- Architecture Declaration - -ARCHITECTURE VST OF chip IS - COMPONENT pvdde_sp - port ( - ck : in BIT; -- ck - vdde : in BIT; -- vdde - vddi : in BIT; -- vddi - vsse : in BIT; -- vsse - vssi : in BIT -- vssi - ); - END COMPONENT; - - COMPONENT pvsse_sp - port ( - ck : in BIT; -- ck - vdde : in BIT; -- vdde - vddi : in BIT; -- vddi - vsse : in BIT; -- vsse - vssi : in BIT -- vssi - ); - END COMPONENT; - - COMPONENT pvsseck_sp - port ( - cko : linkage BIT; -- cko - ck : in BIT; -- ck - vdde : in BIT; -- vdde - vddi : in BIT; -- vddi - vsse : in BIT; -- vsse - vssi : in BIT -- vssi - ); - END COMPONENT; - - COMPONENT pvddi_sp - port ( - ck : in BIT; -- ck - vdde : in BIT; -- vdde - vddi : in BIT; -- vddi - vsse : in BIT; -- vsse - vssi : in BIT -- vssi - ); - END COMPONENT; - - COMPONENT pvssi_sp - port ( - ck : in BIT; -- ck - vdde : in BIT; -- vdde - vddi : in BIT; -- vddi - vsse : in BIT; -- vsse - vssi : in BIT -- vssi - ); - END COMPONENT; - - COMPONENT po_sp - port ( - i : in BIT; -- i - pad : out BIT; -- pad - ck : in BIT; -- ck - vdde : in BIT; -- vdde - vddi : in BIT; -- vddi - vsse : in BIT; -- vsse - vssi : in BIT -- vssi - ); - END COMPONENT; - - COMPONENT piot_sp - port ( - i : in BIT; -- i - b : in BIT; -- b - t : out BIT; -- t - pad : linkage BIT; -- pad - ck : in BIT; -- ck - vdde : in BIT; -- vdde - vddi : in BIT; -- vddi - vsse : in BIT; -- vsse - vssi : in BIT -- vssi - ); - END COMPONENT; - - COMPONENT pi_sp - port ( - pad : in BIT; -- pad - t : out BIT; -- t - ck : in BIT; -- ck - vdde : in BIT; -- vdde - vddi : in BIT; -- vddi - vsse : in BIT; -- vsse - vssi : in BIT -- vssi - ); - END COMPONENT; - - COMPONENT pck_sp - port ( - pad : in BIT; -- pad - ck : out BIT; -- ck - vdde : in BIT; -- vdde - vddi : in BIT; -- vddi - vsse : in BIT; -- vsse - vssi : in BIT -- vssi - ); - END COMPONENT; - - COMPONENT pot_sp - port ( - i : in BIT; -- i - b : in BIT; -- b - pad : linkage BIT; -- pad - ck : in BIT; -- ck - vdde : in BIT; -- vdde - vddi : in BIT; -- vddi - vsse : in BIT; -- vsse - vssi : in BIT -- vssi - ); - END COMPONENT; - - COMPONENT heart - port ( - a : in BIT_VECTOR(3 DOWNTO 0); -- a - b : in BIT_VECTOR(3 DOWNTO 0); -- b - d : in BIT_VECTOR(3 DOWNTO 0); -- d - cin : linkage BIT; -- cin - cout : linkage BIT; -- cout - np : out BIT; -- np - ng : out BIT; -- ng - signe : linkage BIT; -- signe - zero : out BIT; -- zero - ovr : out BIT; -- ovr - i : in BIT_VECTOR(8 DOWNTO 0); -- i - q0 : in BIT; -- q0 - q3 : in BIT; -- q3 - f0 : out BIT; -- f0 - f3 : out BIT; -- f3 - fonc : in BIT; -- fonc - test : in BIT; -- test - scin : in BIT; -- scin - scout : out BIT; -- scout - decald : out BIT; -- decald - decalg : out BIT; -- decalg - decaldr : out BIT; -- decaldr - decalgr : out BIT; -- decalgr - r0 : in BIT; -- r0 - r3 : in BIT; -- r3 - s0 : out BIT; -- s0 - s3 : out BIT; -- s3 - ck : in BIT; -- ck - y : out BIT_VECTOR(3 DOWNTO 0); -- y - noe : in BIT; -- noe - oe : out BIT; -- oe - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - SIGNAL ai_0 : BIT; -- ai 0 - SIGNAL ai_1 : BIT; -- ai 1 - SIGNAL ai_2 : BIT; -- ai 2 - SIGNAL ai_3 : BIT; -- ai 3 - SIGNAL bi_0 : BIT; -- bi 0 - SIGNAL bi_1 : BIT; -- bi 1 - SIGNAL bi_2 : BIT; -- bi 2 - SIGNAL bi_3 : BIT; -- bi 3 - SIGNAL cini : BIT; -- cini - SIGNAL ck : BIT; -- ck - SIGNAL cko : BIT; -- cko - SIGNAL coutc : BIT; -- coutc - SIGNAL decaldc : BIT; -- decaldc - SIGNAL decaldrc : BIT; -- decaldrc - SIGNAL decalgc : BIT; -- decalgc - SIGNAL decalgrc : BIT; -- decalgrc - SIGNAL di_0 : BIT; -- di 0 - SIGNAL di_1 : BIT; -- di 1 - SIGNAL di_2 : BIT; -- di 2 - SIGNAL di_3 : BIT; -- di 3 - SIGNAL f0c : BIT; -- f0c - SIGNAL f3c : BIT; -- f3c - SIGNAL fonci : BIT; -- fonci - SIGNAL ii_0 : BIT; -- ii 0 - SIGNAL ii_1 : BIT; -- ii 1 - SIGNAL ii_2 : BIT; -- ii 2 - SIGNAL ii_3 : BIT; -- ii 3 - SIGNAL ii_4 : BIT; -- ii 4 - SIGNAL ii_5 : BIT; -- ii 5 - SIGNAL ii_6 : BIT; -- ii 6 - SIGNAL ii_7 : BIT; -- ii 7 - SIGNAL ii_8 : BIT; -- ii 8 - SIGNAL ngc : BIT; -- ngc - SIGNAL noei : BIT; -- noei - SIGNAL npc : BIT; -- npc - SIGNAL oec : BIT; -- oec - SIGNAL ovrc : BIT; -- ovrc - SIGNAL q0i : BIT; -- q0i - SIGNAL q3i : BIT; -- q3i - SIGNAL r0i : BIT; -- r0i - SIGNAL r3i : BIT; -- r3i - SIGNAL s0c : BIT; -- s0c - SIGNAL s3c : BIT; -- s3c - SIGNAL scini : BIT; -- scini - SIGNAL scoutc : BIT; -- scoutc - SIGNAL signec : BIT; -- signec - SIGNAL testi : BIT; -- testi - SIGNAL yc_0 : BIT; -- yc 0 - SIGNAL yc_1 : BIT; -- yc 1 - SIGNAL yc_2 : BIT; -- yc 2 - SIGNAL yc_3 : BIT; -- yc 3 - SIGNAL zeroc : BIT; -- zeroc - -BEGIN - - vdde_p0 : pvdde_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck); - vsse_p0 : pvsse_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck); - vsse_ck : pvsseck_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - cko => cko); - vddi_p1 : pvddi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck); - vssi_p1 : pvssi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck); - a3 : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => ai_3, - pad => a(3)); - a2 : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => ai_2, - pad => a(2)); - a1 : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => ai_1, - pad => a(1)); - a0 : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => ai_0, - pad => a(0)); - b3 : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => bi_3, - pad => b(3)); - b2 : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => bi_2, - pad => b(2)); - b1 : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => bi_1, - pad => b(1)); - b0 : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => bi_0, - pad => b(0)); - d3 : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => di_3, - pad => d(3)); - d2 : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => di_2, - pad => d(2)); - d1 : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => di_1, - pad => d(1)); - d0 : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => di_0, - pad => d(0)); - cin : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => cini, - pad => cin); - scout : po_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - pad => scout, - i => scoutc); - cout : po_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - pad => cout, - i => coutc); - np : po_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - pad => np, - i => npc); - ng : po_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - pad => ng, - i => ngc); - signe : po_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - pad => signe, - i => signec); - zero : po_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - pad => zero, - i => zeroc); - ovr : po_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - pad => ovr, - i => ovrc); - q0 : piot_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - pad => q0, - t => q0i, - b => decaldc, - i => f0c); - q3 : piot_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - pad => q3, - t => q3i, - b => decalgc, - i => f3c); - r0 : piot_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - pad => r0, - t => r0i, - b => decaldrc, - i => s0c); - r3 : piot_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - pad => r3, - t => r3i, - b => decalgrc, - i => s3c); - noe : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => noei, - pad => noe); - fonc : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => fonci, - pad => fonc); - test : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => testi, - pad => test); - scin : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => scini, - pad => scin); - i8 : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => ii_8, - pad => i(8)); - i7 : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => ii_7, - pad => i(7)); - i6 : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => ii_6, - pad => i(6)); - i5 : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => ii_5, - pad => i(5)); - i4 : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => ii_4, - pad => i(4)); - i3 : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => ii_3, - pad => i(3)); - i2 : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => ii_2, - pad => i(2)); - i1 : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => ii_1, - pad => i(1)); - i0 : pi_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - t => ii_0, - pad => i(0)); - ck : pck_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - pad => cke); - y0 : pot_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - pad => y(0), - b => oec, - i => yc_0); - y1 : pot_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - pad => y(1), - b => oec, - i => yc_1); - y2 : pot_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - pad => y(2), - b => oec, - i => yc_2); - y3 : pot_sp - PORT MAP ( - vssi => vssi, - vsse => vsse, - vddi => vddi, - vdde => vdde, - ck => ck, - pad => y(3), - b => oec, - i => yc_3); - heart : heart - PORT MAP ( - vss => vssi, - vdd => vddi, - oe => oec, - noe => noei, - y => yc_3& yc_2& yc_1& yc_0, - ck => cko, - s3 => s3c, - s0 => s0c, - r3 => r3i, - r0 => r0i, - decalgr => decalgrc, - decaldr => decaldrc, - decalg => decalgc, - decald => decaldc, - scout => scoutc, - scin => scini, - test => testi, - fonc => fonci, - f3 => f3c, - f0 => f0c, - q3 => q3i, - q0 => q0i, - i => ii_8& ii_7& ii_6& ii_5& ii_4& ii_3& ii_2& ii_1& ii_0, - ovr => ovrc, - zero => zeroc, - signe => signec, - ng => ngc, - np => npc, - cout => coutc, - cin => cini, - d => di_3& di_2& di_1& di_0, - b => bi_3& bi_2& bi_1& bi_0, - a => ai_3& ai_2& ai_1& ai_0); - -end VST; diff --git a/alliance/share/tutorials/amd2901/druc_heart b/alliance/share/tutorials/amd2901/druc_heart deleted file mode 100644 index 55a4897d..00000000 --- a/alliance/share/tutorials/amd2901/druc_heart +++ /dev/null @@ -1 +0,0 @@ -druc_heart done diff --git a/alliance/share/tutorials/amd2901/heart.vst b/alliance/share/tutorials/amd2901/heart.vst deleted file mode 100644 index 07d7ea45..00000000 --- a/alliance/share/tutorials/amd2901/heart.vst +++ /dev/null @@ -1,238 +0,0 @@ --- VHDL structural description generated from `heart` --- date : Sun Sep 27 12:27:25 1998 - - --- Entity Declaration - -ENTITY heart IS - PORT ( - a : in BIT_VECTOR (3 DOWNTO 0); -- a - b : in BIT_VECTOR (3 DOWNTO 0); -- b - d : in BIT_VECTOR (3 DOWNTO 0); -- d - cin : linkage BIT; -- cin - cout : linkage BIT; -- cout - np : out BIT; -- np - ng : out BIT; -- ng - signe : linkage BIT; -- signe - zero : out BIT; -- zero - ovr : out BIT; -- ovr - i : in BIT_VECTOR (8 DOWNTO 0); -- i - q0 : in BIT; -- q0 - q3 : in BIT; -- q3 - f0 : out BIT; -- f0 - f3 : out BIT; -- f3 - fonc : in BIT; -- fonc - test : in BIT; -- test - scin : in BIT; -- scin - scout : out BIT; -- scout - decald : out BIT; -- decald - decalg : out BIT; -- decalg - decaldr : out BIT; -- decaldr - decalgr : out BIT; -- decalgr - r0 : in BIT; -- r0 - r3 : in BIT; -- r3 - s0 : out BIT; -- s0 - s3 : out BIT; -- s3 - ck : in BIT; -- ck - y : out BIT_VECTOR (3 DOWNTO 0); -- y - noe : in BIT; -- noe - oe : out BIT; -- oe - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); -END heart; - --- Architecture Declaration - -ARCHITECTURE VST OF heart IS - COMPONENT muxe - port ( - ra : in BIT_VECTOR(3 DOWNTO 0); -- ra - rb : in BIT_VECTOR(3 DOWNTO 0); -- rb - q : in BIT_VECTOR(3 DOWNTO 0); -- q - d : in BIT_VECTOR(3 DOWNTO 0); -- d - r : out BIT_VECTOR(3 DOWNTO 0); -- r - s : out BIT_VECTOR(3 DOWNTO 0); -- s - i : in BIT_VECTOR(2 DOWNTO 0); -- i - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT muxout - port ( - ra : in BIT_VECTOR(3 DOWNTO 0); -- ra - alu_out : in BIT_VECTOR(3 DOWNTO 0); -- alu_out - noe : in BIT; -- noe - oe : out BIT; -- oe - y : out BIT_VECTOR(3 DOWNTO 0); -- y - i : in BIT_VECTOR(8 DOWNTO 6); -- i - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT alu - port ( - r : in BIT_VECTOR(3 DOWNTO 0); -- r - s : in BIT_VECTOR(3 DOWNTO 0); -- s - alu_out : out BIT_VECTOR(3 DOWNTO 0); -- alu_out - cin : in BIT; -- cin - cout : out BIT; -- cout - np : out BIT; -- np - ng : out BIT; -- ng - signe : out BIT; -- signe - zero : out BIT; -- zero - ovr : out BIT; -- ovr - i : in BIT_VECTOR(5 DOWNTO 3); -- i - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT accu - port ( - alu_out : in BIT_VECTOR(3 DOWNTO 0); -- alu_out - q0 : in BIT; -- q0 - q3 : in BIT; -- q3 - fonc : in BIT; -- fonc - test : in BIT; -- test - fonc_mode : linkage BIT; -- fonc_mode - scin : in BIT; -- scin - scout : out BIT; -- scout - f0 : out BIT; -- f0 - f3 : out BIT; -- f3 - decald : out BIT; -- decald - decalg : out BIT; -- decalg - q : linkage BIT_VECTOR(3 DOWNTO 0); -- q - i : in BIT_VECTOR(8 DOWNTO 6); -- i - ck : in BIT; -- ck - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT ram - port ( - a : in BIT_VECTOR(3 DOWNTO 0); -- a - b : in BIT_VECTOR(3 DOWNTO 0); -- b - alu_out : in BIT_VECTOR(3 DOWNTO 0); -- alu_out - fonc_mode : in BIT; -- fonc_mode - r0 : in BIT; -- r0 - r3 : in BIT; -- r3 - s0 : out BIT; -- s0 - s3 : out BIT; -- s3 - decaldr : out BIT; -- decaldr - decalgr : out BIT; -- decalgr - ra : out BIT_VECTOR(3 DOWNTO 0); -- ra - rb : out BIT_VECTOR(3 DOWNTO 0); -- rb - i : in BIT_VECTOR(8 DOWNTO 7); -- i - ck : in BIT; -- ck - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - SIGNAL alu_out_0 : BIT; -- alu_out 0 - SIGNAL alu_out_1 : BIT; -- alu_out 1 - SIGNAL alu_out_2 : BIT; -- alu_out 2 - SIGNAL alu_out_3 : BIT; -- alu_out 3 - SIGNAL fonc_mode : BIT; -- fonc_mode - SIGNAL q_0 : BIT; -- q 0 - SIGNAL q_1 : BIT; -- q 1 - SIGNAL q_2 : BIT; -- q 2 - SIGNAL q_3 : BIT; -- q 3 - SIGNAL r_0 : BIT; -- r 0 - SIGNAL r_1 : BIT; -- r 1 - SIGNAL r_2 : BIT; -- r 2 - SIGNAL r_3 : BIT; -- r 3 - SIGNAL ra_0 : BIT; -- ra 0 - SIGNAL ra_1 : BIT; -- ra 1 - SIGNAL ra_2 : BIT; -- ra 2 - SIGNAL ra_3 : BIT; -- ra 3 - SIGNAL rb_0 : BIT; -- rb 0 - SIGNAL rb_1 : BIT; -- rb 1 - SIGNAL rb_2 : BIT; -- rb 2 - SIGNAL rb_3 : BIT; -- rb 3 - SIGNAL s_0 : BIT; -- s 0 - SIGNAL s_1 : BIT; -- s 1 - SIGNAL s_2 : BIT; -- s 2 - SIGNAL s_3 : BIT; -- s 3 - -BEGIN - - block1 : muxe - PORT MAP ( - vss => vss, - vdd => vdd, - i => i(2)& i(1)& i(0), - s => s_3& s_2& s_1& s_0, - r => r_3& r_2& r_1& r_0, - d => d(3)& d(2)& d(1)& d(0), - q => q_3& q_2& q_1& q_0, - rb => rb_3& rb_2& rb_1& rb_0, - ra => ra_3& ra_2& ra_1& ra_0); - block2 : muxout - PORT MAP ( - vss => vss, - vdd => vdd, - i => i(8)& i(7)& i(6), - y => y(3)& y(2)& y(1)& y(0), - oe => oe, - noe => noe, - alu_out => alu_out_3& alu_out_2& alu_out_1& alu_out_0, - ra => ra_3& ra_2& ra_1& ra_0); - block3 : alu - PORT MAP ( - vss => vss, - vdd => vdd, - i => i(5)& i(4)& i(3), - ovr => ovr, - zero => zero, - signe => signe, - ng => ng, - np => np, - cout => cout, - cin => cin, - alu_out => alu_out_3& alu_out_2& alu_out_1& alu_out_0, - s => s_3& s_2& s_1& s_0, - r => r_3& r_2& r_1& r_0); - block4 : accu - PORT MAP ( - vss => vss, - vdd => vdd, - ck => ck, - i => i(8)& i(7)& i(6), - q => q_3& q_2& q_1& q_0, - decalg => decalg, - decald => decald, - f3 => f3, - f0 => f0, - scout => scout, - scin => scin, - fonc_mode => fonc_mode, - test => test, - fonc => fonc, - q3 => q3, - q0 => q0, - alu_out => alu_out_3& alu_out_2& alu_out_1& alu_out_0); - block5 : ram - PORT MAP ( - vss => vss, - vdd => vdd, - ck => ck, - i => i(8)& i(7), - rb => rb_3& rb_2& rb_1& rb_0, - ra => ra_3& ra_2& ra_1& ra_0, - decalgr => decalgr, - decaldr => decaldr, - s3 => s3, - s0 => s0, - r3 => r3, - r0 => r0, - fonc_mode => fonc_mode, - alu_out => alu_out_3& alu_out_2& alu_out_1& alu_out_0, - b => b(3)& b(2)& b(1)& b(0), - a => a(3)& a(2)& a(1)& a(0)); - -end VST; diff --git a/alliance/share/tutorials/amd2901/muxe.vst b/alliance/share/tutorials/amd2901/muxe.vst deleted file mode 100644 index c97c2561..00000000 --- a/alliance/share/tutorials/amd2901/muxe.vst +++ /dev/null @@ -1,365 +0,0 @@ --- VHDL structural description generated from `muxe` --- date : Sun Sep 27 12:27:24 1998 - - --- Entity Declaration - -ENTITY muxe IS - PORT ( - ra : in BIT_VECTOR (3 DOWNTO 0); -- ra - rb : in BIT_VECTOR (3 DOWNTO 0); -- rb - q : in BIT_VECTOR (3 DOWNTO 0); -- q - d : in BIT_VECTOR (3 DOWNTO 0); -- d - r : out BIT_VECTOR (3 DOWNTO 0); -- r - s : out BIT_VECTOR (3 DOWNTO 0); -- s - i : in BIT_VECTOR (2 DOWNTO 0); -- i - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); -END muxe; - --- Architecture Declaration - -ARCHITECTURE VST OF muxe IS - COMPONENT n1_y - port ( - i : in BIT; -- i - f : out BIT; -- f - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT a2_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - t : out BIT; -- t - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT o3_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - i2 : in BIT; -- i2 - t : out BIT; -- t - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT o2_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - t : out BIT; -- t - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - SIGNAL ni0 : BIT; -- ni0 - SIGNAL ni1 : BIT; -- ni1 - SIGNAL ni2 : BIT; -- ni2 - SIGNAL o21s : BIT; -- o21s - SIGNAL o22s : BIT; -- o22s - SIGNAL selar : BIT; -- selar - SIGNAL selas : BIT; -- selas - SIGNAL selbs : BIT; -- selbs - SIGNAL seldr : BIT; -- seldr - SIGNAL selqs : BIT; -- selqs - SIGNAL sra0 : BIT; -- sra0 - SIGNAL sra1 : BIT; -- sra1 - SIGNAL sra2 : BIT; -- sra2 - SIGNAL sra3 : BIT; -- sra3 - SIGNAL srb0 : BIT; -- srb0 - SIGNAL srb1 : BIT; -- srb1 - SIGNAL srb2 : BIT; -- srb2 - SIGNAL srb3 : BIT; -- srb3 - SIGNAL srq0 : BIT; -- srq0 - SIGNAL srq1 : BIT; -- srq1 - SIGNAL srq2 : BIT; -- srq2 - SIGNAL srq3 : BIT; -- srq3 - SIGNAL ssa0 : BIT; -- ssa0 - SIGNAL ssa1 : BIT; -- ssa1 - SIGNAL ssa2 : BIT; -- ssa2 - SIGNAL ssa3 : BIT; -- ssa3 - SIGNAL ssd0 : BIT; -- ssd0 - SIGNAL ssd1 : BIT; -- ssd1 - SIGNAL ssd2 : BIT; -- ssd2 - SIGNAL ssd3 : BIT; -- ssd3 - -BEGIN - - n11me : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => ni2, - i => i(2)); - n12me : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => ni1, - i => i(1)); - n13me : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => ni0, - i => i(0)); - a21me : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => selas, - i1 => i(2), - i0 => ni1); - a22me : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => selbs, - i1 => i(0), - i0 => ni2); - o21me : o2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => o21s, - i1 => ni2, - i0 => i(1)); - a23me : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => selar, - i1 => ni1, - i0 => ni2); - o22me : o2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => o22s, - i1 => i(0), - i0 => i(1)); - a24me : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => selqs, - i1 => ni0, - i0 => o21s); - a25me : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => seldr, - i1 => i(2), - i0 => o22s); - a26ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => srb0, - i1 => selbs, - i0 => rb(0)); - a27ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => srb1, - i1 => selbs, - i0 => rb(1)); - a28ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => srb2, - i1 => selbs, - i0 => rb(2)); - a29ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => srb3, - i1 => selbs, - i0 => rb(3)); - a210ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => sra0, - i1 => selas, - i0 => ra(0)); - a211ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => sra1, - i1 => selas, - i0 => ra(1)); - a212ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => sra2, - i1 => selas, - i0 => ra(2)); - a213ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => sra3, - i1 => selas, - i0 => ra(3)); - a214ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ssa0, - i1 => selar, - i0 => ra(0)); - a215ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ssa1, - i1 => selar, - i0 => ra(1)); - a216ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ssa2, - i1 => selar, - i0 => ra(2)); - a217ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ssa3, - i1 => selar, - i0 => ra(3)); - a218ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => srq0, - i1 => selqs, - i0 => q(0)); - a219ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => srq1, - i1 => selqs, - i0 => q(1)); - a220ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => srq2, - i1 => selqs, - i0 => q(2)); - a221ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => srq3, - i1 => selqs, - i0 => q(3)); - a222ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ssd0, - i1 => seldr, - i0 => d(0)); - a223ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ssd1, - i1 => seldr, - i0 => d(1)); - a224ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ssd2, - i1 => seldr, - i0 => d(2)); - a225ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ssd3, - i1 => seldr, - i0 => d(3)); - o31ms : o3_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s(0), - i2 => srq0, - i1 => sra0, - i0 => srb0); - o32ms : o3_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s(1), - i2 => srq1, - i1 => sra1, - i0 => srb1); - o33ms : o3_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s(2), - i2 => srq2, - i1 => sra2, - i0 => srb2); - o34ms : o3_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s(3), - i2 => srq3, - i1 => sra3, - i0 => srb3); - o23ms : o2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => r(0), - i1 => ssd0, - i0 => ssa0); - o24ms : o2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => r(1), - i1 => ssd1, - i0 => ssa1); - o25ms : o2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => r(2), - i1 => ssd2, - i0 => ssa2); - o26ms : o2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => r(3), - i1 => ssd3, - i0 => ssa3); - -end VST; diff --git a/alliance/share/tutorials/amd2901/muxout.vst b/alliance/share/tutorials/amd2901/muxout.vst deleted file mode 100644 index cab26e76..00000000 --- a/alliance/share/tutorials/amd2901/muxout.vst +++ /dev/null @@ -1,195 +0,0 @@ --- VHDL structural description generated from `muxout` --- date : Sun Sep 27 12:27:24 1998 - - --- Entity Declaration - -ENTITY muxout IS - PORT ( - ra : in BIT_VECTOR (3 DOWNTO 0); -- ra - alu_out : in BIT_VECTOR (3 DOWNTO 0); -- alu_out - noe : in BIT; -- noe - oe : out BIT; -- oe - y : out BIT_VECTOR (3 DOWNTO 0); -- y - i : in BIT_VECTOR (8 DOWNTO 6); -- i - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); -END muxout; - --- Architecture Declaration - -ARCHITECTURE VST OF muxout IS - COMPONENT a3_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - i2 : in BIT; -- i2 - t : out BIT; -- t - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT a2_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - t : out BIT; -- t - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT o2_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - t : out BIT; -- t - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT n1_y - port ( - i : in BIT; -- i - f : out BIT; -- f - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - SIGNAL ni6 : BIT; -- ni6 - SIGNAL ni8 : BIT; -- ni8 - SIGNAL selaluy : BIT; -- selaluy - SIGNAL selray : BIT; -- selray - SIGNAL syalu0 : BIT; -- syalu0 - SIGNAL syalu1 : BIT; -- syalu1 - SIGNAL syalu2 : BIT; -- syalu2 - SIGNAL syalu3 : BIT; -- syalu3 - SIGNAL syra0 : BIT; -- syra0 - SIGNAL syra1 : BIT; -- syra1 - SIGNAL syra2 : BIT; -- syra2 - SIGNAL syra3 : BIT; -- syra3 - -BEGIN - - n11ms : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => ni8, - i => i(8)); - n12ms : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => ni6, - i => i(6)); - a31ms : a3_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => selray, - i2 => ni8, - i1 => ni6, - i0 => i(7)); - n13ms : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => selaluy, - i => selray); - a21ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => syra0, - i1 => selray, - i0 => ra(0)); - a22ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => syra1, - i1 => selray, - i0 => ra(1)); - a23ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => syra2, - i1 => selray, - i0 => ra(2)); - a24ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => syra3, - i1 => selray, - i0 => ra(3)); - a25ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => syalu0, - i1 => selaluy, - i0 => alu_out(0)); - a26ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => syalu1, - i1 => selaluy, - i0 => alu_out(1)); - a27ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => syalu2, - i1 => selaluy, - i0 => alu_out(2)); - a28ms : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => syalu3, - i1 => selaluy, - i0 => alu_out(3)); - o21ms : o2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => y(0), - i1 => syalu0, - i0 => syra0); - o22ms : o2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => y(1), - i1 => syalu1, - i0 => syra1); - o23ms : o2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => y(2), - i1 => syalu2, - i0 => syra2); - o24ms : o2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => y(3), - i1 => syalu3, - i0 => syra3); - n1oe : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => oe, - i => noe); - -end VST; diff --git a/alliance/share/tutorials/amd2901/ram.vst b/alliance/share/tutorials/amd2901/ram.vst deleted file mode 100644 index 206871cf..00000000 --- a/alliance/share/tutorials/amd2901/ram.vst +++ /dev/null @@ -1,2791 +0,0 @@ --- VHDL structural description generated from `ram` --- date : Sun Sep 27 12:27:25 1998 - - --- Entity Declaration - -ENTITY ram IS - PORT ( - a : in BIT_VECTOR (3 DOWNTO 0); -- a - b : in BIT_VECTOR (3 DOWNTO 0); -- b - alu_out : in BIT_VECTOR (3 DOWNTO 0); -- alu_out - fonc_mode : in BIT; -- fonc_mode - r0 : in BIT; -- r0 - r3 : in BIT; -- r3 - s0 : out BIT; -- s0 - s3 : out BIT; -- s3 - decaldr : out BIT; -- decaldr - decalgr : out BIT; -- decalgr - ra : out BIT_VECTOR (3 DOWNTO 0); -- ra - rb : out BIT_VECTOR (3 DOWNTO 0); -- rb - i : in BIT_VECTOR (8 DOWNTO 7); -- i - ck : in BIT; -- ck - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); -END ram; - --- Architecture Declaration - -ARCHITECTURE VST OF ram IS - COMPONENT b1_y - port ( - i : in BIT; -- i - t : out BIT; -- t - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT o2_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - t : out BIT; -- t - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT a2p_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - t : out BIT; -- t - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT o3_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - i2 : in BIT; -- i2 - t : out BIT; -- t - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT np1_y - port ( - i : in BIT; -- i - f : out BIT; -- f - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT n1_y - port ( - i : in BIT; -- i - f : out BIT; -- f - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT a2_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - t : out BIT; -- t - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT ms_y - port ( - i : in BIT; -- i - l : in BIT; -- l - t : out BIT; -- t - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT na2_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - f : out BIT; -- f - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT a4_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - i2 : in BIT; -- i2 - i3 : in BIT; -- i3 - t : out BIT; -- t - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - COMPONENT na4_y - port ( - i0 : in BIT; -- i0 - i1 : in BIT; -- i1 - i2 : in BIT; -- i2 - i3 : in BIT; -- i3 - f : out BIT; -- f - vdd : in BIT; -- vdd - vss : in BIT -- vss - ); - END COMPONENT; - - SIGNAL a010s : BIT; -- a010s - SIGNAL a011s : BIT; -- a011s - SIGNAL a012s : BIT; -- a012s - SIGNAL a013s : BIT; -- a013s - SIGNAL a014s : BIT; -- a014s - SIGNAL a015s : BIT; -- a015s - SIGNAL a016s : BIT; -- a016s - SIGNAL a01s : BIT; -- a01s - SIGNAL a02s : BIT; -- a02s - SIGNAL a03s : BIT; -- a03s - SIGNAL a04s : BIT; -- a04s - SIGNAL a05s : BIT; -- a05s - SIGNAL a06s : BIT; -- a06s - SIGNAL a07s : BIT; -- a07s - SIGNAL a08s : BIT; -- a08s - SIGNAL a09s : BIT; -- a09s - SIGNAL a1 : BIT; -- a1 - SIGNAL a10 : BIT; -- a10 - SIGNAL a11 : BIT; -- a11 - SIGNAL a110s : BIT; -- a110s - SIGNAL a111s : BIT; -- a111s - SIGNAL a112s : BIT; -- a112s - SIGNAL a113s : BIT; -- a113s - SIGNAL a114s : BIT; -- a114s - SIGNAL a115s : BIT; -- a115s - SIGNAL a116s : BIT; -- a116s - SIGNAL a11s : BIT; -- a11s - SIGNAL a12 : BIT; -- a12 - SIGNAL a12s : BIT; -- a12s - SIGNAL a13 : BIT; -- a13 - SIGNAL a13s : BIT; -- a13s - SIGNAL a14 : BIT; -- a14 - SIGNAL a14s : BIT; -- a14s - SIGNAL a15 : BIT; -- a15 - SIGNAL a15s : BIT; -- a15s - SIGNAL a16 : BIT; -- a16 - SIGNAL a16s : BIT; -- a16s - SIGNAL a17s : BIT; -- a17s - SIGNAL a18s : BIT; -- a18s - SIGNAL a19s : BIT; -- a19s - SIGNAL a2 : BIT; -- a2 - SIGNAL a210s : BIT; -- a210s - SIGNAL a210sh : BIT; -- a210sh - SIGNAL a211s : BIT; -- a211s - SIGNAL a211sh : BIT; -- a211sh - SIGNAL a212s : BIT; -- a212s - SIGNAL a212sh : BIT; -- a212sh - SIGNAL a213s : BIT; -- a213s - SIGNAL a213sh : BIT; -- a213sh - SIGNAL a214s : BIT; -- a214s - SIGNAL a214sh : BIT; -- a214sh - SIGNAL a215s : BIT; -- a215s - SIGNAL a216s : BIT; -- a216s - SIGNAL a21s : BIT; -- a21s - SIGNAL a22s : BIT; -- a22s - SIGNAL a23s : BIT; -- a23s - SIGNAL a23sh : BIT; -- a23sh - SIGNAL a24s : BIT; -- a24s - SIGNAL a24sh : BIT; -- a24sh - SIGNAL a25s : BIT; -- a25s - SIGNAL a25sh : BIT; -- a25sh - SIGNAL a26s : BIT; -- a26s - SIGNAL a26sh : BIT; -- a26sh - SIGNAL a27s : BIT; -- a27s - SIGNAL a27sh : BIT; -- a27sh - SIGNAL a28s : BIT; -- a28s - SIGNAL a28sh : BIT; -- a28sh - SIGNAL a29s : BIT; -- a29s - SIGNAL a29sh : BIT; -- a29sh - SIGNAL a3 : BIT; -- a3 - SIGNAL a310s : BIT; -- a310s - SIGNAL a311s : BIT; -- a311s - SIGNAL a312s : BIT; -- a312s - SIGNAL a313s : BIT; -- a313s - SIGNAL a314s : BIT; -- a314s - SIGNAL a315s : BIT; -- a315s - SIGNAL a316s : BIT; -- a316s - SIGNAL a31s : BIT; -- a31s - SIGNAL a32s : BIT; -- a32s - SIGNAL a33s : BIT; -- a33s - SIGNAL a34s : BIT; -- a34s - SIGNAL a35s : BIT; -- a35s - SIGNAL a36s : BIT; -- a36s - SIGNAL a37s : BIT; -- a37s - SIGNAL a38s : BIT; -- a38s - SIGNAL a39s : BIT; -- a39s - SIGNAL a4 : BIT; -- a4 - SIGNAL a5 : BIT; -- a5 - SIGNAL a6 : BIT; -- a6 - SIGNAL a7 : BIT; -- a7 - SIGNAL a8 : BIT; -- a8 - SIGNAL a9 : BIT; -- a9 - SIGNAL b010s : BIT; -- b010s - SIGNAL b011s : BIT; -- b011s - SIGNAL b012s : BIT; -- b012s - SIGNAL b013s : BIT; -- b013s - SIGNAL b014s : BIT; -- b014s - SIGNAL b015s : BIT; -- b015s - SIGNAL b016s : BIT; -- b016s - SIGNAL b01s : BIT; -- b01s - SIGNAL b02s : BIT; -- b02s - SIGNAL b03s : BIT; -- b03s - SIGNAL b04s : BIT; -- b04s - SIGNAL b05s : BIT; -- b05s - SIGNAL b06s : BIT; -- b06s - SIGNAL b07s : BIT; -- b07s - SIGNAL b08s : BIT; -- b08s - SIGNAL b09s : BIT; -- b09s - SIGNAL b1 : BIT; -- b1 - SIGNAL b10 : BIT; -- b10 - SIGNAL b11 : BIT; -- b11 - SIGNAL b110s : BIT; -- b110s - SIGNAL b111s : BIT; -- b111s - SIGNAL b112s : BIT; -- b112s - SIGNAL b113s : BIT; -- b113s - SIGNAL b114s : BIT; -- b114s - SIGNAL b115s : BIT; -- b115s - SIGNAL b116s : BIT; -- b116s - SIGNAL b11s : BIT; -- b11s - SIGNAL b12 : BIT; -- b12 - SIGNAL b12s : BIT; -- b12s - SIGNAL b13 : BIT; -- b13 - SIGNAL b13s : BIT; -- b13s - SIGNAL b14 : BIT; -- b14 - SIGNAL b14s : BIT; -- b14s - SIGNAL b15 : BIT; -- b15 - SIGNAL b15s : BIT; -- b15s - SIGNAL b16 : BIT; -- b16 - SIGNAL b16s : BIT; -- b16s - SIGNAL b17s : BIT; -- b17s - SIGNAL b18s : BIT; -- b18s - SIGNAL b19s : BIT; -- b19s - SIGNAL b2 : BIT; -- b2 - SIGNAL b210s : BIT; -- b210s - SIGNAL b211s : BIT; -- b211s - SIGNAL b212s : BIT; -- b212s - SIGNAL b213s : BIT; -- b213s - SIGNAL b214s : BIT; -- b214s - SIGNAL b215s : BIT; -- b215s - SIGNAL b216s : BIT; -- b216s - SIGNAL b21s : BIT; -- b21s - SIGNAL b22s : BIT; -- b22s - SIGNAL b23s : BIT; -- b23s - SIGNAL b24s : BIT; -- b24s - SIGNAL b25s : BIT; -- b25s - SIGNAL b26s : BIT; -- b26s - SIGNAL b27s : BIT; -- b27s - SIGNAL b28s : BIT; -- b28s - SIGNAL b29s : BIT; -- b29s - SIGNAL b3 : BIT; -- b3 - SIGNAL b310s : BIT; -- b310s - SIGNAL b311s : BIT; -- b311s - SIGNAL b312s : BIT; -- b312s - SIGNAL b313s : BIT; -- b313s - SIGNAL b314s : BIT; -- b314s - SIGNAL b315s : BIT; -- b315s - SIGNAL b316s : BIT; -- b316s - SIGNAL b31s : BIT; -- b31s - SIGNAL b32s : BIT; -- b32s - SIGNAL b33s : BIT; -- b33s - SIGNAL b34s : BIT; -- b34s - SIGNAL b35s : BIT; -- b35s - SIGNAL b36s : BIT; -- b36s - SIGNAL b37s : BIT; -- b37s - SIGNAL b38s : BIT; -- b38s - SIGNAL b39s : BIT; -- b39s - SIGNAL b4 : BIT; -- b4 - SIGNAL b5 : BIT; -- b5 - SIGNAL b6 : BIT; -- b6 - SIGNAL b7 : BIT; -- b7 - SIGNAL b8 : BIT; -- b8 - SIGNAL b9 : BIT; -- b9 - SIGNAL ck1 : BIT; -- ck1 - SIGNAL ck10 : BIT; -- ck10 - SIGNAL ck11 : BIT; -- ck11 - SIGNAL ck12 : BIT; -- ck12 - SIGNAL ck13 : BIT; -- ck13 - SIGNAL ck14 : BIT; -- ck14 - SIGNAL ck15 : BIT; -- ck15 - SIGNAL ck16 : BIT; -- ck16 - SIGNAL ck2 : BIT; -- ck2 - SIGNAL ck3 : BIT; -- ck3 - SIGNAL ck4 : BIT; -- ck4 - SIGNAL ck5 : BIT; -- ck5 - SIGNAL ck6 : BIT; -- ck6 - SIGNAL ck7 : BIT; -- ck7 - SIGNAL ck8 : BIT; -- ck8 - SIGNAL ck9 : BIT; -- ck9 - SIGNAL decaldra : BIT; -- decaldra - SIGNAL decalgra : BIT; -- decalgra - SIGNAL decalnr : BIT; -- decalnr - SIGNAL enable : BIT; -- enable - SIGNAL na0 : BIT; -- na0 - SIGNAL na1 : BIT; -- na1 - SIGNAL na2 : BIT; -- na2 - SIGNAL na3 : BIT; -- na3 - SIGNAL nb0 : BIT; -- nb0 - SIGNAL nb1 : BIT; -- nb1 - SIGNAL nb2 : BIT; -- nb2 - SIGNAL nb3 : BIT; -- nb3 - SIGNAL ni7 : BIT; -- ni7 - SIGNAL o21s : BIT; -- o21s - SIGNAL oa410s : BIT; -- oa410s - SIGNAL oa411s : BIT; -- oa411s - SIGNAL oa412s : BIT; -- oa412s - SIGNAL oa413s : BIT; -- oa413s - SIGNAL oa420s : BIT; -- oa420s - SIGNAL oa421s : BIT; -- oa421s - SIGNAL oa422s : BIT; -- oa422s - SIGNAL oa423s : BIT; -- oa423s - SIGNAL oa430s : BIT; -- oa430s - SIGNAL oa431s : BIT; -- oa431s - SIGNAL oa432s : BIT; -- oa432s - SIGNAL oa433s : BIT; -- oa433s - SIGNAL oa440s : BIT; -- oa440s - SIGNAL oa441s : BIT; -- oa441s - SIGNAL oa442s : BIT; -- oa442s - SIGNAL oa443s : BIT; -- oa443s - SIGNAL ob410s : BIT; -- ob410s - SIGNAL ob411s : BIT; -- ob411s - SIGNAL ob412s : BIT; -- ob412s - SIGNAL ob413s : BIT; -- ob413s - SIGNAL ob420s : BIT; -- ob420s - SIGNAL ob421s : BIT; -- ob421s - SIGNAL ob422s : BIT; -- ob422s - SIGNAL ob423s : BIT; -- ob423s - SIGNAL ob430s : BIT; -- ob430s - SIGNAL ob431s : BIT; -- ob431s - SIGNAL ob432s : BIT; -- ob432s - SIGNAL ob433s : BIT; -- ob433s - SIGNAL ob440s : BIT; -- ob440s - SIGNAL ob441s : BIT; -- ob441s - SIGNAL ob442s : BIT; -- ob442s - SIGNAL ob443s : BIT; -- ob443s - SIGNAL s01 : BIT; -- s01 - SIGNAL s010 : BIT; -- s010 - SIGNAL s011 : BIT; -- s011 - SIGNAL s012 : BIT; -- s012 - SIGNAL s013 : BIT; -- s013 - SIGNAL s014 : BIT; -- s014 - SIGNAL s015 : BIT; -- s015 - SIGNAL s016 : BIT; -- s016 - SIGNAL s02 : BIT; -- s02 - SIGNAL s03 : BIT; -- s03 - SIGNAL s04 : BIT; -- s04 - SIGNAL s05 : BIT; -- s05 - SIGNAL s06 : BIT; -- s06 - SIGNAL s07 : BIT; -- s07 - SIGNAL s08 : BIT; -- s08 - SIGNAL s09 : BIT; -- s09 - SIGNAL s11 : BIT; -- s11 - SIGNAL s110 : BIT; -- s110 - SIGNAL s111 : BIT; -- s111 - SIGNAL s112 : BIT; -- s112 - SIGNAL s113 : BIT; -- s113 - SIGNAL s114 : BIT; -- s114 - SIGNAL s115 : BIT; -- s115 - SIGNAL s116 : BIT; -- s116 - SIGNAL s12 : BIT; -- s12 - SIGNAL s13 : BIT; -- s13 - SIGNAL s14 : BIT; -- s14 - SIGNAL s15 : BIT; -- s15 - SIGNAL s16 : BIT; -- s16 - SIGNAL s17 : BIT; -- s17 - SIGNAL s18 : BIT; -- s18 - SIGNAL s19 : BIT; -- s19 - SIGNAL s21 : BIT; -- s21 - SIGNAL s210 : BIT; -- s210 - SIGNAL s211 : BIT; -- s211 - SIGNAL s212 : BIT; -- s212 - SIGNAL s213 : BIT; -- s213 - SIGNAL s214 : BIT; -- s214 - SIGNAL s215 : BIT; -- s215 - SIGNAL s216 : BIT; -- s216 - SIGNAL s22 : BIT; -- s22 - SIGNAL s23 : BIT; -- s23 - SIGNAL s24 : BIT; -- s24 - SIGNAL s25 : BIT; -- s25 - SIGNAL s26 : BIT; -- s26 - SIGNAL s27 : BIT; -- s27 - SIGNAL s28 : BIT; -- s28 - SIGNAL s29 : BIT; -- s29 - SIGNAL s31 : BIT; -- s31 - SIGNAL s310 : BIT; -- s310 - SIGNAL s311 : BIT; -- s311 - SIGNAL s312 : BIT; -- s312 - SIGNAL s313 : BIT; -- s313 - SIGNAL s314 : BIT; -- s314 - SIGNAL s315 : BIT; -- s315 - SIGNAL s316 : BIT; -- s316 - SIGNAL s32 : BIT; -- s32 - SIGNAL s33 : BIT; -- s33 - SIGNAL s34 : BIT; -- s34 - SIGNAL s35 : BIT; -- s35 - SIGNAL s36 : BIT; -- s36 - SIGNAL s37 : BIT; -- s37 - SIGNAL s38 : BIT; -- s38 - SIGNAL s39 : BIT; -- s39 - SIGNAL shram0 : BIT; -- shram0 - SIGNAL shram1 : BIT; -- shram1 - SIGNAL shram2 : BIT; -- shram2 - SIGNAL shram3 : BIT; -- shram3 - SIGNAL wram : BIT; -- wram - -BEGIN - - n11ra : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => decalnr, - i => i(8)); - n12ra : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => ni7, - i => i(7)); - a21r : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => decaldra, - i1 => ni7, - i0 => i(8)); - bufdecaldr : b1_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => decaldr, - i => decaldra); - bufdecalgr : b1_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => decalgr, - i => decalgra); - a22r : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => decalgra, - i1 => i(7), - i0 => i(8)); - o21r : o2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => o21s, - i1 => i(7), - i0 => i(8)); - a215r : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => wram, - i1 => o21s, - i0 => fonc_mode); - a216r : a2p_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => enable, - i1 => wram, - i0 => ck); - a232r : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s3, - i1 => alu_out(3), - i0 => decalgra); - a233r : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s0, - i1 => alu_out(0), - i0 => decaldra); - a23r : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a23sh, - i1 => decalgra, - i0 => alu_out(2)); - a24r : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a24sh, - i1 => decalnr, - i0 => alu_out(3)); - a25r : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a25sh, - i1 => decaldra, - i0 => r3); - a26r : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a26sh, - i1 => decalgra, - i0 => alu_out(1)); - a27r : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a27sh, - i1 => decalnr, - i0 => alu_out(2)); - a28r : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a28sh, - i1 => decaldra, - i0 => alu_out(3)); - a29r : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a29sh, - i1 => decalgra, - i0 => alu_out(0)); - a210r : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a210sh, - i1 => decalnr, - i0 => alu_out(1)); - a211r : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a211sh, - i1 => decaldra, - i0 => alu_out(2)); - a212r : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a212sh, - i1 => decalgra, - i0 => r0); - a213r : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a213sh, - i1 => decalnr, - i0 => alu_out(0)); - a214r : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a214sh, - i1 => decaldra, - i0 => alu_out(1)); - o31r : o3_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => shram3, - i2 => a25sh, - i1 => a24sh, - i0 => a23sh); - o32r : o3_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => shram2, - i2 => a28sh, - i1 => a27sh, - i0 => a26sh); - o33r : o3_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => shram1, - i2 => a211sh, - i1 => a210sh, - i0 => a29sh); - o34r : o3_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => shram0, - i2 => a214sh, - i1 => a213sh, - i0 => a212sh); - n15r : np1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => na0, - i => a(0)); - n16r : np1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => na1, - i => a(1)); - n17r : np1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => na2, - i => a(2)); - n18r : np1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => na3, - i => a(3)); - a41r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a1, - i3 => na0, - i2 => na1, - i1 => na2, - i0 => na3); - a42r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a2, - i3 => a(0), - i2 => na1, - i1 => na2, - i0 => na3); - a43r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a3, - i3 => na0, - i2 => a(1), - i1 => na2, - i0 => na3); - a44r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a4, - i3 => a(0), - i2 => a(1), - i1 => na2, - i0 => na3); - a45r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a5, - i3 => na0, - i2 => na1, - i1 => a(2), - i0 => na3); - a46r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a6, - i3 => a(0), - i2 => na1, - i1 => a(2), - i0 => na3); - a47r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a7, - i3 => na0, - i2 => a(1), - i1 => a(2), - i0 => na3); - a48r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a8, - i3 => a(0), - i2 => a(1), - i1 => a(2), - i0 => na3); - a49r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a9, - i3 => na0, - i2 => na1, - i1 => na2, - i0 => a(3)); - a410r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a10, - i3 => a(0), - i2 => na1, - i1 => na2, - i0 => a(3)); - a411r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a11, - i3 => na0, - i2 => a(1), - i1 => na2, - i0 => a(3)); - a412r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a12, - i3 => a(0), - i2 => a(1), - i1 => na2, - i0 => a(3)); - a413r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a13, - i3 => na0, - i2 => na1, - i1 => a(2), - i0 => a(3)); - a414r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a14, - i3 => a(0), - i2 => na1, - i1 => a(2), - i0 => a(3)); - a415r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a15, - i3 => na0, - i2 => a(1), - i1 => a(2), - i0 => a(3)); - a416r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => a16, - i3 => a(0), - i2 => a(1), - i1 => a(2), - i0 => a(3)); - n111r : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => nb0, - i => b(0)); - n112r : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => nb1, - i => b(1)); - n113r : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => nb2, - i => b(2)); - n114r : n1_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => nb3, - i => b(3)); - b41r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => b1, - i3 => nb0, - i2 => nb1, - i1 => nb2, - i0 => nb3); - b42r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => b2, - i3 => b(0), - i2 => nb1, - i1 => nb2, - i0 => nb3); - b43r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => b3, - i3 => nb0, - i2 => b(1), - i1 => nb2, - i0 => nb3); - b44r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => b4, - i3 => b(0), - i2 => b(1), - i1 => nb2, - i0 => nb3); - b45r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => b5, - i3 => nb0, - i2 => nb1, - i1 => b(2), - i0 => nb3); - b46r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => b6, - i3 => b(0), - i2 => nb1, - i1 => b(2), - i0 => nb3); - b47r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => b7, - i3 => nb0, - i2 => b(1), - i1 => b(2), - i0 => nb3); - b48r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => b8, - i3 => b(0), - i2 => b(1), - i1 => b(2), - i0 => nb3); - b49r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => b9, - i3 => nb0, - i2 => nb1, - i1 => nb2, - i0 => b(3)); - b410r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => b10, - i3 => b(0), - i2 => nb1, - i1 => nb2, - i0 => b(3)); - b411r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => b11, - i3 => nb0, - i2 => b(1), - i1 => nb2, - i0 => b(3)); - b412r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => b12, - i3 => b(0), - i2 => b(1), - i1 => nb2, - i0 => b(3)); - b413r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => b13, - i3 => nb0, - i2 => nb1, - i1 => b(2), - i0 => b(3)); - b414r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => b14, - i3 => b(0), - i2 => nb1, - i1 => b(2), - i0 => b(3)); - b415r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => b15, - i3 => nb0, - i2 => b(1), - i1 => b(2), - i0 => b(3)); - b416r : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => b16, - i3 => b(0), - i2 => b(1), - i1 => b(2), - i0 => b(3)); - c16 : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ck16, - i1 => b16, - i0 => enable); - c15 : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ck15, - i1 => b15, - i0 => enable); - c14 : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ck14, - i1 => b14, - i0 => enable); - c13 : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ck13, - i1 => b13, - i0 => enable); - c12 : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ck12, - i1 => b12, - i0 => enable); - c11 : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ck11, - i1 => b11, - i0 => enable); - c10 : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ck10, - i1 => b10, - i0 => enable); - c9 : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ck9, - i1 => b9, - i0 => enable); - c8 : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ck8, - i1 => b8, - i0 => enable); - c7 : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ck7, - i1 => b7, - i0 => enable); - c6 : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ck6, - i1 => b6, - i0 => enable); - c5 : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ck5, - i1 => b5, - i0 => enable); - c4 : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ck4, - i1 => b4, - i0 => enable); - c3 : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ck3, - i1 => b3, - i0 => enable); - c2 : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ck2, - i1 => b2, - i0 => enable); - c1 : a2_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ck1, - i1 => b1, - i0 => enable); - m_16_3 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s316, - l => ck16, - i => shram3); - m_15_3 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s315, - l => ck15, - i => shram3); - m_14_3 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s314, - l => ck14, - i => shram3); - m_13_3 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s313, - l => ck13, - i => shram3); - m_12_3 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s312, - l => ck12, - i => shram3); - m_11_3 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s311, - l => ck11, - i => shram3); - m_10_3 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s310, - l => ck10, - i => shram3); - m_9_3 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s39, - l => ck9, - i => shram3); - m_8_3 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s38, - l => ck8, - i => shram3); - m_7_3 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s37, - l => ck7, - i => shram3); - m_6_3 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s36, - l => ck6, - i => shram3); - m_5_3 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s35, - l => ck5, - i => shram3); - m_4_3 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s34, - l => ck4, - i => shram3); - m_3_3 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s33, - l => ck3, - i => shram3); - m_2_3 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s32, - l => ck2, - i => shram3); - m_1_3 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s31, - l => ck1, - i => shram3); - m_16_2 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s216, - l => ck16, - i => shram2); - m_15_2 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s215, - l => ck15, - i => shram2); - m_14_2 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s214, - l => ck14, - i => shram2); - m_13_2 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s213, - l => ck13, - i => shram2); - m_12_2 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s212, - l => ck12, - i => shram2); - m_11_2 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s211, - l => ck11, - i => shram2); - m_10_2 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s210, - l => ck10, - i => shram2); - m_9_2 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s29, - l => ck9, - i => shram2); - m_8_2 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s28, - l => ck8, - i => shram2); - m_7_2 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s27, - l => ck7, - i => shram2); - m_6_2 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s26, - l => ck6, - i => shram2); - m_5_2 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s25, - l => ck5, - i => shram2); - m_4_2 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s24, - l => ck4, - i => shram2); - m_3_2 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s23, - l => ck3, - i => shram2); - m_2_2 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s22, - l => ck2, - i => shram2); - m_1_2 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s21, - l => ck1, - i => shram2); - m_16_1 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s116, - l => ck16, - i => shram1); - m_15_1 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s115, - l => ck15, - i => shram1); - m_14_1 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s114, - l => ck14, - i => shram1); - m_13_1 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s113, - l => ck13, - i => shram1); - m_12_1 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s112, - l => ck12, - i => shram1); - m_11_1 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s111, - l => ck11, - i => shram1); - m_10_1 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s110, - l => ck10, - i => shram1); - m_9_1 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s19, - l => ck9, - i => shram1); - m_8_1 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s18, - l => ck8, - i => shram1); - m_7_1 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s17, - l => ck7, - i => shram1); - m_6_1 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s16, - l => ck6, - i => shram1); - m_5_1 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s15, - l => ck5, - i => shram1); - m_4_1 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s14, - l => ck4, - i => shram1); - m_3_1 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s13, - l => ck3, - i => shram1); - m_2_1 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s12, - l => ck2, - i => shram1); - m_1_1 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s11, - l => ck1, - i => shram1); - m_16_0 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s016, - l => ck16, - i => shram0); - m_15_0 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s015, - l => ck15, - i => shram0); - m_14_0 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s014, - l => ck14, - i => shram0); - m_13_0 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s013, - l => ck13, - i => shram0); - m_12_0 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s012, - l => ck12, - i => shram0); - m_11_0 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s011, - l => ck11, - i => shram0); - m_10_0 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s010, - l => ck10, - i => shram0); - m_9_0 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s09, - l => ck9, - i => shram0); - m_8_0 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s08, - l => ck8, - i => shram0); - m_7_0 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s07, - l => ck7, - i => shram0); - m_6_0 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s06, - l => ck6, - i => shram0); - m_5_0 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s05, - l => ck5, - i => shram0); - m_4_0 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s04, - l => ck4, - i => shram0); - m_3_0 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s03, - l => ck3, - i => shram0); - m_2_0 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s02, - l => ck2, - i => shram0); - m_1_0 : ms_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => s01, - l => ck1, - i => shram0); - am316 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a316s, - i1 => s316, - i0 => a16); - am315 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a315s, - i1 => s315, - i0 => a15); - am314 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a314s, - i1 => s314, - i0 => a14); - am313 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a313s, - i1 => s313, - i0 => a13); - am312 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a312s, - i1 => s312, - i0 => a12); - am311 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a311s, - i1 => s311, - i0 => a11); - am310 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a310s, - i1 => s310, - i0 => a10); - am39 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a39s, - i1 => s39, - i0 => a9); - am38 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a38s, - i1 => s38, - i0 => a8); - am37 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a37s, - i1 => s37, - i0 => a7); - am36 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a36s, - i1 => s36, - i0 => a6); - am35 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a35s, - i1 => s35, - i0 => a5); - am34 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a34s, - i1 => s34, - i0 => a4); - am33 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a33s, - i1 => s33, - i0 => a3); - am32 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a32s, - i1 => s32, - i0 => a2); - am31 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a31s, - i1 => s31, - i0 => a1); - oa413 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => oa413s, - i3 => a313s, - i2 => a314s, - i1 => a315s, - i0 => a316s); - oa423 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => oa423s, - i3 => a39s, - i2 => a310s, - i1 => a311s, - i0 => a312s); - oa433 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => oa433s, - i3 => a35s, - i2 => a36s, - i1 => a37s, - i0 => a38s); - oa443 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => oa443s, - i3 => a31s, - i2 => a32s, - i1 => a33s, - i0 => a34s); - oa453 : na4_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => ra(3), - i3 => oa443s, - i2 => oa433s, - i1 => oa423s, - i0 => oa413s); - am216 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a216s, - i1 => s216, - i0 => a16); - am215 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a215s, - i1 => s215, - i0 => a15); - am214 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a214s, - i1 => s214, - i0 => a14); - am213 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a213s, - i1 => s213, - i0 => a13); - am212 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a212s, - i1 => s212, - i0 => a12); - am211 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a211s, - i1 => s211, - i0 => a11); - am210 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a210s, - i1 => s210, - i0 => a10); - am29 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a29s, - i1 => s29, - i0 => a9); - am28 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a28s, - i1 => s28, - i0 => a8); - am27 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a27s, - i1 => s27, - i0 => a7); - am26 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a26s, - i1 => s26, - i0 => a6); - am25 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a25s, - i1 => s25, - i0 => a5); - am24 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a24s, - i1 => s24, - i0 => a4); - am23 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a23s, - i1 => s23, - i0 => a3); - am22 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a22s, - i1 => s22, - i0 => a2); - am21 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a21s, - i1 => s21, - i0 => a1); - oa412 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => oa412s, - i3 => a213s, - i2 => a214s, - i1 => a215s, - i0 => a216s); - oa422 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => oa422s, - i3 => a29s, - i2 => a210s, - i1 => a211s, - i0 => a212s); - oa432 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => oa432s, - i3 => a25s, - i2 => a26s, - i1 => a27s, - i0 => a28s); - oa442 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => oa442s, - i3 => a21s, - i2 => a22s, - i1 => a23s, - i0 => a24s); - oa452 : na4_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => ra(2), - i3 => oa442s, - i2 => oa432s, - i1 => oa422s, - i0 => oa412s); - am116 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a116s, - i1 => s116, - i0 => a16); - am115 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a115s, - i1 => s115, - i0 => a15); - am114 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a114s, - i1 => s114, - i0 => a14); - am113 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a113s, - i1 => s113, - i0 => a13); - am112 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a112s, - i1 => s112, - i0 => a12); - am111 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a111s, - i1 => s111, - i0 => a11); - am110 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a110s, - i1 => s110, - i0 => a10); - am19 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a19s, - i1 => s19, - i0 => a9); - am18 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a18s, - i1 => s18, - i0 => a8); - am17 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a17s, - i1 => s17, - i0 => a7); - am16 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a16s, - i1 => s16, - i0 => a6); - am15 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a15s, - i1 => s15, - i0 => a5); - am14 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a14s, - i1 => s14, - i0 => a4); - am13 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a13s, - i1 => s13, - i0 => a3); - am12 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a12s, - i1 => s12, - i0 => a2); - am11 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a11s, - i1 => s11, - i0 => a1); - oa411 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => oa411s, - i3 => a113s, - i2 => a114s, - i1 => a115s, - i0 => a116s); - oa421 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => oa421s, - i3 => a19s, - i2 => a110s, - i1 => a111s, - i0 => a112s); - oa431 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => oa431s, - i3 => a15s, - i2 => a16s, - i1 => a17s, - i0 => a18s); - oa441 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => oa441s, - i3 => a11s, - i2 => a12s, - i1 => a13s, - i0 => a14s); - oa451 : na4_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => ra(1), - i3 => oa441s, - i2 => oa431s, - i1 => oa421s, - i0 => oa411s); - am016 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a016s, - i1 => s016, - i0 => a16); - am015 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a015s, - i1 => s015, - i0 => a15); - am014 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a014s, - i1 => s014, - i0 => a14); - am013 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a013s, - i1 => s013, - i0 => a13); - am012 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a012s, - i1 => s012, - i0 => a12); - am011 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a011s, - i1 => s011, - i0 => a11); - am010 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a010s, - i1 => s010, - i0 => a10); - am09 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a09s, - i1 => s09, - i0 => a9); - am08 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a08s, - i1 => s08, - i0 => a8); - am07 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a07s, - i1 => s07, - i0 => a7); - am06 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a06s, - i1 => s06, - i0 => a6); - am05 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a05s, - i1 => s05, - i0 => a5); - am04 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a04s, - i1 => s04, - i0 => a4); - am03 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a03s, - i1 => s03, - i0 => a3); - am02 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a02s, - i1 => s02, - i0 => a2); - am01 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => a01s, - i1 => s01, - i0 => a1); - oa410 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => oa410s, - i3 => a013s, - i2 => a014s, - i1 => a015s, - i0 => a016s); - oa420 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => oa420s, - i3 => a09s, - i2 => a010s, - i1 => a011s, - i0 => a012s); - oa430 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => oa430s, - i3 => a05s, - i2 => a06s, - i1 => a07s, - i0 => a08s); - oa440 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => oa440s, - i3 => a01s, - i2 => a02s, - i1 => a03s, - i0 => a04s); - oa450 : na4_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => ra(0), - i3 => oa440s, - i2 => oa430s, - i1 => oa420s, - i0 => oa410s); - bm316 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b316s, - i1 => s316, - i0 => b16); - bm315 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b315s, - i1 => s315, - i0 => b15); - bm314 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b314s, - i1 => s314, - i0 => b14); - bm313 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b313s, - i1 => s313, - i0 => b13); - bm312 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b312s, - i1 => s312, - i0 => b12); - bm311 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b311s, - i1 => s311, - i0 => b11); - bm310 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b310s, - i1 => s310, - i0 => b10); - bm39 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b39s, - i1 => s39, - i0 => b9); - bm38 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b38s, - i1 => s38, - i0 => b8); - bm37 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b37s, - i1 => s37, - i0 => b7); - bm36 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b36s, - i1 => s36, - i0 => b6); - bm35 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b35s, - i1 => s35, - i0 => b5); - bm34 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b34s, - i1 => s34, - i0 => b4); - bm33 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b33s, - i1 => s33, - i0 => b3); - bm32 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b32s, - i1 => s32, - i0 => b2); - bm31 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b31s, - i1 => s31, - i0 => b1); - ob413 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ob413s, - i3 => b313s, - i2 => b314s, - i1 => b315s, - i0 => b316s); - ob423 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ob423s, - i3 => b39s, - i2 => b310s, - i1 => b311s, - i0 => b312s); - ob433 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ob433s, - i3 => b35s, - i2 => b36s, - i1 => b37s, - i0 => b38s); - ob443 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ob443s, - i3 => b31s, - i2 => b32s, - i1 => b33s, - i0 => b34s); - ob453 : na4_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => rb(3), - i3 => ob443s, - i2 => ob433s, - i1 => ob423s, - i0 => ob413s); - bm216 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b216s, - i1 => s216, - i0 => b16); - bm215 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b215s, - i1 => s215, - i0 => b15); - bm214 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b214s, - i1 => s214, - i0 => b14); - bm213 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b213s, - i1 => s213, - i0 => b13); - bm212 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b212s, - i1 => s212, - i0 => b12); - bm211 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b211s, - i1 => s211, - i0 => b11); - bm210 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b210s, - i1 => s210, - i0 => b10); - bm29 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b29s, - i1 => s29, - i0 => b9); - bm28 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b28s, - i1 => s28, - i0 => b8); - bm27 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b27s, - i1 => s27, - i0 => b7); - bm26 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b26s, - i1 => s26, - i0 => b6); - bm25 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b25s, - i1 => s25, - i0 => b5); - bm24 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b24s, - i1 => s24, - i0 => b4); - bm23 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b23s, - i1 => s23, - i0 => b3); - bm22 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b22s, - i1 => s22, - i0 => b2); - bm21 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b21s, - i1 => s21, - i0 => b1); - ob412 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ob412s, - i3 => b213s, - i2 => b214s, - i1 => b215s, - i0 => b216s); - ob422 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ob422s, - i3 => b29s, - i2 => b210s, - i1 => b211s, - i0 => b212s); - ob432 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ob432s, - i3 => b25s, - i2 => b26s, - i1 => b27s, - i0 => b28s); - ob442 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ob442s, - i3 => b21s, - i2 => b22s, - i1 => b23s, - i0 => b24s); - ob452 : na4_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => rb(2), - i3 => ob442s, - i2 => ob432s, - i1 => ob422s, - i0 => ob412s); - bm116 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b116s, - i1 => s116, - i0 => b16); - bm115 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b115s, - i1 => s115, - i0 => b15); - bm114 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b114s, - i1 => s114, - i0 => b14); - bm113 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b113s, - i1 => s113, - i0 => b13); - bm112 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b112s, - i1 => s112, - i0 => b12); - bm111 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b111s, - i1 => s111, - i0 => b11); - bm110 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b110s, - i1 => s110, - i0 => b10); - bm19 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b19s, - i1 => s19, - i0 => b9); - bm18 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b18s, - i1 => s18, - i0 => b8); - bm17 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b17s, - i1 => s17, - i0 => b7); - bm16 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b16s, - i1 => s16, - i0 => b6); - bm15 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b15s, - i1 => s15, - i0 => b5); - bm14 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b14s, - i1 => s14, - i0 => b4); - bm13 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b13s, - i1 => s13, - i0 => b3); - bm12 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b12s, - i1 => s12, - i0 => b2); - bm11 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b11s, - i1 => s11, - i0 => b1); - ob411 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ob411s, - i3 => b113s, - i2 => b114s, - i1 => b115s, - i0 => b116s); - ob421 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ob421s, - i3 => b19s, - i2 => b110s, - i1 => b111s, - i0 => b112s); - ob431 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ob431s, - i3 => b15s, - i2 => b16s, - i1 => b17s, - i0 => b18s); - ob441 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ob441s, - i3 => b11s, - i2 => b12s, - i1 => b13s, - i0 => b14s); - ob451 : na4_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => rb(1), - i3 => ob441s, - i2 => ob431s, - i1 => ob421s, - i0 => ob411s); - bm016 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b016s, - i1 => s016, - i0 => b16); - bm015 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b015s, - i1 => s015, - i0 => b15); - bm014 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b014s, - i1 => s014, - i0 => b14); - bm013 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b013s, - i1 => s013, - i0 => b13); - bm012 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b012s, - i1 => s012, - i0 => b12); - bm011 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b011s, - i1 => s011, - i0 => b11); - bm010 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b010s, - i1 => s010, - i0 => b10); - bm09 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b09s, - i1 => s09, - i0 => b9); - bm08 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b08s, - i1 => s08, - i0 => b8); - bm07 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b07s, - i1 => s07, - i0 => b7); - bm06 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b06s, - i1 => s06, - i0 => b6); - bm05 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b05s, - i1 => s05, - i0 => b5); - bm04 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b04s, - i1 => s04, - i0 => b4); - bm03 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b03s, - i1 => s03, - i0 => b3); - bm02 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b02s, - i1 => s02, - i0 => b2); - bm01 : na2_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => b01s, - i1 => s01, - i0 => b1); - ob410 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ob410s, - i3 => b013s, - i2 => b014s, - i1 => b015s, - i0 => b016s); - ob420 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ob420s, - i3 => b09s, - i2 => b010s, - i1 => b011s, - i0 => b012s); - ob430 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ob430s, - i3 => b05s, - i2 => b06s, - i1 => b07s, - i0 => b08s); - ob440 : a4_y - PORT MAP ( - vss => vss, - vdd => vdd, - t => ob440s, - i3 => b01s, - i2 => b02s, - i1 => b03s, - i0 => b04s); - ob450 : na4_y - PORT MAP ( - vss => vss, - vdd => vdd, - f => rb(0), - i3 => ob440s, - i2 => ob430s, - i1 => ob420s, - i0 => ob410s); - -end VST; diff --git a/alliance/share/tutorials/amd2901/result_beh.pat b/alliance/share/tutorials/amd2901/result_beh.pat deleted file mode 100644 index bce1a81c..00000000 --- a/alliance/share/tutorials/amd2901/result_beh.pat +++ /dev/null @@ -1,548 +0,0 @@ - --- description generated by Pat driver v104 --- date : Sun Sep 27 12:27:16 1998 - - --- sequence : pattern - --- input / output list : -in a (3 downto 0) X;; -in b (3 downto 0) X;; -in d (3 downto 0) X;; -in i (8 downto 0) O;; -in fonc B;; -in test B;; -in scin B;; -in noe B;; -in cke B;; -in cin B;; -inout r0 B;; -inout r3 B;; -inout q0 B;; -inout q3 B;; -out y (3 downto 0) X;; -out zero B;; -out signe B;; -out scout B;; -out ovr B;; -out np B;; -out ng B;; -out cout B;; -in vdde B;; -in vsse B;; -in vddi B;; -in vssi B;; - -begin - --- Pattern description : - --- a b d i f t s n c c r r q q y z s s o n n c v v v v --- o e c o k i 0 3 0 3 e i c v p g o d s d s --- n s i e e n r g o r u d s d s --- c t n o n u t e e i i --- e t - -accu_0 : 0 0 5 007 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 0 5 007 1 0 0 0 1 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 0 5 007 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 0 5 462 1 0 0 0 0 0 ?1 1 ?1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 0 5 462 1 0 0 0 1 0 ?1 1 ?1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 0 5 462 1 0 0 0 0 0 ?0 1 ?0 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 1 5 462 1 0 0 0 0 0 ?0 0 ?0 0 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 1 5 462 1 0 0 0 1 0 ?0 0 ?0 0 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 1 5 462 1 0 0 0 0 0 ?1 0 ?1 0 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 2 5 432 1 0 0 0 0 0 ?1 1 ?1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 2 5 432 1 0 0 0 1 0 ?1 1 ?1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 2 5 432 1 0 0 0 0 0 ?0 1 ?0 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 3 5 432 1 0 0 0 0 0 ?0 0 ?0 0 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 3 5 432 1 0 0 0 1 0 ?0 0 ?0 0 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 3 5 432 1 0 0 0 0 0 ?1 0 ?1 0 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 1 4 5 564 1 0 0 0 0 0 ?1 1 ?1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 1 4 5 564 1 0 0 0 1 0 ?1 1 ?1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 1 4 5 564 1 0 0 0 0 0 ?1 1 ?1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 2 5 5 564 1 0 0 0 0 0 ?0 0 ?1 0 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 2 5 5 564 1 0 0 0 1 0 ?0 0 ?1 0 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 2 5 5 564 1 0 0 0 0 0 ?0 0 ?1 0 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 3 6 5 534 1 0 0 0 0 0 ?1 1 ?1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 3 6 5 534 1 0 0 0 1 0 ?1 1 ?1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 3 6 5 534 1 0 0 0 0 0 ?1 1 ?1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 7 5 534 1 0 0 0 0 0 ?0 0 ?1 0 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 7 5 534 1 0 0 0 1 0 ?0 0 ?1 0 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 7 5 534 1 0 0 0 0 0 ?0 0 ?1 0 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 0 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 0 5 163 1 0 0 0 1 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 0 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 1 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 1 5 163 1 0 0 0 1 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 1 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 2 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 2 5 163 1 0 0 0 1 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 2 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 3 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 3 5 163 1 0 0 0 1 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 3 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 4 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 4 5 163 1 0 0 0 1 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 4 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 5 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 5 5 163 1 0 0 0 1 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 5 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 6 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 6 5 163 1 0 0 0 1 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 6 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 7 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 7 5 163 1 0 0 0 1 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 7 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 7 5 034 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 7 5 034 1 0 0 0 1 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 7 5 034 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 0 5 662 1 0 0 0 0 0 1 ?1 1 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 0 5 662 1 0 0 0 1 0 1 ?1 1 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 0 5 662 1 0 0 0 0 0 1 ?0 1 ?0 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 1 5 662 1 0 0 0 0 0 0 ?0 0 ?0 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 1 5 662 1 0 0 0 1 0 0 ?0 0 ?0 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 1 5 662 1 0 0 0 0 0 0 ?1 0 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 2 5 632 1 0 0 0 0 0 1 ?1 1 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 2 5 632 1 0 0 0 1 0 1 ?1 1 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 2 5 632 1 0 0 0 0 0 1 ?0 1 ?0 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 3 5 632 1 0 0 0 0 0 0 ?0 0 ?0 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 3 5 632 1 0 0 0 1 0 0 ?0 0 ?0 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 3 5 632 1 0 0 0 0 0 0 ?1 0 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 1 4 5 764 1 0 0 0 0 0 1 ?1 1 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 1 4 5 764 1 0 0 0 1 0 1 ?1 1 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 1 4 5 764 1 0 0 0 0 0 1 ?1 1 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 2 5 5 764 1 0 0 0 0 0 0 ?0 0 ?1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 2 5 5 764 1 0 0 0 1 0 0 ?0 0 ?1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 2 5 5 764 1 0 0 0 0 0 0 ?0 0 ?1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 3 6 5 734 1 0 0 0 0 0 1 ?1 1 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 3 6 5 734 1 0 0 0 1 0 1 ?1 1 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 3 6 5 734 1 0 0 0 0 0 1 ?1 1 ?1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 7 5 734 1 0 0 0 0 0 0 ?0 0 ?1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 7 5 734 1 0 0 0 1 0 0 ?0 0 ?1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 7 5 734 1 0 0 0 0 0 0 ?0 0 ?1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 0 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 0 5 163 1 0 0 0 1 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 0 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 1 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 1 5 163 1 0 0 0 1 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 1 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 2 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 2 5 163 1 0 0 0 1 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 2 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 3 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 3 5 163 1 0 0 0 1 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 3 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 4 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 4 5 163 1 0 0 0 1 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 4 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 5 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 5 5 163 1 0 0 0 1 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 5 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 6 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 6 5 163 1 0 0 0 1 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 6 5 163 1 0 0 0 0 0 1 1 1 1 ?5 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 7 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 7 5 163 1 0 0 0 1 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 7 5 163 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; -ram_102 : 4 0 f 367 1 0 0 0 0 0 1 1 1 1 ?f ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 0 f 367 1 0 0 0 1 0 1 1 1 1 ?f ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 0 f 367 1 0 0 0 0 0 1 1 1 1 ?f ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 1 e 267 1 0 0 0 0 0 1 1 1 1 ?f ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 1 e 267 1 0 0 0 1 0 1 1 1 1 ?f ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 0 1 e 267 1 0 0 0 0 0 1 1 1 1 ?f ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 1 2 d 267 1 0 0 0 0 0 1 1 1 1 ?e ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 1 2 d 267 1 0 0 0 1 0 1 1 1 1 ?e ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 1 2 d 267 1 0 0 0 0 0 1 1 1 1 ?e ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 2 3 c 267 1 0 0 0 0 0 1 1 1 1 ?d ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 2 3 c 267 1 0 0 0 1 0 1 1 1 1 ?d ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 2 3 c 267 1 0 0 0 0 0 1 1 1 1 ?d ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 3 4 b 267 1 0 0 0 0 0 1 1 1 1 ?c ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 3 4 b 267 1 0 0 0 1 0 1 1 1 1 ?c ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 3 4 b 267 1 0 0 0 0 0 1 1 1 1 ?c ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 5 a 267 1 0 0 0 0 0 1 1 1 1 ?b ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 5 a 267 1 0 0 0 1 0 1 1 1 1 ?b ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 4 5 a 267 1 0 0 0 0 0 1 1 1 1 ?b ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 5 6 9 267 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 5 6 9 267 1 0 0 0 1 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 5 6 9 267 1 0 0 0 0 0 1 1 1 1 ?a ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 6 7 8 267 1 0 0 0 0 0 1 1 1 1 ?9 ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 6 7 8 267 1 0 0 0 1 0 1 1 1 1 ?9 ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 6 7 8 267 1 0 0 0 0 0 1 1 1 1 ?9 ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 7 8 7 267 1 0 0 0 0 0 1 1 1 1 ?8 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 7 8 7 267 1 0 0 0 1 0 1 1 1 1 ?8 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : 7 8 7 267 1 0 0 0 0 0 1 1 1 1 ?8 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; 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- : f f 0 161 1 0 0 0 0 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f 0 161 1 0 0 0 1 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f 0 161 1 0 0 0 0 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f 0 163 1 0 0 0 0 1 1 1 1 1 ?f ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f 0 163 1 0 0 0 1 1 1 1 1 1 ?f ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f 0 163 1 0 0 0 0 1 1 1 1 1 ?f ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f 0 171 1 0 0 0 0 1 1 1 1 1 ?f ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f 0 171 1 0 0 0 1 1 1 1 1 1 ?f ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f 0 171 1 0 0 0 0 1 1 1 1 1 ?f ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f 0 173 1 0 0 0 0 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f 0 173 1 0 0 0 1 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f 0 173 1 0 0 0 0 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; -scan_471 : f f e 067 1 0 0 0 0 1 1 1 1 1 ?e ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 067 1 0 0 0 1 1 1 1 1 1 ?e ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 067 1 0 0 0 0 1 1 1 1 1 ?e ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 1 0 0 0 0 1 1 1 1 1 ?e ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 1 0 0 0 1 1 1 1 1 1 ?e ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 1 0 0 0 0 1 1 1 1 1 ?e ?0 ?1 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 0 0 0 1 1 1 1 1 ?e ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 0 0 1 1 1 1 1 1 ?e ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 0 0 0 1 1 1 1 1 ?c ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 1 0 0 1 1 1 1 1 ?c ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 1 0 1 1 1 1 1 1 ?c ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 1 0 0 1 1 1 1 1 ?9 ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 0 0 0 1 1 1 1 1 ?9 ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 0 0 1 1 1 1 1 1 ?9 ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 0 0 0 1 1 1 1 1 ?2 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 0 0 0 1 1 1 1 1 ?2 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 0 0 1 1 1 1 1 1 ?2 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 0 0 0 1 1 1 1 1 ?4 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 0 0 0 1 1 1 1 1 ?4 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 0 0 1 1 1 1 1 1 ?4 ?0 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 0 0 0 1 1 1 1 1 ?8 ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 0 0 0 1 1 1 1 1 ?8 ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 0 0 1 1 1 1 1 1 ?8 ?0 ?1 ?1 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 0 0 0 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 0 0 0 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 0 0 1 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 0 0 0 1 1 1 1 1 ?0 ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; -high_z_498 : f f e 162 0 1 0 1 0 1 1 1 1 1 ?f ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 0 1 1 1 1 1 1 1 ?f ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - : f f e 162 0 1 0 1 0 1 1 1 1 1 ?f ?1 ?0 ?0 ?0 ?1 ?1 ?0 1 0 1 0 ; - -end;