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buggy tutorials...

This commit is contained in:
Olivier Sirol 2000-01-19 14:23:31 +00:00
parent 47ff41e696
commit 92da76f9fa
16 changed files with 111 additions and 11634 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1077
alliance/share/tutorials/addaccu/addaccu.ap
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File diff suppressed because it is too large Load Diff

7242
alliance/share/tutorials/addaccu/addaccu.cif
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File diff suppressed because it is too large Load Diff

2
alliance/share/tutorials/addaccu/addaccu.drc
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@ -1,2 +0,0 @@
addaccu

57
alliance/share/tutorials/addaccu/addaccu.proof
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@ -1,57 +0,0 @@
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Formal Proof
Alliance CAD System 3.5, proof 4.20 [1997/10/09]
Copyright (c) 1990-1998, ASIM/LIP6/UPMC
E-mail support: alliance-support@asim.lip6.fr
================================ Environment ================================
MBK_WORK_LIB = .
MBK_CATA_LIB = .:/asim/alliance/cells/sclib:/users/cao7/czo/dev/LOGIC_BUG
======================= Files, Options and Parameters =======================
First VHDL file = addaccue.vbe
Second VHDL file = addaccu.vbe
The auxiliary signals are erased
Errors are displayed
===============================================================================
Compiling 'addaccue' ...
Compiling 'addaccu' ...
Running abl ordonnancer on `addaccue`
........
Running Abl2Bdd on `addaccue`
---> final number of nodes = 610(366)
Running Abl2Bdd on `addaccu`
--------------------------------------------------------------------------------
Formal proof with Ordered Binary Decision Diagrams between
'./addaccue' and './addaccu'
--------------------------------------------------------------------------------
============================== PRIMARY OUTPUT ===============================
============================= AUXILIARY SIGNAL ==============================
============================== REGISTER SIGNAL ==============================
=============================== EXTERNAL BUS =================================
================================ INTERNAL BUS =================================
Formal Proof : OK
pppppppppppppppppppppppprrrrrrrrrrrrooooooooooooooooooooooooooooofffffffffffffff
--------------------------------------------------------------------------------

301
alliance/share/tutorials/addaccu/addaccu.vst
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@ -1,301 +0,0 @@
-- VHDL structural description generated from `addaccu`
-- date : Sun Sep 27 12:26:13 1998
-- Entity Declaration
ENTITY addaccu IS
PORT (
a : in BIT_VECTOR (0 TO 3); -- a
b : in BIT_VECTOR (0 TO 3); -- b
sel : in BIT; -- sel
ck : in BIT; -- ck
vdd : in BIT; -- vdd
vss : in BIT; -- vss
vdde : in BIT; -- vdde
vsse : in BIT; -- vsse
s : out BIT_VECTOR (0 TO 3) -- s
);
END addaccu;
-- Architecture Declaration
ARCHITECTURE VST OF addaccu IS
COMPONENT pvsse_sp
port (
ck : in BIT; -- ck
vdde : in BIT; -- vdde
vddi : in BIT; -- vddi
vsse : in BIT; -- vsse
vssi : in BIT -- vssi
);
END COMPONENT;
COMPONENT pvddeck_sp
port (
cko : linkage BIT; -- cko
ck : in BIT; -- ck
vdde : in BIT; -- vdde
vddi : in BIT; -- vddi
vsse : in BIT; -- vsse
vssi : in BIT -- vssi
);
END COMPONENT;
COMPONENT pvssi_sp
port (
ck : in BIT; -- ck
vdde : in BIT; -- vdde
vddi : in BIT; -- vddi
vsse : in BIT; -- vsse
vssi : in BIT -- vssi
);
END COMPONENT;
COMPONENT pvddi_sp
port (
ck : in BIT; -- ck
vdde : in BIT; -- vdde
vddi : in BIT; -- vddi
vsse : in BIT; -- vsse
vssi : in BIT -- vssi
);
END COMPONENT;
COMPONENT po_sp
port (
i : in BIT; -- i
pad : out BIT; -- pad
ck : in BIT; -- ck
vdde : in BIT; -- vdde
vddi : in BIT; -- vddi
vsse : in BIT; -- vsse
vssi : in BIT -- vssi
);
END COMPONENT;
COMPONENT pi_sp
port (
pad : in BIT; -- pad
t : out BIT; -- t
ck : in BIT; -- ck
vdde : in BIT; -- vdde
vddi : in BIT; -- vddi
vsse : in BIT; -- vsse
vssi : in BIT -- vssi
);
END COMPONENT;
COMPONENT pck_sp
port (
pad : in BIT; -- pad
ck : out BIT; -- ck
vdde : in BIT; -- vdde
vddi : in BIT; -- vddi
vsse : in BIT; -- vsse
vssi : in BIT -- vssi
);
END COMPONENT;
COMPONENT core
port (
a : in BIT_VECTOR(0 TO 3); -- a
b : in BIT_VECTOR(0 TO 3); -- b
sel : in BIT; -- sel
ck : in BIT; -- ck
s : inout BIT_VECTOR(0 TO 3); -- s
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
SIGNAL aa_0 : BIT; -- aa 0
SIGNAL aa_1 : BIT; -- aa 1
SIGNAL aa_2 : BIT; -- aa 2
SIGNAL aa_3 : BIT; -- aa 3
SIGNAL bb_0 : BIT; -- bb 0
SIGNAL bb_1 : BIT; -- bb 1
SIGNAL bb_2 : BIT; -- bb 2
SIGNAL bb_3 : BIT; -- bb 3
SIGNAL cki : BIT; -- cki
SIGNAL clock : BIT; -- clock
SIGNAL selsel : BIT; -- selsel
SIGNAL ss_0 : BIT; -- ss 0
SIGNAL ss_1 : BIT; -- ss 1
SIGNAL ss_2 : BIT; -- ss 2
SIGNAL ss_3 : BIT; -- ss 3
BEGIN
p15 : pvsse_sp
PORT MAP (
vssi => vss,
vsse => vsse,
vddi => vdd,
vdde => vdde,
ck => cki);
p16 : pvsse_sp
PORT MAP (
vssi => vss,
vsse => vsse,
vddi => vdd,
vdde => vdde,
ck => cki);
p17 : pvddeck_sp
PORT MAP (
vssi => vss,
vsse => vsse,
vddi => vdd,
vdde => vdde,
ck => cki,
cko => clock);
p18 : pvssi_sp
PORT MAP (
vssi => vss,
vsse => vsse,
vddi => vdd,
vdde => vdde,
ck => cki);
p19 : pvddi_sp
PORT MAP (
vssi => vss,
vsse => vsse,
vddi => vdd,
vdde => vdde,
ck => cki);
p0 : pi_sp
PORT MAP (
vssi => vss,
vsse => vsse,
vddi => vdd,
vdde => vdde,
ck => cki,
t => aa_0,
pad => a(0));
p1 : pi_sp
PORT MAP (
vssi => vss,
vsse => vsse,
vddi => vdd,
vdde => vdde,
ck => cki,
t => aa_1,
pad => a(1));
p2 : pi_sp
PORT MAP (
vssi => vss,
vsse => vsse,
vddi => vdd,
vdde => vdde,
ck => cki,
t => aa_2,
pad => a(2));
p3 : pi_sp
PORT MAP (
vssi => vss,
vsse => vsse,
vddi => vdd,
vdde => vdde,
ck => cki,
t => aa_3,
pad => a(3));
p4 : pi_sp
PORT MAP (
vssi => vss,
vsse => vsse,
vddi => vdd,
vdde => vdde,
ck => cki,
t => bb_0,
pad => b(0));
p5 : pi_sp
PORT MAP (
vssi => vss,
vsse => vsse,
vddi => vdd,
vdde => vdde,
ck => cki,
t => bb_1,
pad => b(1));
p6 : pi_sp
PORT MAP (
vssi => vss,
vsse => vsse,
vddi => vdd,
vdde => vdde,
ck => cki,
t => bb_2,
pad => b(2));
p7 : pi_sp
PORT MAP (
vssi => vss,
vsse => vsse,
vddi => vdd,
vdde => vdde,
ck => cki,
t => bb_3,
pad => b(3));
p8 : po_sp
PORT MAP (
vssi => vss,
vsse => vsse,
vddi => vdd,
vdde => vdde,
ck => cki,
pad => s(0),
i => ss_0);
p9 : po_sp
PORT MAP (
vssi => vss,
vsse => vsse,
vddi => vdd,
vdde => vdde,
ck => cki,
pad => s(1),
i => ss_1);
p10 : po_sp
PORT MAP (
vssi => vss,
vsse => vsse,
vddi => vdd,
vdde => vdde,
ck => cki,
pad => s(2),
i => ss_2);
p11 : po_sp
PORT MAP (
vssi => vss,
vsse => vsse,
vddi => vdd,
vdde => vdde,
ck => cki,
pad => s(3),
i => ss_3);
p12 : pi_sp
PORT MAP (
vssi => vss,
vsse => vsse,
vddi => vdd,
vdde => vdde,
ck => cki,
t => selsel,
pad => sel);
p13 : pck_sp
PORT MAP (
vssi => vss,
vsse => vsse,
vddi => vdd,
vdde => vdde,
ck => cki,
pad => ck);
core : core
PORT MAP (
vss => vss,
vdd => vdd,
s => ss_0& ss_1& ss_2& ss_3,
ck => clock,
sel => selsel,
b => bb_0& bb_1& bb_2& bb_3,
a => aa_0& aa_1& aa_2& aa_3);
end VST;

12
alliance/share/tutorials/addaccu/addaccu_drc.cif
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@ -1,12 +0,0 @@
(rds to CIF driver version 1.03
technology /asim/alliance/etc/cmos_7.rds
Sun Sep 27 12:26:41 1998
addaccu_drc
czo);
DS1 50 2;
9 addaccu_drc;
DF;
C1;
E

735
alliance/share/tutorials/addaccu/addaccu_rng.cif
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@ -1,735 +0,0 @@
(rds to CIF driver version 1.03
technology /asim/alliance/etc/cmos_7.rds
Sun Sep 27 12:26:28 1998
addaccu_rng
czo);
DS1 50 2;
9 addaccu_rng;
(AB : -670.00, -845.00 1207.00, 1015.00 in micron);
4A -2680 -3380 4828 4060;
LLALU1;
4N s[2] 4426 -692;
B808 400 4426 -692;
B1408 12 4126 -524;
B1408 12 4126 -572;
B1408 12 4126 -620;
B1408 12 4126 -668;
B1408 12 4126 -716;
B1408 12 4126 -764;
B1408 12 4126 -812;
B1408 12 4126 -860;
4N s[3] 4426 -4;
B808 400 4426 -4;
B1408 12 4126 164;
B1408 12 4126 116;
B1408 12 4126 68;
B1408 12 4126 20;
B1408 12 4126 -28;
B1408 12 4126 -76;
B1408 12 4126 -124;
B1408 12 4126 -172;
B1476 12 4092 680;
B808 40 4426 684;
4N sel 4556 684;
B548 400 4556 684;
B548 400 4556 1372;
4N ck 4426 1372;
B808 40 4426 1372;
B1476 12 4092 1368;
B1476 12 -1944 -1040;
B808 40 -2278 -1036;
4N a[0] -2408 -1036;
B548 400 -2408 -1036;
B1476 12 -1944 -352;
B808 40 -2278 -348;
4N a[1] -2408 -348;
B548 400 -2408 -348;
B1476 12 -1944 336;
B808 40 -2278 340;
4N a[2] -2408 340;
B548 400 -2408 340;
B1476 12 -1944 1024;
B808 40 -2278 1028;
4N a[3] -2408 1028;
B548 400 -2408 1028;
B1476 12 -1944 1712;
B808 40 -2278 1716;
4N b[0] -2408 1716;
B548 400 -2408 1716;
4N vsse -272 -2866;
B400 1032 -272 -2866;
4N vsse 416 -2866;
B400 1032 416 -2866;
4N vss 1104 -2380;
B400 2004 1104 -2380;
4N vdd 1792 -2380;
B400 2004 1792 -2380;
4N vdde 2480 -2610;
B400 1544 2480 -2610;
B12 1476 -340 3324;
B40 808 -336 3658;
4N b[1] -336 3788;
B400 548 -336 3788;
B12 1476 348 3324;
B40 808 352 3658;
4N b[2] 352 3788;
B400 548 352 3788;
B12 1476 1036 3324;
B40 808 1040 3658;
4N b[3] 1040 3788;
B400 548 1040 3788;
4N s[0] 1728 3658;
B400 808 1728 3658;
B12 1408 1896 3358;
B12 1408 1848 3358;
B12 1408 1800 3358;
B12 1408 1752 3358;
B12 1408 1704 3358;
B12 1408 1656 3358;
B12 1408 1608 3358;
B12 1408 1560 3358;
4N s[1] 2416 3658;
B400 808 2416 3658;
B12 1408 2584 3358;
B12 1408 2536 3358;
B12 1408 2488 3358;
B12 1408 2440 3358;
B12 1408 2392 3358;
B12 1408 2344 3358;
B12 1408 2296 3358;
B12 1408 2248 3358;
B488 488 4584 -692;
B488 488 4584 -4;
B488 488 4584 684;
B488 488 4584 1372;
B488 488 -2436 -1036;
B488 488 -2436 -348;
B488 488 -2436 340;
B488 488 -2436 1028;
B488 488 -2436 1716;
B488 488 -272 -3136;
B488 488 416 -3136;
B488 488 1104 -3136;
B488 488 1792 -3136;
B488 488 2480 -3136;
B488 488 -336 3816;
B488 488 352 3816;
B488 488 1040 3816;
B488 488 1728 3816;
B488 488 2416 3816;
LLVIA1;
B4 4 4824 -452;
B4 4 4824 -468;
B4 4 4824 -484;
B4 4 4824 -500;
B4 4 4824 -516;
B4 4 4824 -532;
B4 4 4824 -548;
B4 4 4824 -564;
B4 4 4824 -580;
B4 4 4824 -596;
B4 4 4824 -612;
B4 4 4824 -628;
B4 4 4824 -644;
B4 4 4824 -660;
B4 4 4824 -676;
B4 4 4824 -692;
B4 4 4824 -708;
B4 4 4824 -724;
B4 4 4824 -740;
B4 4 4824 -756;
B4 4 4824 -772;
B4 4 4824 -788;
B4 4 4824 -804;
B4 4 4824 -820;
B4 4 4824 -836;
B4 4 4824 -852;
B4 4 4824 -868;
B4 4 4824 -884;
B4 4 4824 -900;
B4 4 4824 -916;
B4 4 4824 -932;
B4 4 4824 236;
B4 4 4824 220;
B4 4 4824 204;
B4 4 4824 188;
B4 4 4824 172;
B4 4 4824 156;
B4 4 4824 140;
B4 4 4824 124;
B4 4 4824 108;
B4 4 4824 92;
B4 4 4824 76;
B4 4 4824 60;
B4 4 4824 44;
B4 4 4824 28;
B4 4 4824 12;
B4 4 4824 -4;
B4 4 4824 -20;
B4 4 4824 -36;
B4 4 4824 -52;
B4 4 4824 -68;
B4 4 4824 -84;
B4 4 4824 -100;
B4 4 4824 -116;
B4 4 4824 -132;
B4 4 4824 -148;
B4 4 4824 -164;
B4 4 4824 -180;
B4 4 4824 -196;
B4 4 4824 -212;
B4 4 4824 -228;
B4 4 4824 -244;
B4 4 4824 924;
B4 4 4824 908;
B4 4 4824 892;
B4 4 4824 876;
B4 4 4824 860;
B4 4 4824 844;
B4 4 4824 828;
B4 4 4824 812;
B4 4 4824 796;
B4 4 4824 780;
B4 4 4824 764;
B4 4 4824 748;
B4 4 4824 732;
B4 4 4824 716;
B4 4 4824 700;
B4 4 4824 684;
B4 4 4824 668;
B4 4 4824 652;
B4 4 4824 636;
B4 4 4824 620;
B4 4 4824 604;
B4 4 4824 588;
B4 4 4824 572;
B4 4 4824 556;
B4 4 4824 540;
B4 4 4824 524;
B4 4 4824 508;
B4 4 4824 492;
B4 4 4824 476;
B4 4 4824 460;
B4 4 4824 444;
B4 4 4824 1612;
B4 4 4824 1596;
B4 4 4824 1580;
B4 4 4824 1564;
B4 4 4824 1548;
B4 4 4824 1532;
B4 4 4824 1516;
B4 4 4824 1500;
B4 4 4824 1484;
B4 4 4824 1468;
B4 4 4824 1452;
B4 4 4824 1436;
B4 4 4824 1420;
B4 4 4824 1404;
B4 4 4824 1388;
B4 4 4824 1372;
B4 4 4824 1356;
B4 4 4824 1340;
B4 4 4824 1324;
B4 4 4824 1308;
B4 4 4824 1292;
B4 4 4824 1276;
B4 4 4824 1260;
B4 4 4824 1244;
B4 4 4824 1228;
B4 4 4824 1212;
B4 4 4824 1196;
B4 4 4824 1180;
B4 4 4824 1164;
B4 4 4824 1148;
B4 4 4824 1132;
B4 4 -2676 -796;
B4 4 -2676 -812;
B4 4 -2676 -828;
B4 4 -2676 -844;
B4 4 -2676 -860;
B4 4 -2676 -876;
B4 4 -2676 -892;
B4 4 -2676 -908;
B4 4 -2676 -924;
B4 4 -2676 -940;
B4 4 -2676 -956;
B4 4 -2676 -972;
B4 4 -2676 -988;
B4 4 -2676 -1004;
B4 4 -2676 -1020;
B4 4 -2676 -1036;
B4 4 -2676 -1052;
B4 4 -2676 -1068;
B4 4 -2676 -1084;
B4 4 -2676 -1100;
B4 4 -2676 -1116;
B4 4 -2676 -1132;
B4 4 -2676 -1148;
B4 4 -2676 -1164;
B4 4 -2676 -1180;
B4 4 -2676 -1196;
B4 4 -2676 -1212;
B4 4 -2676 -1228;
B4 4 -2676 -1244;
B4 4 -2676 -1260;
B4 4 -2676 -1276;
B4 4 -2676 -108;
B4 4 -2676 -124;
B4 4 -2676 -140;
B4 4 -2676 -156;
B4 4 -2676 -172;
B4 4 -2676 -188;
B4 4 -2676 -204;
B4 4 -2676 -220;
B4 4 -2676 -236;
B4 4 -2676 -252;
B4 4 -2676 -268;
B4 4 -2676 -284;
B4 4 -2676 -300;
B4 4 -2676 -316;
B4 4 -2676 -332;
B4 4 -2676 -348;
B4 4 -2676 -364;
B4 4 -2676 -380;
B4 4 -2676 -396;
B4 4 -2676 -412;
B4 4 -2676 -428;
B4 4 -2676 -444;
B4 4 -2676 -460;
B4 4 -2676 -476;
B4 4 -2676 -492;
B4 4 -2676 -508;
B4 4 -2676 -524;
B4 4 -2676 -540;
B4 4 -2676 -556;
B4 4 -2676 -572;
B4 4 -2676 -588;
B4 4 -2676 580;
B4 4 -2676 564;
B4 4 -2676 548;
B4 4 -2676 532;
B4 4 -2676 516;
B4 4 -2676 500;
B4 4 -2676 484;
B4 4 -2676 468;
B4 4 -2676 452;
B4 4 -2676 436;
B4 4 -2676 420;
B4 4 -2676 404;
B4 4 -2676 388;
B4 4 -2676 372;
B4 4 -2676 356;
B4 4 -2676 340;
B4 4 -2676 324;
B4 4 -2676 308;
B4 4 -2676 292;
B4 4 -2676 276;
B4 4 -2676 260;
B4 4 -2676 244;
B4 4 -2676 228;
B4 4 -2676 212;
B4 4 -2676 196;
B4 4 -2676 180;
B4 4 -2676 164;
B4 4 -2676 148;
B4 4 -2676 132;
B4 4 -2676 116;
B4 4 -2676 100;
B4 4 -2676 1268;
B4 4 -2676 1252;
B4 4 -2676 1236;
B4 4 -2676 1220;
B4 4 -2676 1204;
B4 4 -2676 1188;
B4 4 -2676 1172;
B4 4 -2676 1156;
B4 4 -2676 1140;
B4 4 -2676 1124;
B4 4 -2676 1108;
B4 4 -2676 1092;
B4 4 -2676 1076;
B4 4 -2676 1060;
B4 4 -2676 1044;
B4 4 -2676 1028;
B4 4 -2676 1012;
B4 4 -2676 996;
B4 4 -2676 980;
B4 4 -2676 964;
B4 4 -2676 948;
B4 4 -2676 932;
B4 4 -2676 916;
B4 4 -2676 900;
B4 4 -2676 884;
B4 4 -2676 868;
B4 4 -2676 852;
B4 4 -2676 836;
B4 4 -2676 820;
B4 4 -2676 804;
B4 4 -2676 788;
B4 4 -2676 1956;
B4 4 -2676 1940;
B4 4 -2676 1924;
B4 4 -2676 1908;
B4 4 -2676 1892;
B4 4 -2676 1876;
B4 4 -2676 1860;
B4 4 -2676 1844;
B4 4 -2676 1828;
B4 4 -2676 1812;
B4 4 -2676 1796;
B4 4 -2676 1780;
B4 4 -2676 1764;
B4 4 -2676 1748;
B4 4 -2676 1732;
B4 4 -2676 1716;
B4 4 -2676 1700;
B4 4 -2676 1684;
B4 4 -2676 1668;
B4 4 -2676 1652;
B4 4 -2676 1636;
B4 4 -2676 1620;
B4 4 -2676 1604;
B4 4 -2676 1588;
B4 4 -2676 1572;
B4 4 -2676 1556;
B4 4 -2676 1540;
B4 4 -2676 1524;
B4 4 -2676 1508;
B4 4 -2676 1492;
B4 4 -2676 1476;
B4 4 -32 -3376;
B4 4 -48 -3376;
B4 4 -64 -3376;
B4 4 -80 -3376;
B4 4 -96 -3376;
B4 4 -112 -3376;
B4 4 -128 -3376;
B4 4 -144 -3376;
B4 4 -160 -3376;
B4 4 -176 -3376;
B4 4 -192 -3376;
B4 4 -208 -3376;
B4 4 -224 -3376;
B4 4 -240 -3376;
B4 4 -256 -3376;
B4 4 -272 -3376;
B4 4 -288 -3376;
B4 4 -304 -3376;
B4 4 -320 -3376;
B4 4 -336 -3376;
B4 4 -352 -3376;
B4 4 -368 -3376;
B4 4 -384 -3376;
B4 4 -400 -3376;
B4 4 -416 -3376;
B4 4 -432 -3376;
B4 4 -448 -3376;
B4 4 -464 -3376;
B4 4 -480 -3376;
B4 4 -496 -3376;
B4 4 -512 -3376;
B4 4 656 -3376;
B4 4 640 -3376;
B4 4 624 -3376;
B4 4 608 -3376;
B4 4 592 -3376;
B4 4 576 -3376;
B4 4 560 -3376;
B4 4 544 -3376;
B4 4 528 -3376;
B4 4 512 -3376;
B4 4 496 -3376;
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LLALU2;
B492 492 4584 -692;
B492 492 4584 -4;
B492 492 4584 684;
B492 492 4584 1372;
B492 492 -2436 -1036;
B492 492 -2436 -348;
B492 492 -2436 340;
B492 492 -2436 1028;
B492 492 -2436 1716;
B492 492 -272 -3136;
B492 492 416 -3136;
B492 492 1104 -3136;
B492 492 1792 -3136;
B492 492 2480 -3136;
B492 492 -336 3816;
B492 492 352 3816;
B492 492 1040 3816;
B492 492 1728 3816;
B492 492 2416 3816;
DF;
C1;
(AB : -670.00, -845.00 1207.00, 1015.00 in micron);
E

868
alliance/share/tutorials/addaccu/addaccue.al
View File

@ -1,868 +0,0 @@
V ALLIANCE : 6
H addaccue,L,27/ 9/98
C vsse,UNKNOWN,EXTERNAL,1
C vss,UNKNOWN,EXTERNAL,2
C vdde,UNKNOWN,EXTERNAL,4
C vdd,UNKNOWN,EXTERNAL,3
C sel,UNKNOWN,EXTERNAL,136
C s 3,UNKNOWN,EXTERNAL,19
C s 2,UNKNOWN,EXTERNAL,11
C s 1,UNKNOWN,EXTERNAL,169
C s 0,UNKNOWN,EXTERNAL,168
C ck,UNKNOWN,EXTERNAL,153
C b 3,UNKNOWN,EXTERNAL,161
C b 2,UNKNOWN,EXTERNAL,159
C b 1,UNKNOWN,EXTERNAL,157
C b 0,UNKNOWN,EXTERNAL,154
C a 3,UNKNOWN,EXTERNAL,150
C a 2,UNKNOWN,EXTERNAL,28
C a 1,UNKNOWN,EXTERNAL,16
C a 0,UNKNOWN,EXTERNAL,8
T P,1,80,4,12,11,0,2,2,164,164,894.5,-104,tr_00678
T P,1,80,11,12,4,0,2,2,164,164,894.5,-110,tr_00677
T P,1,80,4,12,11,0,2,2,164,164,894.5,-116,tr_00676
T P,1,80,11,12,4,0,2,2,164,164,894.5,-122,tr_00675
T P,1,80,4,12,11,0,2,2,164,164,894.5,-128,tr_00674
T P,1,80,11,12,4,0,2,2,164,164,894.5,-134,tr_00673
T P,1,80,4,12,11,0,2,2,164,164,894.5,-140,tr_00672
T P,1,80,11,12,4,0,2,2,164,164,894.5,-146,tr_00671
T P,1,80,4,12,11,0,2,2,164,164,894.5,-152,tr_00670
T P,1,80,11,12,4,0,2,2,164,164,894.5,-158,tr_00669
T P,1,80,4,12,11,0,2,2,164,164,894.5,-164,tr_00668
T P,1,80,11,12,4,0,2,2,164,164,894.5,-170,tr_00667
T P,1,80,4,12,11,0,2,2,164,164,894.5,-176,tr_00666
T P,1,80,11,12,4,0,2,2,164,164,894.5,-182,tr_00665
T P,1,80,4,12,11,0,2,2,164,164,894.5,-188,tr_00664
T P,1,80,11,12,4,0,2,2,164,164,894.5,-194,tr_00663
T P,1,80,4,12,11,0,2,2,164,164,894.5,-200,tr_00662
T P,1,80,11,12,4,0,2,2,164,164,894.5,-206,tr_00661
T P,1,80,4,12,11,0,2,2,164,164,894.5,-212,tr_00660
T P,1,80,11,12,4,0,2,2,164,164,894.5,-218,tr_00659
T P,1,80,4,12,11,0,2,2,164,164,894.5,-224,tr_00658
T P,1,80,11,12,4,0,2,2,164,164,894.5,-230,tr_00657
T P,1,80,4,12,11,0,2,2,164,164,894.5,-236,tr_00656
T P,1,80,11,12,4,0,2,2,164,164,894.5,-242,tr_00655
T P,1,60,3,15,12,0,2,2,124,124,799.5,-178,tr_00654
T P,1,60,12,15,3,0,2,2,124,124,799.5,-184,tr_00653
T P,1,60,12,15,3,0,2,2,124,124,799.5,-196,tr_00652
T P,1,60,3,14,15,0,2,2,124,124,799.5,-202,tr_00651
T P,1,60,3,15,12,0,2,2,124,124,799.5,-190,tr_00650
T P,1,60,14,13,3,0,2,2,124,124,799.5,-214,tr_00649
T P,1,80,4,20,19,0,2,2,164,164,894.5,68,tr_00648
T P,1,80,19,20,4,0,2,2,164,164,894.5,62,tr_00647
T P,1,80,4,20,19,0,2,2,164,164,894.5,56,tr_00646
T P,1,80,19,20,4,0,2,2,164,164,894.5,50,tr_00645
T P,1,80,4,20,19,0,2,2,164,164,894.5,44,tr_00644
T P,1,80,19,20,4,0,2,2,164,164,894.5,38,tr_00643
T P,1,80,4,20,19,0,2,2,164,164,894.5,32,tr_00642
T P,1,80,19,20,4,0,2,2,164,164,894.5,26,tr_00641
T P,1,80,4,20,19,0,2,2,164,164,894.5,20,tr_00640
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T P,1,60,20,22,3,0,2,2,124,124,799.5,-24,tr_00622
T P,1,60,3,23,22,0,2,2,124,124,799.5,-30,tr_00621
T P,1,60,3,22,20,0,2,2,124,124,799.5,-18,tr_00620
T P,1,60,23,21,3,0,2,2,124,124,799.5,-42,tr_00619
T P,1,80,136,4,4,0,2,2,164,164,894.5,155,tr_00618
T P,1,80,4,4,136,0,2,2,164,164,894.5,161,tr_00617
T P,1,80,136,4,4,0,2,2,164,164,894.5,167,tr_00616
T P,1,80,4,4,136,0,2,2,164,164,894.5,173,tr_00615
T P,1,27,3,136,149,0,2,2,58,58,786,187,tr_00614
T P,1,57,27,149,3,0,2,2,118,118,801,164,tr_00613
T P,1,57,3,149,27,0,2,2,118,118,801,170,tr_00612
T P,1,80,4,4,153,0,2,2,164,164,894.5,345,tr_00611
T P,1,80,153,4,4,0,2,2,164,164,894.5,339,tr_00610
T P,1,80,4,4,153,0,2,2,164,164,894.5,333,tr_00609
T P,1,80,153,4,4,0,2,2,164,164,894.5,327,tr_00608
T P,1,57,6,152,3,0,2,2,118,118,801,294,tr_00607
T P,1,57,3,152,6,0,2,2,118,118,801,288,tr_00606
T P,1,57,6,152,3,0,2,2,118,118,801,282,tr_00605
T P,1,57,6,152,3,0,2,2,118,118,801,318,tr_00604
T P,1,57,3,152,6,0,2,2,118,118,801,312,tr_00603
T P,1,57,6,152,3,0,2,2,118,118,801,306,tr_00602
T P,1,57,3,152,6,0,2,2,118,118,801,300,tr_00601
T P,1,57,3,152,6,0,2,2,118,118,801,324,tr_00600
T P,1,27,3,153,152,0,2,2,58,58,786,341,tr_00599
T P,1,27,152,153,3,0,2,2,58,58,786,347,tr_00598
T P,1,27,3,153,152,0,2,2,58,58,786,353,tr_00597
T P,1,27,152,153,3,0,2,2,58,58,786,359,tr_00596
T P,1,80,8,4,4,0,2,2,164,164,-357.5,-275,tr_00595
T P,1,80,4,4,8,0,2,2,164,164,-357.5,-269,tr_00594
T P,1,80,8,4,4,0,2,2,164,164,-357.5,-263,tr_00593
T P,1,80,4,4,8,0,2,2,164,164,-357.5,-257,tr_00592
T P,1,27,3,8,10,0,2,2,58,58,-249,-243,tr_00591
T P,1,57,9,10,3,0,2,2,118,118,-264,-266,tr_00590
T P,1,57,3,10,9,0,2,2,118,118,-264,-260,tr_00589
T P,1,80,16,4,4,0,2,2,164,164,-357.5,-103,tr_00588
T P,1,80,4,4,16,0,2,2,164,164,-357.5,-97,tr_00587
T P,1,80,16,4,4,0,2,2,164,164,-357.5,-91,tr_00586
T P,1,80,4,4,16,0,2,2,164,164,-357.5,-85,tr_00585
T P,1,27,3,16,18,0,2,2,58,58,-249,-71,tr_00584
T P,1,57,17,18,3,0,2,2,118,118,-264,-94,tr_00583
T P,1,57,3,18,17,0,2,2,118,118,-264,-88,tr_00582
T P,1,80,28,4,4,0,2,2,164,164,-357.5,69,tr_00581
T P,1,80,4,4,28,0,2,2,164,164,-357.5,75,tr_00580
T P,1,80,28,4,4,0,2,2,164,164,-357.5,81,tr_00579
T P,1,80,4,4,28,0,2,2,164,164,-357.5,87,tr_00578
T P,1,27,3,28,91,0,2,2,58,58,-249,101,tr_00577
T P,1,57,24,91,3,0,2,2,118,118,-264,78,tr_00576
T P,1,57,3,91,24,0,2,2,118,118,-264,84,tr_00575
T P,1,80,150,4,4,0,2,2,164,164,-357.5,241,tr_00574
T P,1,80,4,4,150,0,2,2,164,164,-357.5,247,tr_00573
T P,1,80,150,4,4,0,2,2,164,164,-357.5,253,tr_00572
T P,1,80,4,4,150,0,2,2,164,164,-357.5,259,tr_00571
T P,1,27,3,150,151,0,2,2,58,58,-249,273,tr_00570
T P,1,57,25,151,3,0,2,2,118,118,-264,250,tr_00569
T P,1,57,3,151,25,0,2,2,118,118,-264,256,tr_00568
T P,1,80,154,4,4,0,2,2,164,164,-357.5,413,tr_00567
T P,1,80,4,4,154,0,2,2,164,164,-357.5,419,tr_00566
T P,1,80,154,4,4,0,2,2,164,164,-357.5,425,tr_00565
T P,1,80,4,4,154,0,2,2,164,164,-357.5,431,tr_00564
T P,1,27,3,154,155,0,2,2,58,58,-249,445,tr_00563
T P,1,57,105,155,3,0,2,2,118,118,-264,422,tr_00562
T P,1,57,3,155,105,0,2,2,118,118,-264,428,tr_00561
T P,1,40,5,6,3,0,2,2,84,84,586,-437.5,tr_00560
T P,1,34,7,5,3,0,2,2,72,72,622,-434.5,tr_00559
T P,1,34,3,5,7,0,2,2,72,72,616,-434.5,tr_00558
T P,1,34,7,5,3,0,2,2,72,72,610,-434.5,tr_00557
T P,1,34,3,5,7,0,2,2,72,72,604,-434.5,tr_00556
T P,1,34,7,5,3,0,2,2,72,72,598,-434.5,tr_00555
T P,1,80,157,4,4,0,2,2,164,164,-100,702.5,tr_00554
T P,1,80,4,4,157,0,2,2,164,164,-94,702.5,tr_00553
T P,1,80,157,4,4,0,2,2,164,164,-88,702.5,tr_00552
T P,1,80,4,4,157,0,2,2,164,164,-82,702.5,tr_00551
T P,1,27,3,157,156,0,2,2,58,58,-68,594,tr_00550
T P,1,57,53,156,3,0,2,2,118,118,-91,609,tr_00549
T P,1,57,3,156,53,0,2,2,118,118,-85,609,tr_00548
T P,1,80,159,4,4,0,2,2,164,164,72,702.5,tr_00547
T P,1,80,4,4,159,0,2,2,164,164,78,702.5,tr_00546
T P,1,80,159,4,4,0,2,2,164,164,84,702.5,tr_00545
T P,1,80,4,4,159,0,2,2,164,164,90,702.5,tr_00544
T P,1,27,3,159,158,0,2,2,58,58,104,594,tr_00543
T P,1,57,66,158,3,0,2,2,118,118,81,609,tr_00542
T P,1,57,3,158,66,0,2,2,118,118,87,609,tr_00541
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T P,1,80,4,4,161,0,2,2,164,164,250,702.5,tr_00539
T P,1,80,161,4,4,0,2,2,164,164,256,702.5,tr_00538
T P,1,80,4,4,161,0,2,2,164,164,262,702.5,tr_00537
T P,1,27,3,161,160,0,2,2,58,58,276,594,tr_00536
T P,1,57,134,160,3,0,2,2,118,118,253,609,tr_00535
T P,1,57,3,160,134,0,2,2,118,118,259,609,tr_00534
T P,1,80,4,164,168,0,2,2,164,164,501,702.5,tr_00533
T P,1,80,168,164,4,0,2,2,164,164,495,702.5,tr_00532
T P,1,80,4,164,168,0,2,2,164,164,489,702.5,tr_00531
T P,1,80,168,164,4,0,2,2,164,164,483,702.5,tr_00530
T P,1,80,4,164,168,0,2,2,164,164,477,702.5,tr_00529
T P,1,80,168,164,4,0,2,2,164,164,471,702.5,tr_00528
T P,1,80,4,164,168,0,2,2,164,164,465,702.5,tr_00527
T P,1,80,168,164,4,0,2,2,164,164,459,702.5,tr_00526
T P,1,80,4,164,168,0,2,2,164,164,453,702.5,tr_00525
T P,1,80,168,164,4,0,2,2,164,164,447,702.5,tr_00524
T P,1,80,4,164,168,0,2,2,164,164,441,702.5,tr_00523
T P,1,80,168,164,4,0,2,2,164,164,435,702.5,tr_00522
T P,1,80,4,164,168,0,2,2,164,164,429,702.5,tr_00521
T P,1,80,168,164,4,0,2,2,164,164,423,702.5,tr_00520
T P,1,80,4,164,168,0,2,2,164,164,417,702.5,tr_00519
T P,1,80,168,164,4,0,2,2,164,164,411,702.5,tr_00518
T P,1,80,4,164,168,0,2,2,164,164,405,702.5,tr_00517
T P,1,80,168,164,4,0,2,2,164,164,399,702.5,tr_00516
T P,1,80,4,164,168,0,2,2,164,164,393,702.5,tr_00515
T P,1,80,168,164,4,0,2,2,164,164,387,702.5,tr_00514
T P,1,80,4,164,168,0,2,2,164,164,381,702.5,tr_00513
T P,1,80,168,164,4,0,2,2,164,164,375,702.5,tr_00512
T P,1,80,4,164,168,0,2,2,164,164,369,702.5,tr_00511
T P,1,80,168,164,4,0,2,2,164,164,363,702.5,tr_00510
T P,1,60,3,162,164,0,2,2,124,124,427,607.5,tr_00509
T P,1,60,164,162,3,0,2,2,124,124,421,607.5,tr_00508
T P,1,60,164,162,3,0,2,2,124,124,409,607.5,tr_00507
T P,1,60,3,163,162,0,2,2,124,124,403,607.5,tr_00506
T P,1,60,3,162,164,0,2,2,124,124,415,607.5,tr_00505
T P,1,60,163,99,3,0,2,2,124,124,391,607.5,tr_00504
T P,1,80,4,165,169,0,2,2,164,164,673,702.5,tr_00503
T P,1,80,169,165,4,0,2,2,164,164,667,702.5,tr_00502
T P,1,80,4,165,169,0,2,2,164,164,661,702.5,tr_00501
T P,1,80,169,165,4,0,2,2,164,164,655,702.5,tr_00500
T P,1,80,4,165,169,0,2,2,164,164,649,702.5,tr_00499
T P,1,80,169,165,4,0,2,2,164,164,643,702.5,tr_00498
T P,1,80,4,165,169,0,2,2,164,164,637,702.5,tr_00497
T P,1,80,169,165,4,0,2,2,164,164,631,702.5,tr_00496
T P,1,80,4,165,169,0,2,2,164,164,625,702.5,tr_00495
T P,1,80,169,165,4,0,2,2,164,164,619,702.5,tr_00494
T P,1,80,4,165,169,0,2,2,164,164,613,702.5,tr_00493
T P,1,80,169,165,4,0,2,2,164,164,607,702.5,tr_00492
T P,1,80,4,165,169,0,2,2,164,164,601,702.5,tr_00491
T P,1,80,169,165,4,0,2,2,164,164,595,702.5,tr_00490
T P,1,80,4,165,169,0,2,2,164,164,589,702.5,tr_00489
T P,1,80,169,165,4,0,2,2,164,164,583,702.5,tr_00488
T P,1,80,4,165,169,0,2,2,164,164,577,702.5,tr_00487
T P,1,80,169,165,4,0,2,2,164,164,571,702.5,tr_00486
T P,1,80,4,165,169,0,2,2,164,164,565,702.5,tr_00485
T P,1,80,169,165,4,0,2,2,164,164,559,702.5,tr_00484
T P,1,80,4,165,169,0,2,2,164,164,553,702.5,tr_00483
T P,1,80,169,165,4,0,2,2,164,164,547,702.5,tr_00482
T P,1,80,4,165,169,0,2,2,164,164,541,702.5,tr_00481
T P,1,80,169,165,4,0,2,2,164,164,535,702.5,tr_00480
T P,1,60,3,166,165,0,2,2,124,124,599,607.5,tr_00479
T P,1,60,165,166,3,0,2,2,124,124,593,607.5,tr_00478
T P,1,60,165,166,3,0,2,2,124,124,581,607.5,tr_00477
T P,1,60,3,167,166,0,2,2,124,124,575,607.5,tr_00476
T P,1,60,3,166,165,0,2,2,124,124,587,607.5,tr_00475
T P,1,60,167,26,3,0,2,2,124,124,563,607.5,tr_00474
T P,1,23,147,79,133,0,2,2,50,50,510,146,tr_00473
T P,1,23,3,134,147,0,2,2,50,50,516,146,tr_00472
T P,1,23,3,134,148,0,2,2,50,50,534,146,tr_00471
T P,1,23,148,79,3,0,2,2,50,50,540,146,tr_00470
T P,1,23,131,133,148,0,2,2,50,50,546,146,tr_00469
T P,1,23,145,131,130,0,2,2,50,50,462,146,tr_00468
T P,1,23,3,95,145,0,2,2,50,50,468,146,tr_00467
T P,1,23,3,95,146,0,2,2,50,50,486,146,tr_00466
T P,1,23,146,131,3,0,2,2,50,50,492,146,tr_00465
T P,1,23,21,130,146,0,2,2,50,50,498,146,tr_00464
T P,1,16,143,122,144,0,2,2,36,36,444,142.5,tr_00463
T P,1,16,129,94,143,0,2,2,36,36,450,142.5,tr_00462
T P,1,12,3,129,95,0,2,2,28,28,432,140.5,tr_00461
T P,1,16,144,59,3,0,2,2,36,36,438,142.5,tr_00460
T P,1,23,141,67,127,0,2,2,50,50,384,146,tr_00459
T P,1,23,3,93,141,0,2,2,50,50,390,146,tr_00458
T P,1,23,3,93,142,0,2,2,50,50,408,146,tr_00457
T P,1,23,142,67,3,0,2,2,50,50,414,146,tr_00456
T P,1,23,13,127,142,0,2,2,50,50,420,146,tr_00455
T P,1,12,3,126,94,0,2,2,28,28,360,140.5,tr_00454
T P,1,6,3,66,126,0,2,2,16,16,372,140.5,tr_00453
T P,1,6,126,93,3,0,2,2,16,16,366,140.5,tr_00452
T P,1,12,3,123,122,0,2,2,28,28,336,140.5,tr_00451
T P,1,6,3,60,123,0,2,2,16,16,348,140.5,tr_00450
T P,1,6,123,93,3,0,2,2,16,16,342,140.5,tr_00449
T P,1,16,139,116,140,0,2,2,36,36,318,142.5,tr_00448
T P,1,16,121,92,139,0,2,2,36,36,324,142.5,tr_00447
T P,1,12,3,121,93,0,2,2,28,28,306,140.5,tr_00446
T P,1,16,140,54,3,0,2,2,36,36,312,142.5,tr_00445
T P,1,12,3,120,92,0,2,2,28,28,246,140.5,tr_00444
T P,1,6,3,53,120,0,2,2,16,16,258,140.5,tr_00443
T P,1,6,120,38,3,0,2,2,16,16,252,140.5,tr_00442
T P,1,12,3,118,116,0,2,2,28,28,222,140.5,tr_00441
T P,1,6,3,49,118,0,2,2,16,16,234,140.5,tr_00440
T P,1,6,118,38,3,0,2,2,16,16,228,140.5,tr_00439
T P,1,12,114,110,3,0,2,2,28,28,186,142.5,tr_00438
T P,1,5,3,111,110,0,2,2,14,14,168,144,tr_00437
T P,1,18,112,7,3,0,2,2,40,40,174,146.5,tr_00436
T P,4,2,113,115,3,0,2,2,8,8,195.5,145,tr_00435
T P,1,5,3,113,115,0,2,2,14,14,204,140,tr_00434
T P,1,23,62,113,3,0,2,2,50,50,210,146,tr_00433
T P,4,2,111,110,3,0,2,2,8,8,159.5,144,tr_00432
T P,1,12,109,13,3,0,2,2,28,28,150,142.5,tr_00431
T P,1,12,3,107,38,0,2,2,28,28,126,140.5,tr_00430
T P,1,6,3,48,107,0,2,2,16,16,138,140.5,tr_00429
T P,1,6,107,105,3,0,2,2,16,16,132,140.5,tr_00428
T P,1,23,137,48,104,0,2,2,50,50,78,146,tr_00427
T P,1,23,3,105,137,0,2,2,50,50,84,146,tr_00426
T P,1,23,3,105,138,0,2,2,50,50,102,146,tr_00425
T P,1,23,138,48,3,0,2,2,50,50,108,146,tr_00424
T P,1,23,99,104,138,0,2,2,50,50,114,146,tr_00423
T P,1,12,101,98,3,0,2,2,28,28,42,142.5,tr_00422
T P,1,5,3,96,98,0,2,2,14,14,24,144,tr_00421
T P,1,18,102,7,3,0,2,2,40,40,30,146.5,tr_00420
T P,4,2,100,103,3,0,2,2,8,8,51.5,145,tr_00419
T P,1,5,3,100,103,0,2,2,14,14,60,140,tr_00418
T P,1,23,44,100,3,0,2,2,50,50,66,146,tr_00417
T P,4,2,96,98,3,0,2,2,8,8,15.5,144,tr_00416
T P,1,12,97,99,3,0,2,2,28,28,6,142.5,tr_00415
T P,1,12,3,25,90,0,2,2,28,28,516,56.5,tr_00414
T P,1,12,90,45,3,0,2,2,28,28,522,56.5,tr_00413
T P,1,12,76,27,90,0,2,2,28,28,528,56.5,tr_00412
T P,1,12,90,78,76,0,2,2,28,28,534,56.5,tr_00411
T P,1,12,79,76,3,0,2,2,28,28,546,56.5,tr_00410
T P,1,12,72,69,3,0,2,2,28,28,480,58.5,tr_00409
T P,1,5,3,70,69,0,2,2,14,14,462,60,tr_00408
T P,1,18,74,7,3,0,2,2,40,40,468,62.5,tr_00407
T P,4,2,73,75,3,0,2,2,8,8,489.5,61,tr_00406
T P,1,5,3,73,75,0,2,2,14,14,498,56,tr_00405
T P,1,23,78,73,3,0,2,2,50,50,504,62,tr_00404
T P,4,2,70,69,3,0,2,2,8,8,453.5,60,tr_00403
T P,1,12,71,21,3,0,2,2,28,28,444,58.5,tr_00402
T P,1,23,88,60,63,0,2,2,50,50,396,62,tr_00401
T P,1,23,3,66,88,0,2,2,50,50,402,62,tr_00400
T P,1,23,3,66,89,0,2,2,50,50,420,62,tr_00399
T P,1,23,89,60,3,0,2,2,50,50,426,62,tr_00398
T P,1,23,67,63,89,0,2,2,50,50,432,62,tr_00397
T P,1,12,3,65,59,0,2,2,28,28,372,56.5,tr_00396
T P,1,6,3,60,65,0,2,2,16,16,384,56.5,tr_00395
T P,1,6,65,66,3,0,2,2,16,16,378,56.5,tr_00394
T P,1,12,3,24,87,0,2,2,28,28,330,56.5,tr_00393
T P,1,12,87,45,3,0,2,2,28,28,336,56.5,tr_00392
T P,1,12,57,27,87,0,2,2,28,28,342,56.5,tr_00391
T P,1,12,87,62,57,0,2,2,28,28,348,56.5,tr_00390
T P,1,12,60,57,3,0,2,2,28,28,360,56.5,tr_00389
T P,1,12,3,27,45,0,2,2,28,28,318,56.5,tr_00388
T P,1,12,3,56,54,0,2,2,28,28,294,56.5,tr_00387
T P,1,6,3,49,56,0,2,2,16,16,306,56.5,tr_00386
T P,1,6,56,53,3,0,2,2,16,16,300,56.5,tr_00385
T P,1,23,85,49,51,0,2,2,50,50,210,62,tr_00384
T P,1,23,3,53,85,0,2,2,50,50,216,62,tr_00383
T P,1,23,3,53,86,0,2,2,50,50,234,62,tr_00382
T P,1,23,86,49,3,0,2,2,50,50,240,62,tr_00381
T P,1,23,39,51,86,0,2,2,50,50,246,62,tr_00380
T P,1,12,3,17,84,0,2,2,28,28,168,56.5,tr_00379
T P,1,12,84,45,3,0,2,2,28,28,174,56.5,tr_00378
T P,1,12,46,27,84,0,2,2,28,28,180,56.5,tr_00377
T P,1,12,84,37,46,0,2,2,28,28,186,56.5,tr_00376
T P,1,12,49,46,3,0,2,2,28,28,198,56.5,tr_00375
T P,1,12,3,9,83,0,2,2,28,28,126,56.5,tr_00374
T P,1,12,83,45,3,0,2,2,28,28,132,56.5,tr_00373
T P,1,12,43,27,83,0,2,2,28,28,138,56.5,tr_00372
T P,1,12,83,44,43,0,2,2,28,28,144,56.5,tr_00371
T P,1,12,48,43,3,0,2,2,28,28,156,56.5,tr_00370
T P,1,23,81,39,36,0,2,2,50,50,78,62,tr_00369
T P,1,23,3,38,81,0,2,2,50,50,84,62,tr_00368
T P,1,23,3,38,82,0,2,2,50,50,102,62,tr_00367
T P,1,23,82,39,3,0,2,2,50,50,108,62,tr_00366
T P,1,23,26,36,82,0,2,2,50,50,114,62,tr_00365
T P,1,12,33,31,3,0,2,2,28,28,42,58.5,tr_00364
T P,1,5,3,29,31,0,2,2,14,14,24,60,tr_00363
T P,1,18,34,7,3,0,2,2,40,40,30,62.5,tr_00362
T P,4,2,32,35,3,0,2,2,8,8,51.5,61,tr_00361
T P,1,5,3,32,35,0,2,2,14,14,60,56,tr_00360
T P,1,23,37,32,3,0,2,2,50,50,66,62,tr_00359
T P,4,2,29,31,3,0,2,2,8,8,15.5,60,tr_00358
T P,1,12,30,26,3,0,2,2,28,28,6,58.5,tr_00357
T N,1,35,1,12,11,0,2,2,74,74,979,-104,tr_00356
T N,1,35,11,12,1,0,2,2,74,74,979,-110,tr_00355
T N,1,35,1,12,11,0,2,2,74,74,979,-116,tr_00354
T N,1,35,11,12,1,0,2,2,74,74,979,-122,tr_00353
T N,1,35,1,12,11,0,2,2,74,74,979,-128,tr_00352
T N,1,35,11,12,1,0,2,2,74,74,979,-134,tr_00351
T N,1,35,1,12,11,0,2,2,74,74,979,-140,tr_00350
T N,1,35,11,12,1,0,2,2,74,74,979,-146,tr_00349
T N,1,35,1,12,11,0,2,2,74,74,979,-152,tr_00348
T N,1,35,11,12,1,0,2,2,74,74,979,-158,tr_00347
T N,1,35,1,12,11,0,2,2,74,74,979,-164,tr_00346
T N,1,35,11,12,1,0,2,2,74,74,979,-170,tr_00345
T N,1,35,1,12,11,0,2,2,74,74,979,-176,tr_00344
T N,1,35,11,12,1,0,2,2,74,74,979,-182,tr_00343
T N,1,35,1,12,11,0,2,2,74,74,979,-188,tr_00342
T N,1,35,11,12,1,0,2,2,74,74,979,-194,tr_00341
T N,1,35,1,12,11,0,2,2,74,74,979,-200,tr_00340
T N,1,35,11,12,1,0,2,2,74,74,979,-206,tr_00339
T N,1,35,1,12,11,0,2,2,74,74,979,-212,tr_00338
T N,1,35,11,12,1,0,2,2,74,74,979,-218,tr_00337
T N,1,35,1,12,11,0,2,2,74,74,979,-224,tr_00336
T N,1,35,11,12,1,0,2,2,74,74,979,-230,tr_00335
T N,1,35,1,12,11,0,2,2,74,74,979,-236,tr_00334
T N,1,35,11,12,1,0,2,2,74,74,979,-242,tr_00333
T N,1,30,2,15,12,0,2,2,64,64,734.5,-178,tr_00332
T N,1,30,12,15,2,0,2,2,64,64,734.5,-184,tr_00331
T N,1,30,2,15,12,0,2,2,64,64,734.5,-190,tr_00330
T N,1,30,12,15,2,0,2,2,64,64,734.5,-196,tr_00329
T N,1,30,2,14,15,0,2,2,64,64,734.5,-202,tr_00328
T N,1,30,14,13,2,0,2,2,64,64,734.5,-214,tr_00327
T N,1,35,1,20,19,0,2,2,74,74,979,68,tr_00326
T N,1,35,19,20,1,0,2,2,74,74,979,62,tr_00325
T N,1,35,1,20,19,0,2,2,74,74,979,56,tr_00324
T N,1,35,19,20,1,0,2,2,74,74,979,50,tr_00323
T N,1,35,1,20,19,0,2,2,74,74,979,44,tr_00322
T N,1,35,19,20,1,0,2,2,74,74,979,38,tr_00321
T N,1,35,1,20,19,0,2,2,74,74,979,32,tr_00320
T N,1,35,19,20,1,0,2,2,74,74,979,26,tr_00319
T N,1,35,1,20,19,0,2,2,74,74,979,20,tr_00318
T N,1,35,19,20,1,0,2,2,74,74,979,14,tr_00317
T N,1,35,1,20,19,0,2,2,74,74,979,8,tr_00316
T N,1,35,19,20,1,0,2,2,74,74,979,2,tr_00315
T N,1,35,1,20,19,0,2,2,74,74,979,-4,tr_00314
T N,1,35,19,20,1,0,2,2,74,74,979,-10,tr_00313
T N,1,35,1,20,19,0,2,2,74,74,979,-16,tr_00312
T N,1,35,19,20,1,0,2,2,74,74,979,-22,tr_00311
T N,1,35,1,20,19,0,2,2,74,74,979,-28,tr_00310
T N,1,35,19,20,1,0,2,2,74,74,979,-34,tr_00309
T N,1,35,1,20,19,0,2,2,74,74,979,-40,tr_00308
T N,1,35,19,20,1,0,2,2,74,74,979,-46,tr_00307
T N,1,35,1,20,19,0,2,2,74,74,979,-52,tr_00306
T N,1,35,19,20,1,0,2,2,74,74,979,-58,tr_00305
T N,1,35,1,20,19,0,2,2,74,74,979,-64,tr_00304
T N,1,35,19,20,1,0,2,2,74,74,979,-70,tr_00303
T N,1,30,2,22,20,0,2,2,64,64,734.5,-6,tr_00302
T N,1,30,20,22,2,0,2,2,64,64,734.5,-12,tr_00301
T N,1,30,2,22,20,0,2,2,64,64,734.5,-18,tr_00300
T N,1,30,20,22,2,0,2,2,64,64,734.5,-24,tr_00299
T N,1,30,2,23,22,0,2,2,64,64,734.5,-30,tr_00298
T N,1,30,23,21,2,0,2,2,64,64,734.5,-42,tr_00297
T N,1,35,136,1,1,0,2,2,74,74,979,155,tr_00296
T N,1,35,1,1,136,0,2,2,74,74,979,161,tr_00295
T N,1,35,136,1,1,0,2,2,74,74,979,167,tr_00294
T N,1,35,1,1,136,0,2,2,74,74,979,173,tr_00293
T N,1,27,2,136,149,0,2,2,58,58,735,199,tr_00292
T N,1,27,149,136,2,0,2,2,58,58,735,193,tr_00291
T N,1,27,2,136,149,0,2,2,58,58,735,187,tr_00290
T N,1,27,2,149,27,0,2,2,58,58,735,170,tr_00289
T N,1,27,27,149,2,0,2,2,58,58,735,164,tr_00288
T N,1,35,1,1,153,0,2,2,74,74,979,345,tr_00287
T N,1,35,153,1,1,0,2,2,74,74,979,339,tr_00286
T N,1,35,1,1,153,0,2,2,74,74,979,333,tr_00285
T N,1,35,153,1,1,0,2,2,74,74,979,327,tr_00284
T N,1,27,2,152,6,0,2,2,58,58,735,312,tr_00283
T N,1,27,6,152,2,0,2,2,58,58,735,318,tr_00282
T N,1,27,2,152,6,0,2,2,58,58,735,324,tr_00281
T N,1,27,2,152,6,0,2,2,58,58,735,288,tr_00280
T N,1,27,6,152,2,0,2,2,58,58,735,294,tr_00279
T N,1,27,6,152,2,0,2,2,58,58,735,282,tr_00278
T N,1,27,2,152,6,0,2,2,58,58,735,300,tr_00277
T N,1,27,6,152,2,0,2,2,58,58,735,306,tr_00276
T N,1,27,2,153,152,0,2,2,58,58,735,341,tr_00275
T N,1,27,152,153,2,0,2,2,58,58,735,347,tr_00274
T N,1,27,2,153,152,0,2,2,58,58,735,353,tr_00273
T N,1,27,152,153,2,0,2,2,58,58,735,359,tr_00272
T N,1,27,152,153,2,0,2,2,58,58,735,371,tr_00271
T N,1,27,2,153,152,0,2,2,58,58,735,365,tr_00270
T N,1,27,2,153,152,0,2,2,58,58,735,389,tr_00269
T N,1,27,2,153,152,0,2,2,58,58,735,377,tr_00268
T N,1,27,152,153,2,0,2,2,58,58,735,383,tr_00267
T N,1,27,152,153,2,0,2,2,58,58,735,407,tr_00266
T N,1,27,152,153,2,0,2,2,58,58,735,395,tr_00265
T N,1,27,2,153,152,0,2,2,58,58,735,401,tr_00264
T N,1,35,8,1,1,0,2,2,74,74,-442,-275,tr_00263
T N,1,35,1,1,8,0,2,2,74,74,-442,-269,tr_00262
T N,1,35,8,1,1,0,2,2,74,74,-442,-263,tr_00261
T N,1,35,1,1,8,0,2,2,74,74,-442,-257,tr_00260
T N,1,27,2,8,10,0,2,2,58,58,-198,-231,tr_00259
T N,1,27,10,8,2,0,2,2,58,58,-198,-237,tr_00258
T N,1,27,2,8,10,0,2,2,58,58,-198,-243,tr_00257
T N,1,27,2,10,9,0,2,2,58,58,-198,-260,tr_00256
T N,1,27,9,10,2,0,2,2,58,58,-198,-266,tr_00255
T N,1,35,16,1,1,0,2,2,74,74,-442,-103,tr_00254
T N,1,35,1,1,16,0,2,2,74,74,-442,-97,tr_00253
T N,1,35,16,1,1,0,2,2,74,74,-442,-91,tr_00252
T N,1,35,1,1,16,0,2,2,74,74,-442,-85,tr_00251
T N,1,27,2,16,18,0,2,2,58,58,-198,-59,tr_00250
T N,1,27,18,16,2,0,2,2,58,58,-198,-65,tr_00249
T N,1,27,2,16,18,0,2,2,58,58,-198,-71,tr_00248
T N,1,27,2,18,17,0,2,2,58,58,-198,-88,tr_00247
T N,1,27,17,18,2,0,2,2,58,58,-198,-94,tr_00246
T N,1,35,28,1,1,0,2,2,74,74,-442,69,tr_00245
T N,1,35,1,1,28,0,2,2,74,74,-442,75,tr_00244
T N,1,35,28,1,1,0,2,2,74,74,-442,81,tr_00243
T N,1,35,1,1,28,0,2,2,74,74,-442,87,tr_00242
T N,1,27,2,28,91,0,2,2,58,58,-198,113,tr_00241
T N,1,27,91,28,2,0,2,2,58,58,-198,107,tr_00240
T N,1,27,2,28,91,0,2,2,58,58,-198,101,tr_00239
T N,1,27,2,91,24,0,2,2,58,58,-198,84,tr_00238
T N,1,27,24,91,2,0,2,2,58,58,-198,78,tr_00237
T N,1,35,150,1,1,0,2,2,74,74,-442,241,tr_00236
T N,1,35,1,1,150,0,2,2,74,74,-442,247,tr_00235
T N,1,35,150,1,1,0,2,2,74,74,-442,253,tr_00234
T N,1,35,1,1,150,0,2,2,74,74,-442,259,tr_00233
T N,1,27,2,150,151,0,2,2,58,58,-198,285,tr_00232
T N,1,27,151,150,2,0,2,2,58,58,-198,279,tr_00231
T N,1,27,2,150,151,0,2,2,58,58,-198,273,tr_00230
T N,1,27,2,151,25,0,2,2,58,58,-198,256,tr_00229
T N,1,27,25,151,2,0,2,2,58,58,-198,250,tr_00228
T N,1,35,154,1,1,0,2,2,74,74,-442,413,tr_00227
T N,1,35,1,1,154,0,2,2,74,74,-442,419,tr_00226
T N,1,35,154,1,1,0,2,2,74,74,-442,425,tr_00225
T N,1,35,1,1,154,0,2,2,74,74,-442,431,tr_00224
T N,1,27,2,154,155,0,2,2,58,58,-198,457,tr_00223
T N,1,27,155,154,2,0,2,2,58,58,-198,451,tr_00222
T N,1,27,2,154,155,0,2,2,58,58,-198,445,tr_00221
T N,1,27,2,155,105,0,2,2,58,58,-198,428,tr_00220
T N,1,27,105,155,2,0,2,2,58,58,-198,422,tr_00219
T N,1,20,2,5,7,0,2,2,44,44,604,-387.5,tr_00218
T N,1,20,7,5,2,0,2,2,44,44,598,-387.5,tr_00217
T N,1,20,5,6,2,0,2,2,44,44,586,-387.5,tr_00216
T N,1,20,7,5,2,0,2,2,44,44,622,-387.5,tr_00215
T N,1,20,2,5,7,0,2,2,44,44,616,-387.5,tr_00214
T N,1,20,7,5,2,0,2,2,44,44,610,-387.5,tr_00213
T N,1,35,157,1,1,0,2,2,74,74,-100,787,tr_00212
T N,1,35,1,1,157,0,2,2,74,74,-94,787,tr_00211
T N,1,35,157,1,1,0,2,2,74,74,-88,787,tr_00210
T N,1,35,1,1,157,0,2,2,74,74,-82,787,tr_00209
T N,1,27,2,157,156,0,2,2,58,58,-56,543,tr_00208
T N,1,27,156,157,2,0,2,2,58,58,-62,543,tr_00207
T N,1,27,2,157,156,0,2,2,58,58,-68,543,tr_00206
T N,1,27,2,156,53,0,2,2,58,58,-85,543,tr_00205
T N,1,27,53,156,2,0,2,2,58,58,-91,543,tr_00204
T N,1,35,159,1,1,0,2,2,74,74,72,787,tr_00203
T N,1,35,1,1,159,0,2,2,74,74,78,787,tr_00202
T N,1,35,159,1,1,0,2,2,74,74,84,787,tr_00201
T N,1,35,1,1,159,0,2,2,74,74,90,787,tr_00200
T N,1,27,2,159,158,0,2,2,58,58,116,543,tr_00199
T N,1,27,158,159,2,0,2,2,58,58,110,543,tr_00198
T N,1,27,2,159,158,0,2,2,58,58,104,543,tr_00197
T N,1,27,2,158,66,0,2,2,58,58,87,543,tr_00196
T N,1,27,66,158,2,0,2,2,58,58,81,543,tr_00195
T N,1,35,161,1,1,0,2,2,74,74,244,787,tr_00194
T N,1,35,1,1,161,0,2,2,74,74,250,787,tr_00193
T N,1,35,161,1,1,0,2,2,74,74,256,787,tr_00192
T N,1,35,1,1,161,0,2,2,74,74,262,787,tr_00191
T N,1,27,2,161,160,0,2,2,58,58,288,543,tr_00190
T N,1,27,160,161,2,0,2,2,58,58,282,543,tr_00189
T N,1,27,2,161,160,0,2,2,58,58,276,543,tr_00188
T N,1,27,2,160,134,0,2,2,58,58,259,543,tr_00187
T N,1,27,134,160,2,0,2,2,58,58,253,543,tr_00186
T N,1,35,1,164,168,0,2,2,74,74,501,787,tr_00185
T N,1,35,168,164,1,0,2,2,74,74,495,787,tr_00184
T N,1,35,1,164,168,0,2,2,74,74,489,787,tr_00183
T N,1,35,168,164,1,0,2,2,74,74,483,787,tr_00182
T N,1,35,1,164,168,0,2,2,74,74,477,787,tr_00181
T N,1,35,168,164,1,0,2,2,74,74,471,787,tr_00180
T N,1,35,1,164,168,0,2,2,74,74,465,787,tr_00179
T N,1,35,168,164,1,0,2,2,74,74,459,787,tr_00178
T N,1,35,1,164,168,0,2,2,74,74,453,787,tr_00177
T N,1,35,168,164,1,0,2,2,74,74,447,787,tr_00176
T N,1,35,1,164,168,0,2,2,74,74,441,787,tr_00175
T N,1,35,168,164,1,0,2,2,74,74,435,787,tr_00174
T N,1,35,1,164,168,0,2,2,74,74,429,787,tr_00173
T N,1,35,168,164,1,0,2,2,74,74,423,787,tr_00172
T N,1,35,1,164,168,0,2,2,74,74,417,787,tr_00171
T N,1,35,168,164,1,0,2,2,74,74,411,787,tr_00170
T N,1,35,1,164,168,0,2,2,74,74,405,787,tr_00169
T N,1,35,168,164,1,0,2,2,74,74,399,787,tr_00168
T N,1,35,1,164,168,0,2,2,74,74,393,787,tr_00167
T N,1,35,168,164,1,0,2,2,74,74,387,787,tr_00166
T N,1,35,1,164,168,0,2,2,74,74,381,787,tr_00165
T N,1,35,168,164,1,0,2,2,74,74,375,787,tr_00164
T N,1,35,1,164,168,0,2,2,74,74,369,787,tr_00163
T N,1,35,168,164,1,0,2,2,74,74,363,787,tr_00162
T N,1,30,2,162,164,0,2,2,64,64,427,542.5,tr_00161
T N,1,30,164,162,2,0,2,2,64,64,421,542.5,tr_00160
T N,1,30,2,162,164,0,2,2,64,64,415,542.5,tr_00159
T N,1,30,164,162,2,0,2,2,64,64,409,542.5,tr_00158
T N,1,30,2,163,162,0,2,2,64,64,403,542.5,tr_00157
T N,1,30,163,99,2,0,2,2,64,64,391,542.5,tr_00156
T N,1,35,1,165,169,0,2,2,74,74,673,787,tr_00155
T N,1,35,169,165,1,0,2,2,74,74,667,787,tr_00154
T N,1,35,1,165,169,0,2,2,74,74,661,787,tr_00153
T N,1,35,169,165,1,0,2,2,74,74,655,787,tr_00152
T N,1,35,1,165,169,0,2,2,74,74,649,787,tr_00151
T N,1,35,169,165,1,0,2,2,74,74,643,787,tr_00150
T N,1,35,1,165,169,0,2,2,74,74,637,787,tr_00149
T N,1,35,169,165,1,0,2,2,74,74,631,787,tr_00148
T N,1,35,1,165,169,0,2,2,74,74,625,787,tr_00147
T N,1,35,169,165,1,0,2,2,74,74,619,787,tr_00146
T N,1,35,1,165,169,0,2,2,74,74,613,787,tr_00145
T N,1,35,169,165,1,0,2,2,74,74,607,787,tr_00144
T N,1,35,1,165,169,0,2,2,74,74,601,787,tr_00143
T N,1,35,169,165,1,0,2,2,74,74,595,787,tr_00142
T N,1,35,1,165,169,0,2,2,74,74,589,787,tr_00141
T N,1,35,169,165,1,0,2,2,74,74,583,787,tr_00140
T N,1,35,1,165,169,0,2,2,74,74,577,787,tr_00139
T N,1,35,169,165,1,0,2,2,74,74,571,787,tr_00138
T N,1,35,1,165,169,0,2,2,74,74,565,787,tr_00137
T N,1,35,169,165,1,0,2,2,74,74,559,787,tr_00136
T N,1,35,1,165,169,0,2,2,74,74,553,787,tr_00135
T N,1,35,169,165,1,0,2,2,74,74,547,787,tr_00134
T N,1,35,1,165,169,0,2,2,74,74,541,787,tr_00133
T N,1,35,169,165,1,0,2,2,74,74,535,787,tr_00132
T N,1,30,2,166,165,0,2,2,64,64,599,542.5,tr_00131
T N,1,30,165,166,2,0,2,2,64,64,593,542.5,tr_00130
T N,1,30,2,166,165,0,2,2,64,64,587,542.5,tr_00129
T N,1,30,165,166,2,0,2,2,64,64,581,542.5,tr_00128
T N,1,30,2,167,166,0,2,2,64,64,575,542.5,tr_00127
T N,1,30,167,26,2,0,2,2,64,64,563,542.5,tr_00126
T N,1,6,133,79,2,0,2,2,16,16,510,123.5,tr_00125
T N,1,6,2,134,133,0,2,2,16,16,516,123.5,tr_00124
T N,1,12,135,134,2,0,2,2,28,28,534,120.5,tr_00123
T N,1,12,131,79,135,0,2,2,28,28,540,120.5,tr_00122
T N,1,6,2,133,131,0,2,2,16,16,546,123.5,tr_00121
T N,1,6,130,131,2,0,2,2,16,16,462,123.5,tr_00120
T N,1,6,2,95,130,0,2,2,16,16,468,123.5,tr_00119
T N,1,12,132,95,2,0,2,2,28,28,486,120.5,tr_00118
T N,1,12,21,131,132,0,2,2,28,28,492,120.5,tr_00117
T N,1,6,2,130,21,0,2,2,16,16,498,123.5,tr_00116
T N,1,6,2,129,95,0,2,2,16,16,432,122.5,tr_00115
T N,1,4,129,94,2,0,2,2,12,12,450,121.5,tr_00114
T N,1,4,2,122,129,0,2,2,12,12,444,121.5,tr_00113
T N,1,4,129,59,2,0,2,2,12,12,438,121.5,tr_00112
T N,1,6,127,67,2,0,2,2,16,16,384,123.5,tr_00111
T N,1,6,2,93,127,0,2,2,16,16,390,123.5,tr_00110
T N,1,12,128,93,2,0,2,2,28,28,408,120.5,tr_00109
T N,1,12,13,67,128,0,2,2,28,28,414,120.5,tr_00108
T N,1,6,2,127,13,0,2,2,16,16,420,123.5,tr_00107
T N,1,6,2,126,94,0,2,2,16,16,360,122.5,tr_00106
T N,1,6,126,66,124,0,2,2,16,16,372,122.5,tr_00105
T N,1,6,124,93,2,0,2,2,16,16,366,122.5,tr_00104
T N,1,6,2,123,122,0,2,2,16,16,336,122.5,tr_00103
T N,1,6,123,60,125,0,2,2,16,16,348,122.5,tr_00102
T N,1,6,125,93,2,0,2,2,16,16,342,122.5,tr_00101
T N,1,6,2,121,93,0,2,2,16,16,306,122.5,tr_00100
T N,1,4,121,92,2,0,2,2,12,12,324,121.5,tr_00099
T N,1,4,2,116,121,0,2,2,12,12,318,121.5,tr_00098
T N,1,4,121,54,2,0,2,2,12,12,312,121.5,tr_00097
T N,1,6,2,120,92,0,2,2,16,16,246,122.5,tr_00096
T N,1,6,120,53,119,0,2,2,16,16,258,122.5,tr_00095
T N,1,6,119,38,2,0,2,2,16,16,252,122.5,tr_00094
T N,1,6,2,118,116,0,2,2,16,16,222,122.5,tr_00093
T N,1,6,118,49,117,0,2,2,16,16,234,122.5,tr_00092
T N,1,6,117,38,2,0,2,2,16,16,228,122.5,tr_00091
T N,7,3,2,110,111,0,2,2,10,10,165,113,tr_00090
T N,1,6,114,110,2,0,2,2,16,16,186,119.5,tr_00089
T N,1,6,113,112,114,0,2,2,16,16,192,119.5,tr_00088
T N,7,3,2,115,113,0,2,2,10,10,201,114,tr_00087
T N,1,5,2,111,110,0,2,2,14,14,168,122,tr_00086
T N,1,6,111,7,109,0,2,2,16,16,156,119.5,tr_00085
T N,1,9,112,7,2,0,2,2,22,22,174,120,tr_00084
T N,1,5,2,113,115,0,2,2,14,14,204,123,tr_00083
T N,1,12,62,113,2,0,2,2,28,28,210,120.5,tr_00082
T N,1,6,109,13,2,0,2,2,16,16,150,119.5,tr_00081
T N,1,6,2,107,38,0,2,2,16,16,126,122.5,tr_00080
T N,1,6,107,48,108,0,2,2,16,16,138,122.5,tr_00079
T N,1,6,108,105,2,0,2,2,16,16,132,122.5,tr_00078
T N,1,6,104,48,2,0,2,2,16,16,78,123.5,tr_00077
T N,1,6,2,105,104,0,2,2,16,16,84,123.5,tr_00076
T N,1,12,106,105,2,0,2,2,28,28,102,120.5,tr_00075
T N,1,12,99,48,106,0,2,2,28,28,108,120.5,tr_00074
T N,1,6,2,104,99,0,2,2,16,16,114,123.5,tr_00073
T N,7,3,2,98,96,0,2,2,10,10,21,113,tr_00072
T N,1,6,101,98,2,0,2,2,16,16,42,119.5,tr_00071
T N,1,6,100,102,101,0,2,2,16,16,48,119.5,tr_00070
T N,7,3,2,103,100,0,2,2,10,10,57,114,tr_00069
T N,1,5,2,96,98,0,2,2,14,14,24,122,tr_00068
T N,1,6,96,7,97,0,2,2,16,16,12,119.5,tr_00067
T N,1,9,102,7,2,0,2,2,22,22,30,120,tr_00066
T N,1,5,2,100,103,0,2,2,14,14,60,123,tr_00065
T N,1,12,44,100,2,0,2,2,28,28,66,120.5,tr_00064
T N,1,6,97,99,2,0,2,2,16,16,6,119.5,tr_00063
T N,1,6,77,25,2,0,2,2,16,16,516,39.5,tr_00062
T N,1,6,76,45,77,0,2,2,16,16,522,39.5,tr_00061
T N,1,6,80,27,76,0,2,2,16,16,528,39.5,tr_00060
T N,1,6,2,78,80,0,2,2,16,16,534,39.5,tr_00059
T N,1,6,79,76,2,0,2,2,16,16,546,39.5,tr_00058
T N,7,3,2,69,70,0,2,2,10,10,459,29,tr_00057
T N,1,6,72,69,2,0,2,2,16,16,480,35.5,tr_00056
T N,1,6,73,74,72,0,2,2,16,16,486,35.5,tr_00055
T N,7,3,2,75,73,0,2,2,10,10,495,30,tr_00054
T N,1,5,2,70,69,0,2,2,14,14,462,38,tr_00053
T N,1,6,70,7,71,0,2,2,16,16,450,35.5,tr_00052
T N,1,9,74,7,2,0,2,2,22,22,468,36,tr_00051
T N,1,5,2,73,75,0,2,2,14,14,498,39,tr_00050
T N,1,12,78,73,2,0,2,2,28,28,504,36.5,tr_00049
T N,1,6,71,21,2,0,2,2,16,16,444,35.5,tr_00048
T N,1,6,63,60,2,0,2,2,16,16,396,39.5,tr_00047
T N,1,6,2,66,63,0,2,2,16,16,402,39.5,tr_00046
T N,1,12,68,66,2,0,2,2,28,28,420,36.5,tr_00045
T N,1,12,67,60,68,0,2,2,28,28,426,36.5,tr_00044
T N,1,6,2,63,67,0,2,2,16,16,432,39.5,tr_00043
T N,1,6,2,65,59,0,2,2,16,16,372,38.5,tr_00042
T N,1,6,65,60,64,0,2,2,16,16,384,38.5,tr_00041
T N,1,6,64,66,2,0,2,2,16,16,378,38.5,tr_00040
T N,1,6,58,24,2,0,2,2,16,16,330,39.5,tr_00039
T N,1,6,57,45,58,0,2,2,16,16,336,39.5,tr_00038
T N,1,6,61,27,57,0,2,2,16,16,342,39.5,tr_00037
T N,1,6,2,62,61,0,2,2,16,16,348,39.5,tr_00036
T N,1,6,60,57,2,0,2,2,16,16,360,39.5,tr_00035
T N,1,6,2,27,45,0,2,2,16,16,318,39.5,tr_00034
T N,1,6,2,56,54,0,2,2,16,16,294,38.5,tr_00033
T N,1,6,56,49,55,0,2,2,16,16,306,38.5,tr_00032
T N,1,6,55,53,2,0,2,2,16,16,300,38.5,tr_00031
T N,1,6,51,49,2,0,2,2,16,16,210,39.5,tr_00030
T N,1,6,2,53,51,0,2,2,16,16,216,39.5,tr_00029
T N,1,12,52,53,2,0,2,2,28,28,234,36.5,tr_00028
T N,1,12,39,49,52,0,2,2,28,28,240,36.5,tr_00027
T N,1,6,2,51,39,0,2,2,16,16,246,39.5,tr_00026
T N,1,6,47,17,2,0,2,2,16,16,168,39.5,tr_00025
T N,1,6,46,45,47,0,2,2,16,16,174,39.5,tr_00024
T N,1,6,50,27,46,0,2,2,16,16,180,39.5,tr_00023
T N,1,6,2,37,50,0,2,2,16,16,186,39.5,tr_00022
T N,1,6,49,46,2,0,2,2,16,16,198,39.5,tr_00021
T N,1,6,41,9,2,0,2,2,16,16,126,39.5,tr_00020
T N,1,6,43,45,41,0,2,2,16,16,132,39.5,tr_00019
T N,1,6,42,27,43,0,2,2,16,16,138,39.5,tr_00018
T N,1,6,2,44,42,0,2,2,16,16,144,39.5,tr_00017
T N,1,6,48,43,2,0,2,2,16,16,156,39.5,tr_00016
T N,1,6,36,39,2,0,2,2,16,16,78,39.5,tr_00015
T N,1,6,2,38,36,0,2,2,16,16,84,39.5,tr_00014
T N,1,12,40,38,2,0,2,2,28,28,102,36.5,tr_00013
T N,1,12,26,39,40,0,2,2,28,28,108,36.5,tr_00012
T N,1,6,2,36,26,0,2,2,16,16,114,39.5,tr_00011
T N,7,3,2,31,29,0,2,2,10,10,21,29,tr_00010
T N,1,6,33,31,2,0,2,2,16,16,42,35.5,tr_00009
T N,1,6,32,34,33,0,2,2,16,16,48,35.5,tr_00008
T N,7,3,2,35,32,0,2,2,10,10,57,30,tr_00007
T N,1,5,2,29,31,0,2,2,14,14,24,38,tr_00006
T N,1,6,29,7,30,0,2,2,16,16,12,35.5,tr_00005
T N,1,9,34,7,2,0,2,2,22,22,30,36,tr_00004
T N,1,5,2,32,35,0,2,2,14,14,60,39,tr_00003
T N,1,12,37,32,2,0,2,2,28,28,66,36.5,tr_00002
T N,1,6,30,26,2,0,2,2,16,16,6,35.5,tr_00001
S 169,EXTERNAL,s 1
S 168,EXTERNAL,s 0
S 167,INTERNAL
S 166,INTERNAL
S 165,INTERNAL
S 164,INTERNAL
S 163,INTERNAL
S 162,INTERNAL
S 161,EXTERNAL,b 3
S 160,INTERNAL
S 159,EXTERNAL,b 2
S 158,INTERNAL
S 157,EXTERNAL,b 1
S 156,INTERNAL
S 155,INTERNAL
S 154,EXTERNAL,b 0
S 153,EXTERNAL,ck
S 152,INTERNAL
S 151,INTERNAL
S 150,EXTERNAL,a 3
S 149,INTERNAL
S 148,INTERNAL
S 147,INTERNAL
S 146,INTERNAL
S 145,INTERNAL
S 144,INTERNAL
S 143,INTERNAL
S 142,INTERNAL
S 141,INTERNAL
S 140,INTERNAL
S 139,INTERNAL
S 138,INTERNAL
S 137,INTERNAL
S 136,EXTERNAL,sel
S 135,INTERNAL
S 134,INTERNAL,bb_3
S 133,INTERNAL
S 132,INTERNAL
S 131,INTERNAL,core.int_9
S 130,INTERNAL
S 129,INTERNAL
S 128,INTERNAL
S 127,INTERNAL
S 126,INTERNAL
S 125,INTERNAL
S 124,INTERNAL
S 123,INTERNAL
S 122,INTERNAL,core.int_7
S 121,INTERNAL
S 120,INTERNAL
S 119,INTERNAL
S 118,INTERNAL
S 117,INTERNAL
S 116,INTERNAL,core.int_3
S 115,INTERNAL
S 114,INTERNAL
S 113,INTERNAL,core.l2.dff_s
S 112,INTERNAL
S 111,INTERNAL,core.l2.dff_m
S 110,INTERNAL
S 109,INTERNAL
S 108,INTERNAL
S 107,INTERNAL
S 106,INTERNAL
S 105,INTERNAL,bb_0
S 104,INTERNAL
S 103,INTERNAL
S 102,INTERNAL
S 101,INTERNAL
S 100,INTERNAL,core.l0.dff_s
S 99,INTERNAL,ss_0
S 98,INTERNAL
S 97,INTERNAL
S 96,INTERNAL,core.l0.dff_m
S 95,INTERNAL,core.carry_2
S 94,INTERNAL,core.int_8
S 93,INTERNAL,core.carry_1
S 92,INTERNAL,core.int_4
S 91,INTERNAL
S 90,INTERNAL
S 89,INTERNAL
S 88,INTERNAL
S 87,INTERNAL
S 86,INTERNAL
S 85,INTERNAL
S 84,INTERNAL
S 83,INTERNAL
S 82,INTERNAL
S 81,INTERNAL
S 80,INTERNAL
S 79,INTERNAL,core.mux_3
S 78,INTERNAL,core.regout_3
S 77,INTERNAL
S 76,INTERNAL
S 75,INTERNAL
S 74,INTERNAL
S 73,INTERNAL,core.l3.dff_s
S 72,INTERNAL
S 71,INTERNAL
S 70,INTERNAL,core.l3.dff_m
S 69,INTERNAL
S 68,INTERNAL
S 67,INTERNAL,core.int_5
S 66,INTERNAL,bb_2
S 65,INTERNAL
S 64,INTERNAL
S 63,INTERNAL
S 62,INTERNAL,core.regout_2
S 61,INTERNAL
S 60,INTERNAL,core.mux_2
S 59,INTERNAL,core.int_6
S 58,INTERNAL
S 57,INTERNAL
S 56,INTERNAL
S 55,INTERNAL
S 54,INTERNAL,core.int_2
S 53,INTERNAL,bb_1
S 52,INTERNAL
S 51,INTERNAL
S 50,INTERNAL
S 49,INTERNAL,core.mux_1
S 48,INTERNAL,core.mux_0
S 47,INTERNAL
S 46,INTERNAL
S 45,INTERNAL,core.nsel
S 44,INTERNAL,core.regout_0
S 43,INTERNAL
S 42,INTERNAL
S 41,INTERNAL
S 40,INTERNAL
S 39,INTERNAL,core.int_1
S 38,INTERNAL,core.carry_0
S 37,INTERNAL,core.regout_1
S 36,INTERNAL
S 35,INTERNAL
S 34,INTERNAL
S 33,INTERNAL
S 32,INTERNAL,core.l1.dff_s
S 31,INTERNAL
S 30,INTERNAL
S 29,INTERNAL,core.l1.dff_m
S 28,EXTERNAL,a 2
S 27,INTERNAL,selsel
S 26,INTERNAL,ss_1
S 25,INTERNAL,aa_3
S 24,INTERNAL,aa_2
S 23,INTERNAL
S 22,INTERNAL
S 21,INTERNAL,ss_3
S 20,INTERNAL
S 19,EXTERNAL,s 3
S 18,INTERNAL
S 17,INTERNAL,aa_1
S 16,EXTERNAL,a 1
S 15,INTERNAL
S 14,INTERNAL
S 13,INTERNAL,ss_2
S 12,INTERNAL
S 11,EXTERNAL,s 2
S 10,INTERNAL
S 9,INTERNAL,aa_0
S 8,EXTERNAL,a 0
S 7,INTERNAL,clock
S 6,INTERNAL,p17.logic.ck
S 5,INTERNAL
S 4,EXTERNAL,vdde
S 3,EXTERNAL,vdd
S 2,EXTERNAL,vss
S 1,EXTERNAL,vsse
EOF

166
alliance/share/tutorials/addaccu/addaccue.rep
View File

@ -1,166 +0,0 @@
YAGLE V2.05 addaccue.rep Sun Sep 27 12:26:21 1998
[WAR 04] Transistor N (X=2620,Y=7870) is always off
[WAR 04] Transistor N (X=2560,Y=7870) is always off
[WAR 04] Transistor N (X=2500,Y=7870) is always off
[WAR 04] Transistor N (X=2440,Y=7870) is always off
[WAR 04] Transistor N (X=900,Y=7870) is always off
[WAR 04] Transistor N (X=840,Y=7870) is always off
[WAR 04] Transistor N (X=780,Y=7870) is always off
[WAR 04] Transistor N (X=720,Y=7870) is always off
[WAR 04] Transistor N (X=-820,Y=7870) is always off
[WAR 04] Transistor N (X=-880,Y=7870) is always off
[WAR 04] Transistor N (X=-940,Y=7870) is always off
[WAR 04] Transistor N (X=-1000,Y=7870) is always off
[WAR 04] Transistor N (X=-4420,Y=4310) is always off
[WAR 04] Transistor N (X=-4420,Y=4250) is always off
[WAR 04] Transistor N (X=-4420,Y=4190) is always off
[WAR 04] Transistor N (X=-4420,Y=4130) is always off
[WAR 04] Transistor N (X=-4420,Y=2590) is always off
[WAR 04] Transistor N (X=-4420,Y=2530) is always off
[WAR 04] Transistor N (X=-4420,Y=2470) is always off
[WAR 04] Transistor N (X=-4420,Y=2410) is always off
[WAR 04] Transistor N (X=-4420,Y=870) is always off
[WAR 04] Transistor N (X=-4420,Y=810) is always off
[WAR 04] Transistor N (X=-4420,Y=750) is always off
[WAR 04] Transistor N (X=-4420,Y=690) is always off
[WAR 04] Transistor N (X=-4420,Y=-850) is always off
[WAR 04] Transistor N (X=-4420,Y=-910) is always off
[WAR 04] Transistor N (X=-4420,Y=-970) is always off
[WAR 04] Transistor N (X=-4420,Y=-1030) is always off
[WAR 04] Transistor N (X=-4420,Y=-2570) is always off
[WAR 04] Transistor N (X=-4420,Y=-2630) is always off
[WAR 04] Transistor N (X=-4420,Y=-2690) is always off
[WAR 04] Transistor N (X=-4420,Y=-2750) is always off
[WAR 04] Transistor N (X=9790,Y=3270) is always off
[WAR 04] Transistor N (X=9790,Y=3330) is always off
[WAR 04] Transistor N (X=9790,Y=3390) is always off
[WAR 04] Transistor N (X=9790,Y=3450) is always off
[WAR 04] Transistor N (X=9790,Y=1730) is always off
[WAR 04] Transistor N (X=9790,Y=1670) is always off
[WAR 04] Transistor N (X=9790,Y=1610) is always off
[WAR 04] Transistor N (X=9790,Y=1550) is always off
[WAR 04] Transistor P (X=2620,Y=7025) is always off
[WAR 04] Transistor P (X=2560,Y=7025) is always off
[WAR 04] Transistor P (X=2500,Y=7025) is always off
[WAR 04] Transistor P (X=2440,Y=7025) is always off
[WAR 04] Transistor P (X=900,Y=7025) is always off
[WAR 04] Transistor P (X=840,Y=7025) is always off
[WAR 04] Transistor P (X=780,Y=7025) is always off
[WAR 04] Transistor P (X=720,Y=7025) is always off
[WAR 04] Transistor P (X=-820,Y=7025) is always off
[WAR 04] Transistor P (X=-880,Y=7025) is always off
[WAR 04] Transistor P (X=-940,Y=7025) is always off
[WAR 04] Transistor P (X=-1000,Y=7025) is always off
[WAR 04] Transistor P (X=-3575,Y=4310) is always off
[WAR 04] Transistor P (X=-3575,Y=4250) is always off
[WAR 04] Transistor P (X=-3575,Y=4190) is always off
[WAR 04] Transistor P (X=-3575,Y=4130) is always off
[WAR 04] Transistor P (X=-3575,Y=2590) is always off
[WAR 04] Transistor P (X=-3575,Y=2530) is always off
[WAR 04] Transistor P (X=-3575,Y=2470) is always off
[WAR 04] Transistor P (X=-3575,Y=2410) is always off
[WAR 04] Transistor P (X=-3575,Y=870) is always off
[WAR 04] Transistor P (X=-3575,Y=810) is always off
[WAR 04] Transistor P (X=-3575,Y=750) is always off
[WAR 04] Transistor P (X=-3575,Y=690) is always off
[WAR 04] Transistor P (X=-3575,Y=-850) is always off
[WAR 04] Transistor P (X=-3575,Y=-910) is always off
[WAR 04] Transistor P (X=-3575,Y=-970) is always off
[WAR 04] Transistor P (X=-3575,Y=-1030) is always off
[WAR 04] Transistor P (X=-3575,Y=-2570) is always off
[WAR 04] Transistor P (X=-3575,Y=-2630) is always off
[WAR 04] Transistor P (X=-3575,Y=-2690) is always off
[WAR 04] Transistor P (X=-3575,Y=-2750) is always off
[WAR 04] Transistor P (X=8945,Y=3270) is always off
[WAR 04] Transistor P (X=8945,Y=3330) is always off
[WAR 04] Transistor P (X=8945,Y=3390) is always off
[WAR 04] Transistor P (X=8945,Y=3450) is always off
[WAR 04] Transistor P (X=8945,Y=1730) is always off
[WAR 04] Transistor P (X=8945,Y=1670) is always off
[WAR 04] Transistor P (X=8945,Y=1610) is always off
[WAR 04] Transistor P (X=8945,Y=1550) is always off
[WAR 07] Transistor N (X=2620,Y=7870) tr_00191 is not used
[WAR 07] Transistor N (X=2560,Y=7870) tr_00192 is not used
[WAR 07] Transistor N (X=2500,Y=7870) tr_00193 is not used
[WAR 07] Transistor N (X=2440,Y=7870) tr_00194 is not used
[WAR 07] Transistor N (X=900,Y=7870) tr_00200 is not used
[WAR 07] Transistor N (X=840,Y=7870) tr_00201 is not used
[WAR 07] Transistor N (X=780,Y=7870) tr_00202 is not used
[WAR 07] Transistor N (X=720,Y=7870) tr_00203 is not used
[WAR 07] Transistor N (X=-820,Y=7870) tr_00209 is not used
[WAR 07] Transistor N (X=-880,Y=7870) tr_00210 is not used
[WAR 07] Transistor N (X=-940,Y=7870) tr_00211 is not used
[WAR 07] Transistor N (X=-1000,Y=7870) tr_00212 is not used
[WAR 07] Transistor N (X=-4420,Y=4310) tr_00224 is not used
[WAR 07] Transistor N (X=-4420,Y=4250) tr_00225 is not used
[WAR 07] Transistor N (X=-4420,Y=4190) tr_00226 is not used
[WAR 07] Transistor N (X=-4420,Y=4130) tr_00227 is not used
[WAR 07] Transistor N (X=-4420,Y=2590) tr_00233 is not used
[WAR 07] Transistor N (X=-4420,Y=2530) tr_00234 is not used
[WAR 07] Transistor N (X=-4420,Y=2470) tr_00235 is not used
[WAR 07] Transistor N (X=-4420,Y=2410) tr_00236 is not used
[WAR 07] Transistor N (X=-4420,Y=870) tr_00242 is not used
[WAR 07] Transistor N (X=-4420,Y=810) tr_00243 is not used
[WAR 07] Transistor N (X=-4420,Y=750) tr_00244 is not used
[WAR 07] Transistor N (X=-4420,Y=690) tr_00245 is not used
[WAR 07] Transistor N (X=-4420,Y=-850) tr_00251 is not used
[WAR 07] Transistor N (X=-4420,Y=-910) tr_00252 is not used
[WAR 07] Transistor N (X=-4420,Y=-970) tr_00253 is not used
[WAR 07] Transistor N (X=-4420,Y=-1030) tr_00254 is not used
[WAR 07] Transistor N (X=-4420,Y=-2570) tr_00260 is not used
[WAR 07] Transistor N (X=-4420,Y=-2630) tr_00261 is not used
[WAR 07] Transistor N (X=-4420,Y=-2690) tr_00262 is not used
[WAR 07] Transistor N (X=-4420,Y=-2750) tr_00263 is not used
[WAR 07] Transistor N (X=9790,Y=3270) tr_00284 is not used
[WAR 07] Transistor N (X=9790,Y=3330) tr_00285 is not used
[WAR 07] Transistor N (X=9790,Y=3390) tr_00286 is not used
[WAR 07] Transistor N (X=9790,Y=3450) tr_00287 is not used
[WAR 07] Transistor N (X=9790,Y=1730) tr_00293 is not used
[WAR 07] Transistor N (X=9790,Y=1670) tr_00294 is not used
[WAR 07] Transistor N (X=9790,Y=1610) tr_00295 is not used
[WAR 07] Transistor N (X=9790,Y=1550) tr_00296 is not used
[WAR 07] Transistor P (X=2620,Y=7025) tr_00537 is not used
[WAR 07] Transistor P (X=2560,Y=7025) tr_00538 is not used
[WAR 07] Transistor P (X=2500,Y=7025) tr_00539 is not used
[WAR 07] Transistor P (X=2440,Y=7025) tr_00540 is not used
[WAR 07] Transistor P (X=900,Y=7025) tr_00544 is not used
[WAR 07] Transistor P (X=840,Y=7025) tr_00545 is not used
[WAR 07] Transistor P (X=780,Y=7025) tr_00546 is not used
[WAR 07] Transistor P (X=720,Y=7025) tr_00547 is not used
[WAR 07] Transistor P (X=-820,Y=7025) tr_00551 is not used
[WAR 07] Transistor P (X=-880,Y=7025) tr_00552 is not used
[WAR 07] Transistor P (X=-940,Y=7025) tr_00553 is not used
[WAR 07] Transistor P (X=-1000,Y=7025) tr_00554 is not used
[WAR 07] Transistor P (X=-3575,Y=4310) tr_00564 is not used
[WAR 07] Transistor P (X=-3575,Y=4250) tr_00565 is not used
[WAR 07] Transistor P (X=-3575,Y=4190) tr_00566 is not used
[WAR 07] Transistor P (X=-3575,Y=4130) tr_00567 is not used
[WAR 07] Transistor P (X=-3575,Y=2590) tr_00571 is not used
[WAR 07] Transistor P (X=-3575,Y=2530) tr_00572 is not used
[WAR 07] Transistor P (X=-3575,Y=2470) tr_00573 is not used
[WAR 07] Transistor P (X=-3575,Y=2410) tr_00574 is not used
[WAR 07] Transistor P (X=-3575,Y=870) tr_00578 is not used
[WAR 07] Transistor P (X=-3575,Y=810) tr_00579 is not used
[WAR 07] Transistor P (X=-3575,Y=750) tr_00580 is not used
[WAR 07] Transistor P (X=-3575,Y=690) tr_00581 is not used
[WAR 07] Transistor P (X=-3575,Y=-850) tr_00585 is not used
[WAR 07] Transistor P (X=-3575,Y=-910) tr_00586 is not used
[WAR 07] Transistor P (X=-3575,Y=-970) tr_00587 is not used
[WAR 07] Transistor P (X=-3575,Y=-1030) tr_00588 is not used
[WAR 07] Transistor P (X=-3575,Y=-2570) tr_00592 is not used
[WAR 07] Transistor P (X=-3575,Y=-2630) tr_00593 is not used
[WAR 07] Transistor P (X=-3575,Y=-2690) tr_00594 is not used
[WAR 07] Transistor P (X=-3575,Y=-2750) tr_00595 is not used
[WAR 07] Transistor P (X=8945,Y=3270) tr_00608 is not used
[WAR 07] Transistor P (X=8945,Y=3330) tr_00609 is not used
[WAR 07] Transistor P (X=8945,Y=3390) tr_00610 is not used
[WAR 07] Transistor P (X=8945,Y=3450) tr_00611 is not used
[WAR 07] Transistor P (X=8945,Y=1730) tr_00615 is not used
[WAR 07] Transistor P (X=8945,Y=1670) tr_00616 is not used
[WAR 07] Transistor P (X=8945,Y=1610) tr_00617 is not used
[WAR 07] Transistor P (X=8945,Y=1550) tr_00618 is not used
[WAR 11] Loop between 2 gates at 79 'core.l2.dff_m' (flip-flop found 0)
[WAR 11] Loop between 2 gates at 88 'core.l0.dff_m' (flip-flop found 0)
[WAR 11] Loop between 2 gates at 97 'core.l3.dff_m' (flip-flop found 0)
[WAR 11] Loop between 2 gates at 112 'core.l1.dff_m' (flip-flop found 0)

245
alliance/share/tutorials/addaccu/addaccue.vbe
View File

@ -1,245 +0,0 @@
-- VHDL data flow description generated from `addaccue`
-- date : Sun Sep 27 12:26:21 1998
-- Entity Declaration
ENTITY addaccue IS
PORT (
vsse : in BIT; -- vsse
vss : in BIT; -- vss
vdde : in BIT; -- vdde
vdd : in BIT; -- vdd
sel : in BIT; -- sel
s : out bit_vector(3 DOWNTO 0) ; -- s
ck : in BIT; -- ck
b : in bit_vector(3 DOWNTO 0) ; -- b
a : in bit_vector(3 DOWNTO 0) -- a
);
END addaccue;
-- Architecture Declaration
ARCHITECTURE VBE OF addaccue IS
SIGNAL reg : REG_VECTOR(3 DOWNTO 0) REGISTER; -- reg
SIGNAL mbk_sig12 : BIT; -- mbk_sig12
SIGNAL mbk_sig15 : BIT; -- mbk_sig15
SIGNAL mbk_sig14 : BIT; -- mbk_sig14
SIGNAL ss_2 : BIT; -- ss_2
SIGNAL mbk_sig20 : BIT; -- mbk_sig20
SIGNAL mbk_sig22 : BIT; -- mbk_sig22
SIGNAL mbk_sig23 : BIT; -- mbk_sig23
SIGNAL ss_3 : BIT; -- ss_3
SIGNAL mbk_sig149 : BIT; -- mbk_sig149
SIGNAL selsel : BIT; -- selsel
SIGNAL p17_logic_ck : BIT; -- p17.logic.ck
SIGNAL mbk_sig152 : BIT; -- mbk_sig152
SIGNAL mbk_sig10 : BIT; -- mbk_sig10
SIGNAL aa_0 : BIT; -- aa_0
SIGNAL mbk_sig18 : BIT; -- mbk_sig18
SIGNAL aa_1 : BIT; -- aa_1
SIGNAL mbk_sig91 : BIT; -- mbk_sig91
SIGNAL aa_2 : BIT; -- aa_2
SIGNAL mbk_sig151 : BIT; -- mbk_sig151
SIGNAL aa_3 : BIT; -- aa_3
SIGNAL mbk_sig155 : BIT; -- mbk_sig155
SIGNAL bb_0 : BIT; -- bb_0
SIGNAL mbk_sig5 : BIT; -- mbk_sig5
SIGNAL clock : BIT; -- clock
SIGNAL mbk_sig156 : BIT; -- mbk_sig156
SIGNAL bb_1 : BIT; -- bb_1
SIGNAL mbk_sig158 : BIT; -- mbk_sig158
SIGNAL bb_2 : BIT; -- bb_2
SIGNAL mbk_sig160 : BIT; -- mbk_sig160
SIGNAL bb_3 : BIT; -- bb_3
SIGNAL mbk_sig164 : BIT; -- mbk_sig164
SIGNAL mbk_sig162 : BIT; -- mbk_sig162
SIGNAL mbk_sig163 : BIT; -- mbk_sig163
SIGNAL ss_0 : BIT; -- ss_0
SIGNAL mbk_sig165 : BIT; -- mbk_sig165
SIGNAL mbk_sig166 : BIT; -- mbk_sig166
SIGNAL mbk_sig167 : BIT; -- mbk_sig167
SIGNAL ss_1 : BIT; -- ss_1
SIGNAL core_mux_3 : BIT; -- core.mux_3
SIGNAL mbk_sig133 : BIT; -- mbk_sig133
SIGNAL core_int_9 : BIT; -- core.int_9
SIGNAL mbk_sig130 : BIT; -- mbk_sig130
SIGNAL core_carry_2 : BIT; -- core.carry_2
SIGNAL core_int_7 : BIT; -- core.int_7
SIGNAL mbk_sig129 : BIT; -- mbk_sig129
SIGNAL core_int_8 : BIT; -- core.int_8
SIGNAL core_int_6 : BIT; -- core.int_6
SIGNAL core_int_5 : BIT; -- core.int_5
SIGNAL mbk_sig127 : BIT; -- mbk_sig127
SIGNAL core_carry_1 : BIT; -- core.carry_1
SIGNAL mbk_sig126 : BIT; -- mbk_sig126
SIGNAL mbk_sig123 : BIT; -- mbk_sig123
SIGNAL core_mux_2 : BIT; -- core.mux_2
SIGNAL core_int_3 : BIT; -- core.int_3
SIGNAL mbk_sig121 : BIT; -- mbk_sig121
SIGNAL core_int_4 : BIT; -- core.int_4
SIGNAL core_int_2 : BIT; -- core.int_2
SIGNAL mbk_sig120 : BIT; -- mbk_sig120
SIGNAL core_carry_0 : BIT; -- core.carry_0
SIGNAL mbk_sig118 : BIT; -- mbk_sig118
SIGNAL core_mux_1 : BIT; -- core.mux_1
SIGNAL core_regout_2 : BIT; -- core.regout_2
SIGNAL mbk_sig107 : BIT; -- mbk_sig107
SIGNAL core_mux_0 : BIT; -- core.mux_0
SIGNAL mbk_sig104 : BIT; -- mbk_sig104
SIGNAL core_regout_0 : BIT; -- core.regout_0
SIGNAL core_nsel : BIT; -- core.nsel
SIGNAL mbk_sig76 : BIT; -- mbk_sig76
SIGNAL core_regout_3 : BIT; -- core.regout_3
SIGNAL mbk_sig63 : BIT; -- mbk_sig63
SIGNAL mbk_sig65 : BIT; -- mbk_sig65
SIGNAL mbk_sig57 : BIT; -- mbk_sig57
SIGNAL mbk_sig56 : BIT; -- mbk_sig56
SIGNAL mbk_sig51 : BIT; -- mbk_sig51
SIGNAL core_int_1 : BIT; -- core.int_1
SIGNAL mbk_sig46 : BIT; -- mbk_sig46
SIGNAL core_regout_1 : BIT; -- core.regout_1
SIGNAL mbk_sig43 : BIT; -- mbk_sig43
SIGNAL mbk_sig36 : BIT; -- mbk_sig36
SIGNAL mbk_sig35 : BIT; -- mbk_sig35
SIGNAL mbk_sig75 : BIT; -- mbk_sig75
SIGNAL mbk_sig103 : BIT; -- mbk_sig103
SIGNAL mbk_sig115 : BIT; -- mbk_sig115
SIGNAL mbk_sig30 : BIT; -- mbk_sig30
SIGNAL mbk_sig71 : BIT; -- mbk_sig71
SIGNAL mbk_sig97 : BIT; -- mbk_sig97
SIGNAL mbk_sig109 : BIT; -- mbk_sig109
SIGNAL yag_zero : BIT; -- yag_zero
SIGNAL yag_one : BIT; -- yag_one
BEGIN
yag_one <= '1';
yag_zero <= '0';
mbk_sig109 <= not (ss_2);
mbk_sig97 <= not (ss_0);
mbk_sig71 <= not (ss_3);
mbk_sig30 <= not (ss_1);
mbk_sig115 <= not (reg (2));
mbk_sig103 <= not (reg (0));
mbk_sig75 <= not (reg (3));
mbk_sig35 <= not (reg (1));
mbk_sig36 <= (not (core_int_1) and not (core_carry_0));
mbk_sig43 <= ((not (selsel) and not (aa_0)) or (not (selsel) and not (core_nsel))
or (not (core_regout_0) and not (aa_0)) or (not (core_regout_0)
and not (core_nsel)));
core_regout_1 <= not (reg (1));
mbk_sig46 <= ((not (selsel) and not (aa_1)) or (not (selsel) and not (core_nsel))
or (not (core_regout_1) and not (aa_1)) or (not (core_regout_1)
and not (core_nsel)));
core_int_1 <= ((not (mbk_sig51) and not (bb_1)) or (not (mbk_sig51) and not
(core_mux_1)));
mbk_sig51 <= (not (core_mux_1) and not (bb_1));
mbk_sig56 <= (not (core_mux_1) or not (bb_1));
mbk_sig57 <= ((not (selsel) and not (aa_2)) or (not (selsel) and not (core_nsel))
or (not (core_regout_2) and not (aa_2)) or (not (core_regout_2)
and not (core_nsel)));
mbk_sig65 <= (not (core_mux_2) or not (bb_2));
mbk_sig63 <= (not (core_mux_2) and not (bb_2));
core_regout_3 <= not (reg (3));
mbk_sig76 <= ((not (selsel) and not (aa_3)) or (not (selsel) and not (core_nsel))
or (not (core_regout_3) and not (aa_3)) or (not (core_regout_3)
and not (core_nsel)));
core_nsel <= not (selsel);
core_regout_0 <= not (reg (0));
mbk_sig104 <= (not (core_mux_0) and not (bb_0));
core_mux_0 <= not (mbk_sig43);
mbk_sig107 <= (not (core_mux_0) or not (bb_0));
core_regout_2 <= not (reg (2));
core_mux_1 <= not (mbk_sig46);
mbk_sig118 <= (not (core_mux_1) or not (core_carry_0));
core_carry_0 <= not (mbk_sig107);
mbk_sig120 <= (not (bb_1) or not (core_carry_0));
core_int_2 <= not (mbk_sig56);
core_int_4 <= not (mbk_sig120);
mbk_sig121 <= (not (core_int_4) and not (core_int_3) and not (core_int_2));
core_int_3 <= not (mbk_sig118);
core_mux_2 <= not (mbk_sig57);
mbk_sig123 <= (not (core_mux_2) or not (core_carry_1));
mbk_sig126 <= (not (bb_2) or not (core_carry_1));
core_carry_1 <= not (mbk_sig121);
mbk_sig127 <= (not (core_int_5) and not (core_carry_1));
core_int_5 <= ((not (mbk_sig63) and not (bb_2)) or (not (mbk_sig63) and not
(core_mux_2)));
core_int_6 <= not (mbk_sig65);
core_int_8 <= not (mbk_sig126);
mbk_sig129 <= (not (core_int_8) and not (core_int_7) and not (core_int_6));
core_int_7 <= not (mbk_sig123);
core_carry_2 <= not (mbk_sig129);
mbk_sig130 <= (not (core_int_9) and not (core_carry_2));
core_int_9 <= ((not (mbk_sig133) and not (bb_3)) or (not (mbk_sig133) and not
(core_mux_3)));
mbk_sig133 <= (not (core_mux_3) and not (bb_3));
core_mux_3 <= not (mbk_sig76);
ss_1 <= ((not (mbk_sig36) and not (core_carry_0)) or (not (mbk_sig36)
and not (core_int_1)));
mbk_sig167 <= not (ss_1);
mbk_sig166 <= not (mbk_sig167);
mbk_sig165 <= not (mbk_sig166);
ss_0 <= ((not (mbk_sig104) and not (bb_0)) or (not (mbk_sig104) and not
(core_mux_0)));
mbk_sig163 <= not (ss_0);
mbk_sig162 <= not (mbk_sig163);
mbk_sig164 <= not (mbk_sig162);
bb_3 <= not (mbk_sig160);
mbk_sig160 <= not (b (3));
bb_2 <= not (mbk_sig158);
mbk_sig158 <= not (b (2));
bb_1 <= not (mbk_sig156);
mbk_sig156 <= not (b (1));
clock <= not (mbk_sig5);
mbk_sig5 <= not (p17_logic_ck);
bb_0 <= not (mbk_sig155);
mbk_sig155 <= not (b (0));
aa_3 <= not (mbk_sig151);
mbk_sig151 <= not (a (3));
aa_2 <= not (mbk_sig91);
mbk_sig91 <= not (a (2));
aa_1 <= not (mbk_sig18);
mbk_sig18 <= not (a (1));
aa_0 <= not (mbk_sig10);
mbk_sig10 <= not (a (0));
mbk_sig152 <= not (ck);
p17_logic_ck <= not (mbk_sig152);
selsel <= not (mbk_sig149);
mbk_sig149 <= not (sel);
ss_3 <= ((not (mbk_sig130) and not (core_carry_2)) or (not (mbk_sig130)
and not (core_int_9)));
mbk_sig23 <= not (ss_3);
mbk_sig22 <= not (mbk_sig23);
mbk_sig20 <= not (mbk_sig22);
ss_2 <= ((not (mbk_sig127) and not (core_carry_1)) or (not (mbk_sig127)
and not (core_int_5)));
mbk_sig14 <= not (ss_2);
mbk_sig15 <= not (mbk_sig14);
mbk_sig12 <= not (mbk_sig15);
label0 : BLOCK ((not (clock) and not (clock'STABLE)) = '1')
BEGIN
reg (0) <= GUARDED mbk_sig97;
END BLOCK label0;
label1 : BLOCK ((not (clock) and not (clock'STABLE)) = '1')
BEGIN
reg (1) <= GUARDED mbk_sig30;
END BLOCK label1;
label2 : BLOCK ((not (clock) and not (clock'STABLE)) = '1')
BEGIN
reg (2) <= GUARDED mbk_sig109;
END BLOCK label2;
label3 : BLOCK ((not (clock) and not (clock'STABLE)) = '1')
BEGIN
reg (3) <= GUARDED mbk_sig71;
END BLOCK label3;
s (0) <= not (mbk_sig164);
s (1) <= not (mbk_sig165);
s (2) <= not (mbk_sig12);
s (3) <= not (mbk_sig20);
END;

227
alliance/share/tutorials/addaccu/core.al
View File

@ -1,227 +0,0 @@
V ALLIANCE : 6
H core,L,27/ 9/98
C vss,UNKNOWN,EXTERNAL,2
C vdd,UNKNOWN,EXTERNAL,15
C sel,UNKNOWN,EXTERNAL,9
C s 3,UNKNOWN,EXTERNAL,22
C s 2,UNKNOWN,EXTERNAL,33
C s 1,UNKNOWN,EXTERNAL,1
C s 0,UNKNOWN,EXTERNAL,31
C ck,UNKNOWN,EXTERNAL,3
C b 3,UNKNOWN,EXTERNAL,37
C b 2,UNKNOWN,EXTERNAL,21
C b 1,UNKNOWN,EXTERNAL,14
C b 0,UNKNOWN,EXTERNAL,32
C a 3,UNKNOWN,EXTERNAL,25
C a 2,UNKNOWN,EXTERNAL,17
C a 1,UNKNOWN,EXTERNAL,12
C a 0,UNKNOWN,EXTERNAL,7
I xr2_y,xr5
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,36
C i1,UNKNOWN,INTERNAL,37
C i0,UNKNOWN,INTERNAL,26
I xr2_y,xr6
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,22
C i1,UNKNOWN,INTERNAL,30
C i0,UNKNOWN,INTERNAL,36
I o3_y,an8
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,30
C i2,UNKNOWN,INTERNAL,29
C i1,UNKNOWN,INTERNAL,35
C i0,UNKNOWN,INTERNAL,20
I xr2_y,xr4
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,33
C i1,UNKNOWN,INTERNAL,28
C i0,UNKNOWN,INTERNAL,23
I a2_y,an7
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,29
C i1,UNKNOWN,INTERNAL,28
C i0,UNKNOWN,INTERNAL,21
I a2_y,an6
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,35
C i1,UNKNOWN,INTERNAL,28
C i0,UNKNOWN,INTERNAL,19
I o3_y,an4
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,28
C i2,UNKNOWN,INTERNAL,27
C i1,UNKNOWN,INTERNAL,34
C i0,UNKNOWN,INTERNAL,16
I tie_y,feed3
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
I tie_y,feed2
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
I a2_y,an3
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,27
C i1,UNKNOWN,INTERNAL,5
C i0,UNKNOWN,INTERNAL,14
I a2_y,an2
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,34
C i1,UNKNOWN,INTERNAL,5
C i0,UNKNOWN,INTERNAL,13
I ms_y,l2
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,18
C l,UNKNOWN,INTERNAL,3
C i,UNKNOWN,INTERNAL,33
I a2_y,an0
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,5
C i1,UNKNOWN,INTERNAL,32
C i0,UNKNOWN,INTERNAL,11
I xr2_y,xr0
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,31
C i1,UNKNOWN,INTERNAL,32
C i0,UNKNOWN,INTERNAL,11
I ms_y,l0
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,10
C l,UNKNOWN,INTERNAL,3
C i,UNKNOWN,INTERNAL,31
I mx2_y,mux3
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,26
C l1,UNKNOWN,INTERNAL,9
C l0,UNKNOWN,INTERNAL,8
C i1,UNKNOWN,INTERNAL,24
C i0,UNKNOWN,INTERNAL,25
I ms_y,l3
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,24
C l,UNKNOWN,INTERNAL,3
C i,UNKNOWN,INTERNAL,22
I xr2_y,xr3
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,23
C i1,UNKNOWN,INTERNAL,21
C i0,UNKNOWN,INTERNAL,19
I a2_y,an5
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,20
C i1,UNKNOWN,INTERNAL,21
C i0,UNKNOWN,INTERNAL,19
I mx2_y,mux2
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,19
C l1,UNKNOWN,INTERNAL,9
C l0,UNKNOWN,INTERNAL,8
C i1,UNKNOWN,INTERNAL,18
C i0,UNKNOWN,INTERNAL,17
I n1_y,n10
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C i,UNKNOWN,INTERNAL,9
C f,UNKNOWN,INTERNAL,8
I a2_y,an1
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,16
C i1,UNKNOWN,INTERNAL,14
C i0,UNKNOWN,INTERNAL,13
I tie_y,feed1
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
I tie_y,feed0
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
I xr2_y,xr1
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,6
C i1,UNKNOWN,INTERNAL,14
C i0,UNKNOWN,INTERNAL,13
I mx2_y,mux1
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,13
C l1,UNKNOWN,INTERNAL,9
C l0,UNKNOWN,INTERNAL,8
C i1,UNKNOWN,INTERNAL,4
C i0,UNKNOWN,INTERNAL,12
I mx2_y,mux0
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,11
C l1,UNKNOWN,INTERNAL,9
C l0,UNKNOWN,INTERNAL,8
C i1,UNKNOWN,INTERNAL,10
C i0,UNKNOWN,INTERNAL,7
I xr2_y,xr2
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,1
C i1,UNKNOWN,INTERNAL,5
C i0,UNKNOWN,INTERNAL,6
I ms_y,l1
C vss,UNKNOWN,INTERNAL,2
C vdd,UNKNOWN,INTERNAL,15
C t,UNKNOWN,INTERNAL,4
C l,UNKNOWN,INTERNAL,3
C i,UNKNOWN,INTERNAL,1
S 37,EXTERNAL,b 3
S 36,INTERNAL,int_9
S 35,INTERNAL,int_7
S 34,INTERNAL,int_3
S 33,EXTERNAL,s 2
S 32,EXTERNAL,b 0
S 31,EXTERNAL,s 0
S 30,INTERNAL,carry_2
S 29,INTERNAL,int_8
S 28,INTERNAL,carry_1
S 27,INTERNAL,int_4
S 26,INTERNAL,mux_3
S 25,EXTERNAL,a 3
S 24,INTERNAL,regout_3
S 23,INTERNAL,int_5
S 22,EXTERNAL,s 3
S 21,EXTERNAL,b 2
S 20,INTERNAL,int_6
S 19,INTERNAL,mux_2
S 18,INTERNAL,regout_2
S 17,EXTERNAL,a 2
S 16,INTERNAL,int_2
S 15,EXTERNAL,vdd
S 14,EXTERNAL,b 1
S 13,INTERNAL,mux_1
S 12,EXTERNAL,a 1
S 11,INTERNAL,mux_0
S 10,INTERNAL,regout_0
S 9,EXTERNAL,sel
S 8,INTERNAL,nsel
S 7,EXTERNAL,a 0
S 6,INTERNAL,int_1
S 5,INTERNAL,carry_0
S 4,INTERNAL,regout_1
S 3,EXTERNAL,ck
S 2,EXTERNAL,vss
S 1,EXTERNAL,s 1
EOF

316
alliance/share/tutorials/addaccu/core.ap
View File

@ -1,316 +0,0 @@
V ALLIANCE : 4
H core,P,27/ 8/98,10
A 0,0,5520,1700
C 2810,0,80,vss,0,SOUTH,ALU2
C 2710,0,80,vdd,0,SOUTH,ALU2
C 2810,1700,80,vss,5,NORTH,ALU2
C 2710,1700,80,vdd,5,NORTH,ALU2
C 5520,1130,80,vss,4,EAST,ALU1
C 5520,1510,80,vdd,4,EAST,ALU1
C 0,1130,80,vss,3,WEST,ALU1
C 0,1510,80,vdd,3,WEST,ALU1
C 5520,290,80,vss,2,EAST,ALU1
C 5520,670,80,vdd,2,EAST,ALU1
C 0,290,80,vss,1,WEST,ALU1
C 0,670,80,vdd,1,WEST,ALU1
C 1230,0,20,a 0,0,SOUTH,ALU2
C 1650,0,20,a 1,0,SOUTH,ALU2
C 3270,0,20,a 2,0,SOUTH,ALU2
C 5130,0,20,a 3,0,SOUTH,ALU2
C 1290,1700,20,b 0,0,NORTH,ALU2
C 2610,1700,20,b 1,0,NORTH,ALU2
C 3750,1700,20,b 2,0,NORTH,ALU2
C 5190,1700,20,b 3,0,NORTH,ALU2
C 5310,0,20,sel,0,SOUTH,ALU2
C 4650,0,20,ck,0,SOUTH,ALU2
C 30,1700,20,s 0,0,NORTH,ALU2
C 30,0,20,s 1,0,SOUTH,ALU2
C 1470,1700,20,s 2,0,NORTH,ALU2
C 4410,0,20,s 3,0,SOUTH,ALU2
S 30,210,1170,210,10,s 1,RIGHT,ALU1
S 690,160,1890,160,10,regout_1,RIGHT,ALU1
S 1050,110,1950,110,10,int_1,RIGHT,ALU1
S 1290,210,5190,210,10,nsel,RIGHT,ALU1
S 1410,60,5310,60,10,sel,RIGHT,ALU1
S 1950,160,2490,160,10,int_1,RIGHT,ALU1
S 5070,160,5250,160,10,regout_3,RIGHT,ALU1
S 5250,210,5370,210,10,regout_3,RIGHT,ALU1
S 30,0,30,270,20,s 1,UP,ALU2
S 690,160,690,270,20,regout_1,UP,ALU2
S 1050,110,1050,270,20,int_1,UP,ALU2
S 1170,210,1170,270,20,s 1,UP,ALU2
S 1230,0,1230,270,20,a 0,UP,ALU2
S 1290,210,1290,270,20,nsel,UP,ALU2
S 1410,60,1410,270,20,sel,UP,ALU2
S 1650,0,1650,270,20,a 1,UP,ALU2
S 1710,210,1710,270,20,nsel,UP,ALU2
S 1830,60,1830,270,20,sel,UP,ALU2
S 1890,160,1890,270,20,regout_1,UP,ALU2
S 1950,110,1950,160,20,int_1,UP,ALU2
S 2490,160,2490,270,20,int_1,UP,ALU2
S 3150,210,3150,270,20,nsel,UP,ALU2
S 3210,60,3210,270,20,sel,UP,ALU2
S 3270,0,3270,270,20,a 2,UP,ALU2
S 3330,210,3330,270,20,nsel,UP,ALU2
S 3450,60,3450,270,20,sel,UP,ALU2
S 4410,0,4410,270,20,s 3,UP,ALU2
S 4650,0,4650,270,20,ck,UP,ALU2
S 5070,160,5070,270,20,regout_3,UP,ALU2
S 5130,0,5130,270,20,a 3,UP,ALU2
S 5190,210,5190,270,20,nsel,UP,ALU2
S 5250,160,5250,210,20,regout_3,UP,ALU2
S 5310,0,5310,270,20,sel,UP,ALU2
S 5370,210,5370,270,20,regout_3,UP,ALU2
S 270,1050,1710,1050,10,ck,RIGHT,ALU1
S 690,750,1470,750,10,regout_0,RIGHT,ALU1
S 870,1000,2490,1000,10,carry_0,RIGHT,ALU1
S 1050,950,1410,950,10,mux_0,RIGHT,ALU1
S 1410,800,1590,800,10,mux_0,RIGHT,ALU1
S 1710,750,4650,750,10,ck,RIGHT,ALU1
S 2010,800,3090,800,10,mux_1,RIGHT,ALU1
S 2130,850,3510,850,10,regout_2,RIGHT,ALU1
S 2190,1050,3150,1050,10,int_3,RIGHT,ALU1
S 2190,900,2970,900,10,b 1,RIGHT,ALU1
S 2430,950,3210,950,10,int_4,RIGHT,ALU1
S 2910,1000,3090,1000,10,int_2,RIGHT,ALU1
S 3030,900,3150,900,10,carry_1,RIGHT,ALU1
S 3150,1000,3930,1000,10,carry_1,RIGHT,ALU1
S 3330,1050,4410,1050,10,int_7,RIGHT,ALU1
S 3510,950,3690,950,10,mux_2,RIGHT,ALU1
S 3570,900,4470,900,10,int_8,RIGHT,ALU1
S 3690,850,4230,850,10,mux_2,RIGHT,ALU1
S 3690,800,3990,800,10,int_6,RIGHT,ALU1
S 3750,950,4050,950,10,b 2,RIGHT,ALU1
S 3990,1000,4350,1000,10,int_6,RIGHT,ALU1
S 4110,800,4350,800,10,int_5,RIGHT,ALU1
S 4290,950,4530,950,10,carry_2,RIGHT,ALU1
S 4410,1000,5010,1000,10,s 3,RIGHT,ALU1
S 4530,1050,4710,1050,10,carry_2,RIGHT,ALU1
S 4890,1050,5490,1050,10,int_9,RIGHT,ALU1
S 5370,750,5490,750,10,mux_3,RIGHT,ALU1
S 270,690,270,1110,20,ck,UP,ALU2
S 690,750,690,1110,20,regout_0,UP,ALU2
S 870,690,870,1000,20,carry_0,UP,ALU2
S 1050,950,1050,1110,20,mux_0,UP,ALU2
S 1230,1000,1230,1110,20,carry_0,UP,ALU2
S 1410,800,1410,1110,20,mux_0,UP,ALU2
S 1470,690,1470,750,20,regout_0,UP,ALU2
S 1590,690,1590,800,20,mux_0,UP,ALU2
S 1710,750,1710,1110,20,ck,UP,ALU2
S 2010,690,2010,800,20,mux_1,UP,ALU2
S 2130,850,2130,1110,20,regout_2,UP,ALU2
S 2190,1050,2190,1110,20,int_3,UP,ALU2
S 2190,690,2190,900,20,b 1,UP,ALU2
S 2250,1000,2250,1110,20,carry_0,UP,ALU2
S 2370,690,2370,1110,20,mux_1,UP,ALU2
S 2430,950,2430,1110,20,int_4,UP,ALU2
S 2490,1000,2490,1110,20,carry_0,UP,ALU2
S 2610,900,2610,1110,20,b 1,UP,ALU2
S 2910,690,2910,1000,20,int_2,UP,ALU2
S 2970,690,2970,900,20,b 1,UP,ALU2
S 3030,900,3030,1110,20,carry_1,UP,ALU2
S 3090,1000,3090,1110,20,int_2,UP,ALU2
S 3090,690,3090,800,20,mux_1,UP,ALU2
S 3150,1050,3150,1110,20,int_3,UP,ALU2
S 3150,900,3150,1000,20,carry_1,UP,ALU2
S 3210,950,3210,1110,20,int_4,UP,ALU2
S 3330,1050,3330,1110,20,int_7,UP,ALU2
S 3390,1000,3390,1110,20,carry_1,UP,ALU2
S 3510,950,3510,1110,20,mux_2,UP,ALU2
S 3510,690,3510,850,20,regout_2,UP,ALU2
S 3570,900,3570,1110,20,int_8,UP,ALU2
S 3630,1000,3630,1110,20,carry_1,UP,ALU2
S 3630,690,3630,950,20,mux_2,UP,ALU2
S 3690,850,3690,950,20,mux_2,UP,ALU2
S 3690,690,3690,800,20,int_6,UP,ALU2
S 3750,690,3750,1110,20,b 2,UP,ALU2
S 3870,690,3870,850,20,mux_2,UP,ALU2
S 3930,1000,3930,1110,20,carry_1,UP,ALU2
S 3990,800,3990,1000,20,int_6,UP,ALU2
S 4050,690,4050,950,20,b 2,UP,ALU2
S 4110,800,4110,1110,20,int_5,UP,ALU2
S 4230,690,4230,850,20,mux_2,UP,ALU2
S 4290,950,4290,1110,20,carry_2,UP,ALU2
S 4350,1000,4350,1110,20,int_6,UP,ALU2
S 4350,690,4350,800,20,int_5,UP,ALU2
S 4410,1050,4410,1110,20,int_7,UP,ALU2
S 4410,690,4410,1000,20,s 3,UP,ALU2
S 4470,900,4470,1110,20,int_8,UP,ALU2
S 4530,950,4530,1050,20,carry_2,UP,ALU2
S 4650,690,4650,750,20,ck,UP,ALU2
S 4710,1050,4710,1110,20,carry_2,UP,ALU2
S 4890,1050,4890,1110,20,int_9,UP,ALU2
S 5010,1000,5010,1110,20,s 3,UP,ALU2
S 5370,750,5370,1110,20,mux_3,UP,ALU2
S 5490,1050,5490,1110,20,int_9,UP,ALU2
S 5490,690,5490,750,20,mux_3,UP,ALU2
S 30,1590,1170,1590,10,s 0,RIGHT,ALU1
S 870,1640,1290,1640,10,b 0,RIGHT,ALU1
S 1470,1590,4230,1590,10,s 2,RIGHT,ALU1
S 30,1530,30,1700,20,s 0,UP,ALU2
S 870,1530,870,1640,20,b 0,UP,ALU2
S 1170,1530,1170,1590,20,s 0,UP,ALU2
S 1290,1530,1290,1700,20,b 0,UP,ALU2
S 1470,1530,1470,1700,20,s 2,UP,ALU2
S 2610,1530,2610,1700,20,b 1,UP,ALU2
S 3750,1530,3750,1700,20,b 2,UP,ALU2
S 4230,1530,4230,1590,20,s 2,UP,ALU2
S 5190,1530,5190,1700,20,b 3,UP,ALU2
S 2810,0,2810,1700,80,vss,UP,ALU2
S 2710,0,2710,1700,80,vdd,UP,ALU2
S 2790,1130,2830,1130,70,*,RIGHT,ALU2
S 2790,1130,2830,1130,60,*,RIGHT,ALU1
S 2810,1110,2810,1150,70,*,UP,ALU2
S 2810,1110,2810,1150,60,*,UP,ALU1
S 2690,1510,2730,1510,70,*,RIGHT,ALU2
S 2690,1510,2730,1510,60,*,RIGHT,ALU1
S 2710,1490,2710,1530,70,*,UP,ALU2
S 2710,1490,2710,1530,60,*,UP,ALU1
S 2640,1510,2880,1510,80,vdd,RIGHT,ALU1
S 2640,1130,2880,1130,80,vss,RIGHT,ALU1
S 2790,290,2830,290,70,*,RIGHT,ALU2
S 2790,290,2830,290,60,*,RIGHT,ALU1
S 2810,270,2810,310,70,*,UP,ALU2
S 2810,270,2810,310,60,*,UP,ALU1
S 2690,670,2730,670,70,*,RIGHT,ALU2
S 2690,670,2730,670,60,*,RIGHT,ALU1
S 2710,650,2710,690,70,*,UP,ALU2
S 2710,650,2710,690,60,*,UP,ALU1
S 2640,670,2880,670,80,vdd,RIGHT,ALU1
S 2640,290,2880,290,80,vss,RIGHT,ALU1
I 0,270,ms_y,l1,NOSYM
I 720,270,xr2_y,xr2,NOSYM
I 1200,270,mx2_y,mux0,NOSYM
I 1620,270,mx2_y,mux1,NOSYM
I 2040,270,xr2_y,xr1,NOSYM
I 2520,270,tie_y,feed0,NOSYM
I 2580,270,tie_y,feed1,NOSYM
I 2880,270,a2_y,an1,NOSYM
I 3120,270,n1_y,n10,NOSYM
I 3240,270,mx2_y,mux2,NOSYM
I 3660,270,a2_y,an5,NOSYM
I 3900,270,xr2_y,xr3,NOSYM
I 4380,270,ms_y,l3,NOSYM
I 5100,270,mx2_y,mux3,NOSYM
I 0,1110,ms_y,l0,NOSYM
I 720,1110,xr2_y,xr0,NOSYM
I 1200,1110,a2_y,an0,NOSYM
I 1440,1110,ms_y,l2,NOSYM
I 2160,1110,a2_y,an2,NOSYM
I 2400,1110,a2_y,an3,NOSYM
I 2880,1110,tie_y,feed2,NOSYM
I 2940,1110,tie_y,feed3,NOSYM
I 3000,1110,o3_y,an4,NOSYM
I 3300,1110,a2_y,an6,NOSYM
I 3540,1110,a2_y,an7,NOSYM
I 3780,1110,xr2_y,xr4,NOSYM
I 4260,1110,o3_y,an8,NOSYM
I 4560,1110,xr2_y,xr6,NOSYM
I 5040,1110,xr2_y,xr5,NOSYM
V 30,210,CONT_VIA
V 690,160,CONT_VIA
V 1050,110,CONT_VIA
V 1170,210,CONT_VIA
V 1290,210,CONT_VIA
V 1410,60,CONT_VIA
V 1710,210,CONT_VIA
V 1830,60,CONT_VIA
V 1890,160,CONT_VIA
V 1950,160,CONT_VIA
V 1950,110,CONT_VIA
V 2490,160,CONT_VIA
V 3150,210,CONT_VIA
V 3210,60,CONT_VIA
V 3330,210,CONT_VIA
V 3450,60,CONT_VIA
V 5070,160,CONT_VIA
V 5190,210,CONT_VIA
V 5250,210,CONT_VIA
V 5250,160,CONT_VIA
V 5310,60,CONT_VIA
V 5370,210,CONT_VIA
V 270,1050,CONT_VIA
V 690,750,CONT_VIA
V 870,1000,CONT_VIA
V 1050,950,CONT_VIA
V 1230,1000,CONT_VIA
V 1410,950,CONT_VIA
V 1410,800,CONT_VIA
V 1470,750,CONT_VIA
V 1590,800,CONT_VIA
V 1710,1050,CONT_VIA
V 1710,750,CONT_VIA
V 2010,800,CONT_VIA
V 2130,850,CONT_VIA
V 2190,1050,CONT_VIA
V 2190,900,CONT_VIA
V 2250,1000,CONT_VIA
V 2370,800,CONT_VIA
V 2430,950,CONT_VIA
V 2490,1000,CONT_VIA
V 2610,900,CONT_VIA
V 2910,1000,CONT_VIA
V 2970,900,CONT_VIA
V 3030,900,CONT_VIA
V 3090,1000,CONT_VIA
V 3090,800,CONT_VIA
V 3150,1050,CONT_VIA
V 3150,1000,CONT_VIA
V 3150,900,CONT_VIA
V 3210,950,CONT_VIA
V 3330,1050,CONT_VIA
V 3390,1000,CONT_VIA
V 3510,950,CONT_VIA
V 3510,850,CONT_VIA
V 3570,900,CONT_VIA
V 3630,1000,CONT_VIA
V 3630,950,CONT_VIA
V 3690,950,CONT_VIA
V 3690,850,CONT_VIA
V 3690,800,CONT_VIA
V 3750,950,CONT_VIA
V 3870,850,CONT_VIA
V 3930,1000,CONT_VIA
V 3990,1000,CONT_VIA
V 3990,800,CONT_VIA
V 4050,950,CONT_VIA
V 4110,800,CONT_VIA
V 4230,850,CONT_VIA
V 4290,950,CONT_VIA
V 4350,1000,CONT_VIA
V 4350,800,CONT_VIA
V 4410,1050,CONT_VIA
V 4410,1000,CONT_VIA
V 4470,900,CONT_VIA
V 4530,1050,CONT_VIA
V 4530,950,CONT_VIA
V 4650,750,CONT_VIA
V 4710,1050,CONT_VIA
V 4890,1050,CONT_VIA
V 5010,1000,CONT_VIA
V 5370,750,CONT_VIA
V 5490,1050,CONT_VIA
V 5490,750,CONT_VIA
V 30,1590,CONT_VIA
V 870,1640,CONT_VIA
V 1170,1590,CONT_VIA
V 1290,1640,CONT_VIA
V 1470,1590,CONT_VIA
V 4230,1590,CONT_VIA
V 2830,1150,CONT_VIA
V 2830,1110,CONT_VIA
V 2790,1150,CONT_VIA
V 2790,1110,CONT_VIA
V 2730,1530,CONT_VIA
V 2730,1490,CONT_VIA
V 2690,1530,CONT_VIA
V 2690,1490,CONT_VIA
V 2830,310,CONT_VIA
V 2830,270,CONT_VIA
V 2790,310,CONT_VIA
V 2790,270,CONT_VIA
V 2730,690,CONT_VIA
V 2730,650,CONT_VIA
V 2690,690,CONT_VIA
V 2690,650,CONT_VIA
EOF

42
alliance/share/tutorials/addaccu/core.lvx
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@ -1,42 +0,0 @@
@@@@@@ @@@@ @@@ @@@@ @@@@
@@ @@ @ @@ @
@@ @@ @ @@ @
@@ @@ @ @@ @
@@ @@ @ @@
@@ @@ @ @@
@@ @@ @ @@@
@@ @@@ @ @@
@@ @ @@@ @ @@
@@ @ @ @ @@
@@@@@@@@@@ @ @@@ @@@@
Gate Netlist Comparator
Alliance CAD System 3.5, lvx 2.23
Copyright (c) 1992-1998, ASIM/LIP6/UPMC
E-mail support: alliance-support@asim.lip6.fr
***** Loading and flattening core (vst)...
***** Loading and flattening core (al)...
***** Compare Terminals ..............
***** O.K. (0 sec)
***** Compare Instances ..........
***** O.K. (0 sec)
***** Compare Connections ............
***** O.K. (0 sec)
===== Terminals .......... 16
===== Instances .......... 25
===== Connectors ......... 150
***** Netlists are Identical. ***** (0 sec)

293
alliance/share/tutorials/addaccu/core.vst
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@ -1,293 +0,0 @@
-- VHDL structural description generated from `core`
-- date : Fri Sep 25 12:14:00 1998
-- Entity Declaration
ENTITY core IS
PORT (
a : in BIT_VECTOR (0 TO 3); -- a
b : in BIT_VECTOR (0 TO 3); -- b
sel : in BIT; -- sel
ck : in BIT; -- ck
s : inout BIT_VECTOR (0 TO 3); -- s
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END core;
-- Architecture Declaration
ARCHITECTURE VST OF core IS
COMPONENT a2_y
port (
i0 : in BIT; -- i0
i1 : in BIT; -- i1
t : out BIT; -- t
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT o3_y
port (
i0 : in BIT; -- i0
i1 : in BIT; -- i1
i2 : in BIT; -- i2
t : out BIT; -- t
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT xr2_y
port (
i0 : in BIT; -- i0
i1 : in BIT; -- i1
t : out BIT; -- t
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT n1_y
port (
i : in BIT; -- i
f : out BIT; -- f
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT mx2_y
port (
i0 : in BIT; -- i0
l0 : in BIT; -- l0
i1 : in BIT; -- i1
l1 : in BIT; -- l1
t : out BIT; -- t
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT ms_y
port (
i : in BIT; -- i
l : in BIT; -- l
t : out BIT; -- t
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
SIGNAL carry_0 : BIT; -- carry 0
SIGNAL carry_1 : BIT; -- carry 1
SIGNAL carry_2 : BIT; -- carry 2
SIGNAL int_1 : BIT; -- int 1
SIGNAL int_2 : BIT; -- int 2
SIGNAL int_3 : BIT; -- int 3
SIGNAL int_4 : BIT; -- int 4
SIGNAL int_5 : BIT; -- int 5
SIGNAL int_6 : BIT; -- int 6
SIGNAL int_7 : BIT; -- int 7
SIGNAL int_8 : BIT; -- int 8
SIGNAL int_9 : BIT; -- int 9
SIGNAL mux_0 : BIT; -- mux 0
SIGNAL mux_1 : BIT; -- mux 1
SIGNAL mux_2 : BIT; -- mux 2
SIGNAL mux_3 : BIT; -- mux 3
SIGNAL nsel : BIT; -- nsel
SIGNAL regout_0 : BIT; -- regout 0
SIGNAL regout_1 : BIT; -- regout 1
SIGNAL regout_2 : BIT; -- regout 2
SIGNAL regout_3 : BIT; -- regout 3
BEGIN
xr0 : xr2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => s(0),
i1 => b(0),
i0 => mux_0);
an0 : a2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => carry_0,
i1 => b(0),
i0 => mux_0);
xr1 : xr2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => int_1,
i1 => b(1),
i0 => mux_1);
xr2 : xr2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => s(1),
i1 => carry_0,
i0 => int_1);
an1 : a2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => int_2,
i1 => b(1),
i0 => mux_1);
an2 : a2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => int_3,
i1 => carry_0,
i0 => mux_1);
an3 : a2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => int_4,
i1 => carry_0,
i0 => b(1));
an4 : o3_y
PORT MAP (
vss => vss,
vdd => vdd,
t => carry_1,
i2 => int_4,
i1 => int_3,
i0 => int_2);
xr3 : xr2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => int_5,
i1 => b(2),
i0 => mux_2);
xr4 : xr2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => s(2),
i1 => carry_1,
i0 => int_5);
an5 : a2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => int_6,
i1 => b(2),
i0 => mux_2);
an6 : a2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => int_7,
i1 => carry_1,
i0 => mux_2);
an7 : a2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => int_8,
i1 => carry_1,
i0 => b(2));
an8 : o3_y
PORT MAP (
vss => vss,
vdd => vdd,
t => carry_2,
i2 => int_8,
i1 => int_7,
i0 => int_6);
xr5 : xr2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => int_9,
i1 => b(3),
i0 => mux_3);
xr6 : xr2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => s(3),
i1 => carry_2,
i0 => int_9);
n10 : n1_y
PORT MAP (
vss => vss,
vdd => vdd,
f => nsel,
i => sel);
mux0 : mx2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => mux_0,
l1 => sel,
i1 => regout_0,
l0 => nsel,
i0 => a(0));
l0 : ms_y
PORT MAP (
vss => vss,
vdd => vdd,
t => regout_0,
l => ck,
i => s(0));
mux1 : mx2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => mux_1,
l1 => sel,
i1 => regout_1,
l0 => nsel,
i0 => a(1));
l1 : ms_y
PORT MAP (
vss => vss,
vdd => vdd,
t => regout_1,
l => ck,
i => s(1));
mux2 : mx2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => mux_2,
l1 => sel,
i1 => regout_2,
l0 => nsel,
i0 => a(2));
l2 : ms_y
PORT MAP (
vss => vss,
vdd => vdd,
t => regout_2,
l => ck,
i => s(2));
mux3 : mx2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => mux_3,
l1 => sel,
i1 => regout_3,
l0 => nsel,
i0 => a(3));
l3 : ms_y
PORT MAP (
vss => vss,
vdd => vdd,
t => regout_3,
l => ck,
i => s(3));
end VST;

111
alliance/share/tutorials/addaccu/genvect.c Normal file
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@ -0,0 +1,111 @@
#include <genpat.h>
#include <stdio.h>
/*#include <mut315.h> */
char *
inttostr (entier)
int entier;
{
char *str;
str = (char *) mbkalloc (32 * sizeof (char));
sprintf (str, "%d", entier);
return (str);
}
/*------------------------------*/
/* end of the description */
/*------------------------------*/
main ()
{
int i;
int j;
int numvect;
int CKcour;
int test;
numvect = 0;
test = 0;
CKcour = 0;
DEF_GENPAT ("genvect");
/* Declaration de l'interface */
DECLAR ("A", ":2", "X", IN, "3 downto 0");
DECLAR ("B", ":2", "X", IN, "3 downto 0");
DECLAR ("SEL", ":2", "B", IN, "");
DECLAR ("s", ":2", "X", OUT, "3 downto 0");
DECLAR ("CK", ":2", "B", IN, "");
DECLAR ("vdd", ":2", "B", IN, "");
DECLAR ("vss", ":2", "B", IN, "");
LABEL ("additionneur");
AFFECT ("0", "SEL", "0b0");
AFFECT ("0", "A", "0X0");
AFFECT ("0", "vdd", "0b1");
AFFECT ("0", "vss", "0b0");
AFFECT ("0", "B", "0X0");
/* Boucle d'affectation des vecteurs */
while (numvect < 768)
{
if (test == 1)
{
AFFECT (inttostr (numvect), "A", inttostr (i));
AFFECT (inttostr (numvect), "B", inttostr (j));
AFFECT (inttostr (numvect), "CK", "0b1");
CKcour = 1;
numvect++;
if (j == 16)
i++;
if (j == 16)
j = 0;
else
j++;
test = 0;
}
else
{
if (CKcour == 0 && test == 0)
test = 1;
AFFECT (inttostr (numvect), "CK", "0b0");
CKcour = 0;
numvect++;
}
}
i = 0;
j = 0;
AFFECT (inttostr (numvect), "SEL", "0b1");
/* Boucle d'affectation des vecteurs */
while (numvect < 1536)
{
if (test == 1)
{
AFFECT (inttostr (numvect), "A", inttostr (i));
AFFECT (inttostr (numvect), "B", inttostr (j));
AFFECT (inttostr (numvect), "CK", "0b1");
CKcour = 1;
numvect++;
if (j == 16)
i++;
if (j == 16)
j = 0;
else
j++;
test = 0;
}
else
{
if (CKcour == 0 && test == 0)
test = 1;
AFFECT (inttostr (numvect), "CK", "0b0");
numvect++;
CKcour = 0;
}
}
SAV_GENPAT ();
}

51
alliance/share/tutorials/addaccu/specifications.pat
View File

@ -1,51 +0,0 @@
-- description generated by Pat driver v104
-- date : Fri Sep 25 12:13:54 1998
-- sequence : addaccu
-- input / output list :
in vdde B;
in vsse B;
in vdd B;
in vss B;
in a (3 downto 0) B;
in b (3 downto 0) B;
in sel B;;
in ck B;;;
out s (3 downto 0) B;
begin
-- Pattern description :
-- vvvva b s c s
-- dsds e k
-- dsds l
-- ee
# a=0, b=3, sel=direct input, we expect value 3 on s
pat_1 : 1010000000110 0 ?0011;
# a=1, b=3, sel=direct input, we expect value 4 on s
pat_2 : 1010000100110 0 ?0100;
# a=7, b=3, sel=direct input, we expect value bin 1010 on s
pat_3 : 1010011100110 0 ?1010;
# a=7, b=3, sel=direct input, we set ck to 1, we still expect bin 1010 on s
pat_4 : 1010011100110 1 ?1010;
# when ck falls to 0, the computed value (7+3=bin 1010) is stored in accu
pat_5 : 1010011100110 0 ?1010;
# if we choose sel=accu output, we expect value bin 1010 + 4= bin 1110 on s
# even if a=1111
pat_6 : 1010111101001 0 ?1110;
# back to normal mode, 5+4=9
pat_7 : 1010010101000 0 ?1001;
end;