riscv
/
alliance
mirror of https://gitlab.lip6.fr/vlsi-eda/alliance.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Mise a jour du manuel.

This commit is contained in:
Gregoire Avot 1999-06-01 14:59:46 +00:00
parent e27b59751a
commit 0bd81b857a
1 changed files with 31 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

40
alliance/share/man/man1/lynx.1
View File

@ -1,6 +1,5 @@
.\" $Id: lynx.1,v 1.1 1999/05/31 17:30:14 alliance Exp $ .\" @(#)lynx 1.09 94/10/10 UPMC/MASI/CAO-VLSI " Ludovic Jacomme, Frederic Petrot
.\" @(#)lynx 1.09 94/10/10 UPMC/ASIM/LIP6/CAO-VLSI " Ludovic Jacomme, Frederic Petrot .TH LYNX 1 "October, 1st 1994" "Release 1.9" "ALLIANCE USER COMMANDS"
.TH LYNX 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
.SH NAME .SH NAME
lynx \- Hierarchical netlist extractor lynx \- Hierarchical netlist extractor
.SH SYNOPSIS .SH SYNOPSIS
@ -17,12 +16,27 @@ lynx \- Hierarchical netlist extractor
[ [
.I \-t .I \-t
] ]
[
.I \-ar
]
[
.I \-ac
]
.I input_name .I input_name
[ [
.I output_name .I output_name
] ]
.br .br
.so man1/alc_origin.1 .SH ORIGIN
This software belongs to the
.B ALLIANCE
CAD system from the
.br
CAO-VLSI team at MASI laboratory, University P. et M. Curie
.br
4, place Jussieu ; 75252 PARIS Cedex 05 ; FRANCE
.br
Fax: (33-1) 44.27.62.86 ; E-mail: cao-vlsi@masi.ibp.fr
.SH DESCRIPTION .SH DESCRIPTION
\fBLynx\fP is a hierarchical layout extractor. \fBLynx\fP is a hierarchical layout extractor.
It builds a netlist of interconnections from a symbolic layout view. It builds a netlist of interconnections from a symbolic layout view.
@ -42,7 +56,8 @@ variables.
.BR MBK_OUT_LO (1), .BR MBK_OUT_LO (1),
.BR RDS_TECHNO_NAME (1). .BR RDS_TECHNO_NAME (1).
.PP .PP
\fBLynx\fP computes capacitances attached to the signals. At the moment, \fBLynx\fP computes capacitances attached to the signals if the -ac option is
set. At the moment,
the value of these capacitances is computed for a typical one micron the value of these capacitances is computed for a typical one micron
technology, and cannot be changed by the user through a technology file. technology, and cannot be changed by the user through a technology file.
The extracted netlist can be simulated for performance evaluation. The extracted netlist can be simulated for performance evaluation.
@ -99,6 +114,13 @@ Generates a \fBcore\fP file representing the conflictuel net, when
the same signal, or when it finds two external connectors having the same signal, or when it finds two external connectors having
the same name but not internally connected to the same net, or when the same name but not internally connected to the same net, or when
it cannot correctly extract an L shaped transistor. it cannot correctly extract an L shaped transistor.
.TP
\-ac
Extract capacitance to ground on losig.
.TP
\-ar
Extract interconnect resistance and capacitance to ground. Value of
resistance foreach layer can be changed in the RDS file.
.SH EXAMPLES .SH EXAMPLES
.ie t \{\ .ie t \{\
.ft CR \} .ft CR \}
@ -137,7 +159,7 @@ prompt> lynx -t amd2901
.ft R .ft R
.RS .RS
Gives a logical netlist of the amd2901 chip at the transistor level. Gives a logical netlist of the amd2901 chip at the transistor level.
This is useful with \fByagle\fP(1), to retrieve logical equations from This is useful with \fBdesb\fP(1), to retrieve logical equations from
a layout. a layout.
.RE .RE
.SH SEE ALSO .SH SEE ALSO
@ -148,6 +170,6 @@ a layout.
.BR MBK_IN_PH (1), .BR MBK_IN_PH (1),
.BR catal (5), .BR catal (5),
.BR RDS_TECHNO_NAME (1). .BR RDS_TECHNO_NAME (1).
.SH DIAGNOSTICS
.so man1/alc_bug_report.1 Please report bugs, problems and suggestions to
.B cao-vlsi@masi.ibp.fr