From 0bd81b857a98f5fd31df8376cbb566f7a4087caa Mon Sep 17 00:00:00 2001
From: Gregoire Avot <alliance-cvs@asim.lip6.fr>
Date: Tue, 1 Jun 1999 14:59:46 +0000
Subject: [PATCH] Mise a jour du manuel.

---
 alliance/share/man/man1/lynx.1 | 40 ++++++++++++++++++++++++++--------
 1 file changed, 31 insertions(+), 9 deletions(-)

diff --git a/alliance/share/man/man1/lynx.1 b/alliance/share/man/man1/lynx.1
index 5d0b4b22..eb715c47 100644
--- a/alliance/share/man/man1/lynx.1
+++ b/alliance/share/man/man1/lynx.1
@@ -1,6 +1,5 @@
-.\"   $Id: lynx.1,v 1.1 1999/05/31 17:30:14 alliance Exp $
-.\" @(#)lynx 1.09 94/10/10 UPMC/ASIM/LIP6/CAO-VLSI " Ludovic Jacomme, Frederic Petrot
-.TH LYNX 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
+.\" @(#)lynx 1.09 94/10/10 UPMC/MASI/CAO-VLSI " Ludovic Jacomme, Frederic Petrot
+.TH LYNX 1 "October, 1st 1994" "Release 1.9" "ALLIANCE USER COMMANDS"
 .SH NAME
 lynx \- Hierarchical netlist extractor
 .SH SYNOPSIS
@@ -17,12 +16,27 @@ lynx \- Hierarchical netlist extractor
 [
 .I \-t
 ]
+[
+.I \-ar
+]
+[
+.I \-ac
+]
 .I input_name
 [
 .I output_name
 ]
 .br
-.so man1/alc_origin.1
+.SH ORIGIN
+This software belongs to the
+.B ALLIANCE
+CAD system from the
+.br
+CAO-VLSI team at MASI laboratory, University P. et M. Curie
+.br
+4, place Jussieu ; 75252 PARIS Cedex 05 ; FRANCE
+.br
+Fax: (33-1) 44.27.62.86 ; E-mail: cao-vlsi@masi.ibp.fr
 .SH DESCRIPTION
 \fBLynx\fP is a hierarchical layout extractor.
 It builds a netlist of interconnections from a symbolic layout view.
@@ -42,7 +56,8 @@ variables.
 .BR MBK_OUT_LO (1),
 .BR RDS_TECHNO_NAME (1).
 .PP
-\fBLynx\fP computes capacitances attached to the signals. At the moment,
+\fBLynx\fP computes capacitances attached to the signals if the -ac option is
+set. At the moment,
 the value of these capacitances is computed for a typical one micron
 technology, and cannot be changed by the user through a technology file.
 The extracted netlist can be simulated for performance evaluation.
@@ -99,6 +114,13 @@ Generates a \fBcore\fP file representing the conflictuel net, when
 the same signal, or when it finds two external connectors having 
 the same name but not internally connected to the same net, or when 
 it cannot correctly extract an L shaped transistor.
+.TP
+\-ac
+Extract capacitance to ground on losig.
+.TP
+\-ar
+Extract interconnect resistance and capacitance to ground. Value of
+resistance foreach layer can be changed in the RDS file.
 .SH EXAMPLES
 .ie t  \{\
 .ft CR \}
@@ -137,7 +159,7 @@ prompt> lynx -t amd2901
 .ft R
 .RS
 Gives a logical netlist of the amd2901 chip at the transistor level.
-This is useful with \fByagle\fP(1), to retrieve logical equations from
+This is useful with \fBdesb\fP(1), to retrieve logical equations from
 a layout.
 .RE
 .SH SEE ALSO
@@ -148,6 +170,6 @@ a layout.
 .BR MBK_IN_PH (1),
 .BR catal (5),
 .BR RDS_TECHNO_NAME (1).
-
-.so man1/alc_bug_report.1
-
+.SH DIAGNOSTICS
+Please report bugs, problems and suggestions to
+.B cao-vlsi@masi.ibp.fr