176 lines
4.5 KiB
Groff
176 lines
4.5 KiB
Groff
.\" @(#)lynx 1.09 94/10/10 UPMC/MASI/CAO-VLSI " Ludovic Jacomme, Frederic Petrot
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.TH LYNX 1 "October, 1st 1994" "Release 1.9" "ALLIANCE USER COMMANDS"
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.SH NAME
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lynx \- Hierarchical netlist extractor
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.SH SYNOPSIS
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.B lynx
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[
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.I \-v
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]
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[
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.I \-c
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]
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[
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.I \-f
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]
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[
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.I \-t
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]
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[
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.I \-ar
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]
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[
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.I \-ac
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]
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.I input_name
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[
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.I output_name
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]
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.br
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.SH ORIGIN
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This software belongs to the
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.B ALLIANCE
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CAD system from the
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.br
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CAO-VLSI team at MASI laboratory, University P. et M. Curie
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.br
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4, place Jussieu ; 75252 PARIS Cedex 05 ; FRANCE
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.br
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Fax: (33-1) 44.27.62.86 ; E-mail: cao-vlsi@masi.ibp.fr
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.SH DESCRIPTION
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\fBLynx\fP is a hierarchical layout extractor.
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It builds a netlist of interconnections from a symbolic layout view.
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The \fIinput\fP argument is the name of the symbolic layout cell to
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be extracted, using as input format the one selected by the
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\fBMBK_IN_PH\fP(1) environment variable.
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If \fIoutput\fP is present, the resulting netlist will be given this name.
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If no \fIoutput\fP is given, then \fIinput\fP will also be the generated
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netlist name.
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The output format is specified by the \fBMBK_OUT_LO\fP(1) environment variable.
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.br
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As most of the Alliance cad tools, \fBlynx\fP uses \fBmbk\fP(1) environment
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variables.
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.BR MBK_CATA_LIB (1),
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.BR MBK_WORK_LIB (1),
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.BR MBK_IN_PH (1),
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.BR MBK_OUT_LO (1),
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.BR RDS_TECHNO_NAME (1).
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.PP
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\fBLynx\fP computes capacitances attached to the signals if the -ac option is
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set. At the moment,
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the value of these capacitances is computed for a typical one micron
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technology, and cannot be changed by the user through a technology file.
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The extracted netlist can be simulated for performance evaluation.
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.br
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The typical capacitances are given below in 10e-18 farad / lamda^2 :
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.TP 20
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POLY
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100
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.TP 20
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ALU1
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50
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.TP 20
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ALU2
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25
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.SH OPTIONS
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\fBLynx\fP checks the two basic \fBALLIANCE\fP rules regarding connector names:
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.br
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.RS
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If two physical connectors are connected to the same net, they must have
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the same name.
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.br
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If two physical connectors have the same name, they must be internally
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connected to the same net.
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.RE
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.br
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As a result only one logical connector will appear in the netlist.
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A fatal error occurs if one of those two rules is violated ( even for power
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and ground connectors )
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When no options are specified, the current hierarchical level is extracted.
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The resulting netlist is the list of interconnections of the current
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layout hierarchy level.
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Three options are available to change \fBlynx\fP behaviour :
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.TP
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\-t
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Notifies a transistor level extraction, the symbolic layout cell is flattened to
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transistor layout before extraction.
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.TP
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\-f
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The symbolic layout cell is flattened to the catalog level before extraction.
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Use "man catal" for detail on the catalog file.
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If the catalog is empty, or doesn't exist, the netlist is an interconection of
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transistors, if it isn't, the netlist is an interconection of gates or blocks
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whose names are defined in the catalog.
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.TP
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\-v
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Verbose mode on.
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Each step of the extraction is displayed on the standard output,
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along with some statistics.
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.TP
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\-c
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Generates a \fBcore\fP file representing the conflictuel net, when
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\fBlynx\fP detects two external connectors with different names on
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the same signal, or when it finds two external connectors having
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the same name but not internally connected to the same net, or when
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it cannot correctly extract an L shaped transistor.
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.TP
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\-ac
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Extract capacitance to ground on losig.
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.TP
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\-ar
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Extract interconnect resistance and capacitance to ground. Value of
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resistance foreach layer can be changed in the RDS file.
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.SH EXAMPLES
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.ie t \{\
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.ft CR \}
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.el \fB
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prompt> lynx -v amd2901
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.ft R
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.RS
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Gives a logical netlist of the chip amd2901, for one hierarchical
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level, using verbose mode.
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This would be typically used to verify the work of the \fBring\fP(1)
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router, in conjunction with \fBlvx\fP on the specificated netlist and
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the extracted one.
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.RE
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.ie t \{\
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.ft CR \}
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.el \fB
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.nf
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prompt> cat $MBK_WORK_LIB/$MBK_CATAL_NAME
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a2_y
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a2p_y
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.
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.
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prompt> lynx -f amd2901
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.fi
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.ft R
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.RS
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Gives a logical netlist of the chip amd2901, after a flatten operation stopping
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on the cells specified in the catalog ( the standard cell library in our case ).
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.RE
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.ie t \{\
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.ft CR \}
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.el \fB
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.nf
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prompt> lynx -t amd2901
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.fi
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.ft R
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.RS
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Gives a logical netlist of the amd2901 chip at the transistor level.
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This is useful with \fBdesb\fP(1), to retrieve logical equations from
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a layout.
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.RE
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.SH SEE ALSO
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.BR al (1),
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.BR MBK_CATA_LIB (1),
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.BR MBK_WORK_LIB (1),
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.BR MBK_CATAL_NAME (1),
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.BR MBK_IN_PH (1),
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.BR catal (5),
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.BR RDS_TECHNO_NAME (1).
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.SH DIAGNOSTICS
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Please report bugs, problems and suggestions to
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.B cao-vlsi@masi.ibp.fr
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