romangauchi 568de2497b [SOFA] fix typos in the 'generate_testbench.openfpga' script causing the unknown 'write_verilog_testbench' command error'		2022-01-31 11:36:42 -07:00
..
arch	[Flow] Updated CHD design	2021-04-06 00:29:19 -06:00
config	[Repo] Adding skywater PDK as submodule	2021-04-06 08:58:07 -06:00
micro_benchmark	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
sc_verilog	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
BENCHMARK	[Flow] Updated CHD design	2021-04-06 00:29:19 -06:00
design_variables.yml	[Flow] Updated CHD design	2021-04-06 00:29:19 -06:00
generate_fabric.openfpga	[Flow] Updated CHD design	2021-04-06 00:29:19 -06:00
generate_testbench.openfpga	[SOFA] fix typos in the 'generate_testbench.openfpga' script causing the unknown 'write_verilog_testbench' command error'	2022-01-31 11:36:42 -07:00
process_top_def.sh	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
user_project_wrapper_empty.def	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00
user_project_wrapper_template.def	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00