8 Commits

Author	SHA1	Message	Date
romangauchi	568de2497b	[SOFA] fix typos in the 'generate_testbench.openfpga' script causing the unknown 'write_verilog_testbench' command error'	2022-01-31 11:36:42 -07:00
tangxifan	d15e7db1be	[Script] Update openfpga shell script due to the deprecation of 'write_verilog_testbench'	2021-06-09 19:40:41 -06:00
Ganesh Gore	1b2a14886b	[Repo] Adding skywater PDK as submodule	2021-04-06 08:58:07 -06:00
Ganesh Gore	da95b57b6b	[Flow] Updated CHD design	2021-04-06 00:29:19 -06:00
Ganesh Gore	3a472b0db0	[Flow] Adding Makefile for running task	2021-04-03 17:54:59 -06:00
Lalit Sharma	51f11ee630	Replacing deprecated tile_port syntax	2021-01-12 21:33:53 -08:00
Ganesh Gore	562641ed4d	[SOFA-CHD] Bugfix to fix floating cin net	2020-12-22 00:23:12 -07:00
Ganesh Gore	9284bbf8fa	[SOFA_CHD] Added OpenFPGA taks and verilog netlist	2020-12-09 00:49:00 -07:00