Ganesh Gore 0cc5b492d2 [Cleanup] Removed/Ignored testbench files from generated source		2020-12-02 12:03:24 -07:00
..
FPGA1212_FLAT_HD_SKY_Verilog	[Cleanup] Removed/Ignored testbench files from generated source	2020-12-02 12:03:24 -07:00
FPGA1212_FLAT_HD_SKY_task	[FPGA1212_V1] Updated design + Added buffer on IO_EN net + Tie Off floating module inputs + Complete DRC/Timing closed	2020-11-29 10:24:03 -07:00
Verification	Added FPGA12x12 with CocoTB tests	2020-11-21 16:07:09 -07:00
fpga_top	[FPGA1212_v1] Added top-level pnr screenshots	2020-11-29 10:59:15 -07:00
modules	[FPGA1212_v1] Module level results	2020-11-29 11:02:17 -07:00
config.sh	Added FPGA12x12 with CocoTB tests	2020-11-21 16:07:09 -07:00