7 Commits

Author	SHA1	Message	Date
Ganesh Gore	0cc5b492d2	[Cleanup] Removed/Ignored testbench files from generated source	2020-12-02 12:03:24 -07:00
Ganesh Gore	20dc203b31	[FPGA1212_v1] Module level results	2020-11-29 11:02:17 -07:00
Ganesh Gore	225feaef3c	[FPGA1212_v1] Added top-level pnr screenshots	2020-11-29 10:59:15 -07:00
Ganesh Gore	7db7c240e3	[FPGA1212_V1] Updated design + Added buffer on IO_EN net + Tie Off floating module inputs + Complete DRC/Timing closed	2020-11-29 10:24:03 -07:00
Ganesh Gore	66d09da857	[FPGA1212_v1] Updated the PostPnR Netlist and PnR Files	2020-11-27 22:11:51 -07:00
Ganesh Gore	ce4a6f72f5	[FPGA1212_v1] Updated the task and PrePNR Verilog netlist	2020-11-27 22:08:16 -07:00
Ganesh Gore	c54cdcd3ef	Added FPGA12x12 with CocoTB tests	2020-11-21 16:07:09 -07:00