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tangxifan a2b42c2e5f [Script] Now use variables to redirect the output directory of Verilog/SDC files 2020-10-09 16:00:41 -06:00
ARCH [Architecture] Rename architecture file 2020-10-09 15:04:21 -06:00
SCRIPT [Script] Now use variables to redirect the output directory of Verilog/SDC files 2020-10-09 16:00:41 -06:00
LICENSE Initial commit 2020-10-09 14:16:36 -06:00
README.md Initial commit 2020-10-09 14:16:36 -06:00

README.md

skywater-openfpga

FPGA tape-outs using the open-source Skywater 130nm PDK and OpenFPGA