Lalit Sharma 9b3cd1f5ff Updating task template file by calling synth_quicklogic inside yosys		2021-01-06 23:19:20 -08:00
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openfpga_shell_script	Disable generation of formal verification testbench due to disk space	2021-01-05 19:44:08 -08:00
openfpga_simulation_setting	[Script] Try auto number of simulation clock cycles	2020-12-02 19:33:28 -07:00
skywater_openfpga_task	Updating task template file by calling synth_quicklogic inside yosys	2021-01-06 23:19:20 -08:00
magic_drc_to_rdb.py	[Action] Updated action script for local run	2020-12-14 12:08:16 -07:00
merge_caravel_klayout.py	[Action] More cleanup while precheck	2020-12-20 17:04:56 -07:00
merge_fpga_top.tcl	[BugFix] After Integration with mpw-one-b	2020-12-17 09:29:54 -07:00
repo_setup.py	[Script] Now batch task run will error out in the first failed task	2020-11-26 18:30:01 -07:00