Lalit Sharma 9b3cd1f5ff Updating task template file by calling synth_quicklogic inside yosys		2021-01-06 23:19:20 -08:00
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k4_N8_caravel_cc_fdhd_2x2	[Script] Update openfpga task-run script to use the adhoc simulation settings tuned for Caravel SoC	2020-11-17 15:03:10 -07:00
k4_N8_caravel_cc_fdhd_12x12	[Script] Add and2_or2 benchmark to the testbench generation script for 12x12 HD FPGA	2020-11-22 13:34:53 -07:00
k4_N8_reset_softadder_caravel_cc_customhd_12x12	[Script] Add task run for custom cell FPGA architectures	2020-12-01 20:22:16 -07:00
k4_N8_reset_softadder_caravel_cc_fdhd_12x12	[Script] Increase routing chan width from 40 to 60 for version 1.2	2020-12-01 10:17:47 -07:00
k4_N8_reset_softadder_caravel_cc_fdhd_32x32	Updating task template file by calling synth_quicklogic inside yosys	2021-01-06 23:19:20 -08:00