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SOFA/FPGA1212_SOFA_CHD_PNR
History
tangxifan d15e7db1be [Script] Update openfpga shell script due to the deprecation of 'write_verilog_testbench' 2021-06-09 19:40:41 -06:00
..
FPGA1212_QLSOFA_CHD_Verilog [SOFA-CHD] Bugfix to fix floating cin net 2020-12-22 00:23:12 -07:00
FPGA1212_SOFA_CHD_Verilog [SOFA-CHD] Bugfix to fix floating cin net 2020-12-22 00:23:12 -07:00
FPGA1212_SOFA_CHD_task [Script] Update openfpga shell script due to the deprecation of 'write_verilog_testbench' 2021-06-09 19:40:41 -06:00
Verification [SOFA-CHD] Updated design with mux-primitive bug fixed - Calibre DRC pending 2020-12-14 00:34:42 -07:00
fpga_top [DRCFix] Fixed filler cell boundary SOFA CHD 2021-02-10 23:29:18 -07:00
modules [Cleanup] Converted .spef to .spef.gz 2020-12-20 02:10:51 -07:00
Makefile [Repo] Adding skywater PDK as submodule 2021-04-06 08:58:07 -06:00
README.md [SOFA-CHD] Updated design with mux-primitive bug fixed - Calibre DRC pending 2020-12-14 00:34:42 -07:00
config.sh [SOFA-CHD] Bugfix to fix floating cin net 2020-12-22 00:23:12 -07:00

README.md

FPGA1212_SOFA_CHD_PNR

https://skywater-openfpga.readthedocs.io/en/latest/datasheet/qlsofa_hd/