Tarachand Pagarani 353207693a 1. added 32x32 fabric key\n 2. disable shift register packing due to routability failure\n 3. Disable IIR design due to routabiity failure in shift register mode\n 4. revert changes to QLSOFA architecture		2020-12-26 23:29:13 -08:00
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openfpga_shell_script	incoporated changes based on feedback from xifan	2020-12-24 23:05:47 -08:00
openfpga_simulation_setting	[Script] Try auto number of simulation clock cycles	2020-12-02 19:33:28 -07:00
skywater_openfpga_task	1. added 32x32 fabric key\n 2. disable shift register packing due to routability failure\n 3. Disable IIR design due to routabiity failure in shift register mode\n 4. revert changes to QLSOFA architecture	2020-12-26 23:29:13 -08:00
magic_drc_to_rdb.py	[Action] Updated action script for local run	2020-12-14 12:08:16 -07:00
merge_caravel_klayout.py	[Actions] Merged Caravel with Klayout	2020-12-08 13:33:17 -07:00
merge_fpga_top.tcl	[Action] Integrated MPW prechecker	2020-12-06 01:41:58 -07:00
repo_setup.py	[Script] Now batch task run will error out in the first failed task	2020-11-26 18:30:01 -07:00