SOFA/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC
Ganesh Gore 452af85e98 [Cleanup] Removed/Ignored testbench files from generated source 2020-12-06 01:40:21 -07:00
..
lb Change configuration flipflop + Fixed configuration chain 2020-11-09 19:17:15 -07:00
routing Change configuration flipflop + Fixed configuration chain 2020-11-09 19:17:15 -07:00
sub_module Change configuration flipflop + Fixed configuration chain 2020-11-09 19:17:15 -07:00
InstancesMap.txt Updated design with new architecure and merged grid_io 2020-11-06 22:35:31 -07:00
define_simulation.v [Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-26 23:59:20 -06:00
fabric_netlists.v Change configuration flipflop + Fixed configuration chain 2020-11-09 19:17:15 -07:00
fpga_core.v Fixed scan-chain connections 2020-11-08 01:06:13 -07:00
fpga_defines.v [Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-26 23:59:20 -06:00
fpga_top.v Updated design with new architecure and merged grid_io 2020-11-06 22:35:31 -07:00
top_include_netlists.v [Design] Added FPGA22 design with SKY130_FD_SC_HD 2020-10-26 23:59:20 -06:00
top_top_formal_verification.v Change configuration flipflop + Fixed configuration chain 2020-11-09 19:17:15 -07:00