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SOFA/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog
History
Ganesh Gore abea1a8aa0 Changed fpga_top to fpga_core 2023-03-17 10:23:05 -06:00
..
SRC Changed fpga_top to fpga_core 2023-03-17 10:23:05 -06:00
SRCLint Added global signal feedthrough 2023-03-01 20:53:28 -07:00
SRCOriginal Added global signal feedthrough 2023-03-01 20:53:28 -07:00
SRCSynth Added global signal feedthrough 2023-03-01 20:53:28 -07:00
XML Updated port names 2023-03-01 15:59:04 -07:00
openfpgashell.log Added scan chain ports 2023-03-17 10:20:14 -06:00