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Updated port names

This commit is contained in:
Ganesh Gore 2023-03-01 15:59:04 -07:00
parent df1bdf01ea
commit 8d120b23b6
159 changed files with 6323 additions and 6375 deletions
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37
SOFA_A/CommonFiles/restructure_fabric_sofa_a.py
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@ -218,6 +218,15 @@ def main():
shapes[module]["PLACEMENT"][1] += 1
fpga.create_placement()
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Feedthrough generation
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
instance_map = [[0 for _ in range(FPGA_HEIGHT + 1)]
for _ in range(FPGA_WIDTH + 1)]
for inst in fpga.top_module.get_instances():
_, x, _, y, _ = inst.name.rsplit("_", 4)
instance_map[int(x)][int(y)] = inst.name
# create_global_feedthrough(fpga, "reset", instance_map)
filename = SVG_DIR + f"{PROJ_NAME}_pre_tile_floorplan.svg"
save_tiling_floorplan(fpga, filename, STYLE_SHEET=STYLE_SHEET)
@ -234,6 +243,34 @@ def main():
logger.info("Saved floorplan in %s", filename)
# save_netlist_outline(fpga)
def create_global_feedthrough(
fpga: OpenFPGA, signal, instance_map, down_port=None, top_cable=None
):
"""
This creates global feedthroughs
"""
logger.debug("create_global_feedthrough [%s]", signal)
with open(PICKLE_DIR + f"{signal}_pattern.pickle", "rb") as fp:
sig_conn_patt: ConnectPointList = pickle.load(fp)
sig_conn_patt.get_top_instance_name = lambda x, y: instance_map[x][y]
signal_cable = next(fpga.top_module.get_cables(signal), None)
if not signal_cable:
signal_cable = fpga.top_module.create_cable(signal, wires=1)
else:
for pin in list(signal_cable.wires[0].pins):
if isinstance(pin, sdn.OuterPin):
signal_cable.wires[0].disconnect_pin(pin)
sig_conn_patt.create_ft_ports(fpga.netlist, signal, signal_cable)
sig_conn_patt.create_ft_connection(
fpga.netlist,
signal_cable,
down_port=down_port,
top_cable=top_cable or signal_cable,
)
rpt_file = f"{RELEASE_DIR}/rpts/pre_pnr/{signal}_ports.txt"
sig_conn_patt.print_port_stat(fpga.netlist, filename=rpt_file)
def save_tiling_floorplan(fpga: OpenFPGA, filename: str, STYLE_SHEET=None):
"""
Save currnt tiling strategy to SVG file

2
SOFA_A/FPGA88_SOFA_A/.spydrnet
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@ -1 +1 @@
spydrnet_physical
spydrnet_physical

18
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/arch/openfpga_arch.xml
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@ -154,7 +154,7 @@
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="DI" lib_name="SCD" size="1"/>
<port type="input" prefix="Test_en" lib_name="SCE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="scan_enable" lib_name="SCE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="reset" lib_name="RESET_B" size="1" default_val="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="false" default_val="0" />
@ -182,16 +182,16 @@
<port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
<port type="input" prefix="pReset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_prog="true" is_reset="true"/>
<port type="input" prefix="prog_reset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_prog="true" is_reset="true"/>
</circuit_model>
<circuit_model type="iopad" name="EMBEDDED_IO_HD" prefix="EMBEDDED_IO_HD" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v">
<circuit_model type="iopad" name="io" prefix="io" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="input" prefix="SOC_IN" lib_name="SOC_IN" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="SOC_OUT" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="SOC_DIR" lib_name="SOC_DIR" size="1" is_global="true" is_io="true"/>
<port type="input" prefix="IO_ISOL_N" lib_name="IO_ISOL_N" size="1" is_global="true" default_val="1"/>
<port type="input" prefix="soc_in" lib_name="SOC_IN" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="soc_out" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="soc_dir" lib_name="SOC_DIR" size="1" is_global="true" is_io="true"/>
<port type="input" prefix="isol_n" lib_name="IO_ISOL_N" size="1" is_global="true" default_val="1"/>
<port type="output" prefix="inpad" lib_name="FPGA_IN" size="1"/>
<port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
<port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfrtp_1" default_val="1"/>
@ -232,7 +232,7 @@
<global_port name="clk" is_clock="true" default_val="0">
<tile name="clb" port="clk" x="-1" y="-1"/>
</global_port>
<global_port name="Reset" is_reset="true" default_val="1">
<global_port name="reset" is_reset="true" default_val="1">
<tile name="clb" port="reset" x="-1" y="-1"/>
</global_port>
</tile_annotations>
@ -240,7 +240,7 @@
<!-- physical pb_type binding in complex block IO -->
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
<!-- IMPORTANT: must set unused I/Os to operating in INPUT mode !!! -->
<pb_type name="io[physical].iopad" circuit_model_name="EMBEDDED_IO_HD" mode_bits="1"/>
<pb_type name="io[physical].iopad" circuit_model_name="io" mode_bits="1"/>
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO -->

3
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fabric_netlists.v
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@ -1,6 +1,4 @@
`include "./SRC/fpga_top.v"
`include "./SRC/submodules/EMBEDDED_IO_HD.v"
`include "./SRC/submodules/EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.v"
`include "./SRC/submodules/cbx_1__0_.v"
`include "./SRC/submodules/cbx_1__0__old.v"
`include "./SRC/submodules/cbx_1__1_.v"
@ -22,6 +20,7 @@
`include "./SRC/submodules/grid_io_left_left.v"
`include "./SRC/submodules/grid_io_right_right.v"
`include "./SRC/submodules/grid_io_top_top.v"
`include "./SRC/submodules/io_sky130_fd_sc_hd__dfrtp_1_mem.v"
`include "./SRC/submodules/logical_tile_clb_mode_clb_.v"
`include "./SRC/submodules/logical_tile_clb_mode_default__fle.v"
`include "./SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric.v"

714
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fpga_top.v
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File diff suppressed because it is too large Load Diff

31
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/EMBEDDED_IO_HD.v
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@ -1,31 +0,0 @@
//Generated from netlist by SpyDrNet
//netlist name: FPGA88_SOFA_A
module EMBEDDED_IO_HD
(
FPGA_DIR,
FPGA_OUT,
IO_ISOL_N,
SOC_IN,
FPGA_IN,
SOC_DIR,
SOC_OUT
);
input FPGA_DIR;
input FPGA_OUT;
input IO_ISOL_N;
input SOC_IN;
output FPGA_IN;
output SOC_DIR;
output SOC_OUT;
wire FPGA_DIR;
wire FPGA_IN;
wire FPGA_OUT;
wire IO_ISOL_N;
wire SOC_DIR;
wire SOC_IN;
wire SOC_OUT;
endmodule

42
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__0_.v
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@ -2,46 +2,45 @@
//netlist name: FPGA88_SOFA_A
module cbx_1__0_
(
IO_ISOL_N,
ccff_head,
ccff_head_0,
chanx_left_in,
chanx_right_in,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
pReset,
gfpga_pad_io_soc_in,
isol_n,
prog_clk,
prog_reset,
ccff_tail,
ccff_tail_0,
chanx_left_out,
chanx_right_out,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out,
top_width_0_height_0_subtile_0__pin_inpad_0_,
top_width_0_height_0_subtile_1__pin_inpad_0_,
top_width_0_height_0_subtile_2__pin_inpad_0_,
top_width_0_height_0_subtile_3__pin_inpad_0_
);
input IO_ISOL_N;
input ccff_head;
input ccff_head_0;
input [29:0]chanx_left_in;
input [29:0]chanx_right_in;
input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
input pReset;
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input prog_clk;
input prog_reset;
output ccff_tail;
output ccff_tail_0;
output [29:0]chanx_left_out;
output [29:0]chanx_right_out;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [3:0]gfpga_pad_io_soc_dir;
output [3:0]gfpga_pad_io_soc_out;
output top_width_0_height_0_subtile_0__pin_inpad_0_;
output top_width_0_height_0_subtile_1__pin_inpad_0_;
output top_width_0_height_0_subtile_2__pin_inpad_0_;
output top_width_0_height_0_subtile_3__pin_inpad_0_;
wire IO_ISOL_N;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;
wire bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_;
wire bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_;
@ -54,11 +53,12 @@ module cbx_1__0_
wire [29:0]chanx_left_out;
wire [29:0]chanx_right_in;
wire [29:0]chanx_right_out;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire pReset;
wire [3:0]gfpga_pad_io_soc_dir;
wire [3:0]gfpga_pad_io_soc_in;
wire [3:0]gfpga_pad_io_soc_out;
wire isol_n;
wire prog_clk;
wire prog_reset;
wire top_width_0_height_0_subtile_0__pin_inpad_0_;
wire top_width_0_height_0_subtile_1__pin_inpad_0_;
wire top_width_0_height_0_subtile_2__pin_inpad_0_;
@ -69,8 +69,8 @@ module cbx_1__0_
.ccff_head(ccff_head_0),
.chanx_left_in(chanx_left_in),
.chanx_right_in(chanx_right_in),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@ -81,18 +81,18 @@ module cbx_1__0_
);
grid_io_bottom_bottom grid_io_bottom_bottom_8__0_
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(ccff_head),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.pReset(pReset),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.top_width_0_height_0_subtile_0__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
.top_width_0_height_0_subtile_1__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
.top_width_0_height_0_subtile_2__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
.top_width_0_height_0_subtile_3__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_tail(ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
.top_width_0_height_0_subtile_0__pin_inpad_0_(top_width_0_height_0_subtile_0__pin_inpad_0_),
.top_width_0_height_0_subtile_1__pin_inpad_0_(top_width_0_height_0_subtile_1__pin_inpad_0_),
.top_width_0_height_0_subtile_2__pin_inpad_0_(top_width_0_height_0_subtile_2__pin_inpad_0_),

14
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__0__old.v
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@ -5,8 +5,8 @@ module cbx_1__0__old
ccff_head,
chanx_left_in,
chanx_right_in,
pReset,
prog_clk,
prog_reset,
bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_,
@ -19,8 +19,8 @@ module cbx_1__0__old
input ccff_head;
input [0:29]chanx_left_in;
input [0:29]chanx_right_in;
input pReset;
input prog_clk;
input prog_reset;
output bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;
output bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_;
output bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_;
@ -50,8 +50,8 @@ module cbx_1__0__old
wire mux_tree_tapbuf_size12_mem_0_ccff_tail;
wire mux_tree_tapbuf_size12_mem_1_ccff_tail;
wire mux_tree_tapbuf_size12_mem_2_ccff_tail;
wire pReset;
wire prog_clk;
wire prog_reset;
assign chanx_right_out[0] = chanx_left_in[0];
assign chanx_right_out[1] = chanx_left_in[1];
@ -116,32 +116,32 @@ assign chanx_right_out[9] = chanx_left_in[9];
mux_tree_tapbuf_size12_mem mem_top_ipin_0
(
.ccff_head(ccff_head),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_0_sram)
);
mux_tree_tapbuf_size12_mem mem_top_ipin_1
(
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_1_sram)
);
mux_tree_tapbuf_size12_mem mem_top_ipin_2
(
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_2_sram)
);
mux_tree_tapbuf_size12_mem mem_top_ipin_3
(
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size12_3_sram)
);

38
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__1_.v
View File

@ -5,8 +5,8 @@ module cbx_1__1_
ccff_head,
chanx_left_in,
chanx_right_in,
pReset,
prog_clk,
prog_reset,
bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_,
@ -31,8 +31,8 @@ module cbx_1__1_
input ccff_head;
input [0:29]chanx_left_in;
input [0:29]chanx_right_in;
input pReset;
input prog_clk;
input prog_reset;
output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
@ -122,8 +122,8 @@ module cbx_1__1_
wire mux_tree_tapbuf_size12_mem_5_ccff_tail;
wire mux_tree_tapbuf_size12_mem_6_ccff_tail;
wire mux_tree_tapbuf_size12_mem_7_ccff_tail;
wire pReset;
wire prog_clk;
wire prog_reset;
assign chanx_right_out[0] = chanx_left_in[0];
assign chanx_right_out[1] = chanx_left_in[1];
@ -188,128 +188,128 @@ assign chanx_right_out[9] = chanx_left_in[9];
mux_tree_tapbuf_size12_mem mem_top_ipin_0
(
.ccff_head(ccff_head),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_0_sram)
);
mux_tree_tapbuf_size10_mem mem_top_ipin_1
(
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_0_sram)
);
mux_tree_tapbuf_size12_mem mem_top_ipin_10
(
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_5_sram)
);
mux_tree_tapbuf_size10_mem mem_top_ipin_11
(
.ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_5_sram)
);
mux_tree_tapbuf_size12_mem mem_top_ipin_12
(
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_6_sram)
);
mux_tree_tapbuf_size10_mem mem_top_ipin_13
(
.ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_6_sram)
);
mux_tree_tapbuf_size12_mem mem_top_ipin_14
(
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_7_sram)
);
mux_tree_tapbuf_size10_mem mem_top_ipin_15
(
.ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size10_7_sram)
);
mux_tree_tapbuf_size12_mem mem_top_ipin_2
(
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_1_sram)
);
mux_tree_tapbuf_size10_mem mem_top_ipin_3
(
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_1_sram)
);
mux_tree_tapbuf_size12_mem mem_top_ipin_4
(
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_2_sram)
);
mux_tree_tapbuf_size10_mem mem_top_ipin_5
(
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_2_sram)
);
mux_tree_tapbuf_size12_mem mem_top_ipin_6
(
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_3_sram)
);
mux_tree_tapbuf_size10_mem mem_top_ipin_7
(
.ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_3_sram)
);
mux_tree_tapbuf_size12_mem mem_top_ipin_8
(
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_4_sram)
);
mux_tree_tapbuf_size10_mem mem_top_ipin_9
(
.ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_4_sram)
);

42
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__8_.v
View File

@ -2,13 +2,13 @@
//netlist name: FPGA88_SOFA_A
module cbx_1__8_
(
IO_ISOL_N,
ccff_head_0,
chanx_left_in,
chanx_right_in,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
pReset,
gfpga_pad_io_soc_in,
isol_n,
prog_clk,
prog_reset,
bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_,
@ -32,17 +32,17 @@ module cbx_1__8_
ccff_tail,
chanx_left_out,
chanx_right_out,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out
);
input IO_ISOL_N;
input ccff_head_0;
input [29:0]chanx_left_in;
input [29:0]chanx_right_in;
input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
input pReset;
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input prog_clk;
input prog_reset;
output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
@ -66,10 +66,9 @@ module cbx_1__8_
output ccff_tail;
output [29:0]chanx_left_out;
output [29:0]chanx_right_out;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [3:0]gfpga_pad_io_soc_dir;
output [3:0]gfpga_pad_io_soc_out;
wire IO_ISOL_N;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
@ -97,11 +96,12 @@ module cbx_1__8_
wire [29:0]chanx_left_out;
wire [29:0]chanx_right_in;
wire [29:0]chanx_right_out;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire pReset;
wire [3:0]gfpga_pad_io_soc_dir;
wire [3:0]gfpga_pad_io_soc_in;
wire [3:0]gfpga_pad_io_soc_out;
wire isol_n;
wire prog_clk;
wire prog_reset;
wire top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_;
wire top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_;
wire top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_;
@ -112,8 +112,8 @@ module cbx_1__8_
.ccff_head(ccff_head_0),
.chanx_left_in(chanx_left_in),
.chanx_right_in(chanx_right_in),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@ -140,22 +140,22 @@ module cbx_1__8_
);
grid_io_top_top grid_io_top_top_1__9_
(
.IO_ISOL_N(IO_ISOL_N),
.bottom_width_0_height_0_subtile_0__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
.bottom_width_0_height_0_subtile_1__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
.bottom_width_0_height_0_subtile_2__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
.bottom_width_0_height_0_subtile_3__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(ccff_tail_0),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.pReset(pReset),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.bottom_width_0_height_0_subtile_0__pin_inpad_0_(bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_width_0_height_0_subtile_1__pin_inpad_0_(bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_width_0_height_0_subtile_2__pin_inpad_0_(bottom_width_0_height_0_subtile_2__pin_inpad_0_),
.bottom_width_0_height_0_subtile_3__pin_inpad_0_(bottom_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_tail(ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT)
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out)
);
endmodule

46
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__8__old.v
View File

@ -5,8 +5,8 @@ module cbx_1__8__old
ccff_head,
chanx_left_in,
chanx_right_in,
pReset,
prog_clk,
prog_reset,
bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_,
@ -35,8 +35,8 @@ module cbx_1__8__old
input ccff_head;
input [0:29]chanx_left_in;
input [0:29]chanx_right_in;
input pReset;
input prog_clk;
input prog_reset;
output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
@ -142,8 +142,8 @@ module cbx_1__8__old
wire mux_tree_tapbuf_size12_mem_7_ccff_tail;
wire mux_tree_tapbuf_size12_mem_8_ccff_tail;
wire mux_tree_tapbuf_size12_mem_9_ccff_tail;
wire pReset;
wire prog_clk;
wire prog_reset;
wire top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_;
wire top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_;
wire top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_;
@ -212,160 +212,160 @@ assign chanx_right_out[9] = chanx_left_in[9];
mux_tree_tapbuf_size12_mem mem_bottom_ipin_0
(
.ccff_head(ccff_head),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_0_sram)
);
mux_tree_tapbuf_size12_mem mem_bottom_ipin_1
(
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_1_sram)
);
mux_tree_tapbuf_size12_mem mem_bottom_ipin_2
(
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_2_sram)
);
mux_tree_tapbuf_size12_mem mem_bottom_ipin_3
(
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_3_sram)
);
mux_tree_tapbuf_size12_mem mem_top_ipin_0
(
.ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_4_sram)
);
mux_tree_tapbuf_size10_mem mem_top_ipin_1
(
.ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_0_sram)
);
mux_tree_tapbuf_size12_mem mem_top_ipin_10
(
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_9_sram)
);
mux_tree_tapbuf_size10_mem mem_top_ipin_11
(
.ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_5_sram)
);
mux_tree_tapbuf_size12_mem mem_top_ipin_12
(
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_10_sram)
);
mux_tree_tapbuf_size10_mem mem_top_ipin_13
(
.ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_6_sram)
);
mux_tree_tapbuf_size12_mem mem_top_ipin_14
(
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_11_sram)
);
mux_tree_tapbuf_size10_mem mem_top_ipin_15
(
.ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size10_7_sram)
);
mux_tree_tapbuf_size12_mem mem_top_ipin_2
(
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_5_sram)
);
mux_tree_tapbuf_size10_mem mem_top_ipin_3
(
.ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_1_sram)
);
mux_tree_tapbuf_size12_mem mem_top_ipin_4
(
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_6_sram)
);
mux_tree_tapbuf_size10_mem mem_top_ipin_5
(
.ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_2_sram)
);
mux_tree_tapbuf_size12_mem mem_top_ipin_6
(
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_7_sram)
);
mux_tree_tapbuf_size10_mem mem_top_ipin_7
(
.ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_3_sram)
);
mux_tree_tapbuf_size12_mem mem_top_ipin_8
(
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_8_sram)
);
mux_tree_tapbuf_size10_mem mem_top_ipin_9
(
.ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_4_sram)
);

42
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_0__1_.v
View File

@ -2,42 +2,41 @@
//netlist name: FPGA88_SOFA_A
module cby_0__1_
(
IO_ISOL_N,
ccff_head_0,
chany_bottom_in,
chany_top_in,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
pReset,
gfpga_pad_io_soc_in,
isol_n,
prog_clk,
prog_reset,
ccff_tail,
chany_bottom_out,
chany_top_out,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out,
right_width_0_height_0_subtile_0__pin_inpad_0_,
right_width_0_height_0_subtile_1__pin_inpad_0_,
right_width_0_height_0_subtile_2__pin_inpad_0_,
right_width_0_height_0_subtile_3__pin_inpad_0_
);
input IO_ISOL_N;
input ccff_head_0;
input [29:0]chany_bottom_in;
input [29:0]chany_top_in;
input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
input pReset;
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input prog_clk;
input prog_reset;
output ccff_tail;
output [29:0]chany_bottom_out;
output [29:0]chany_top_out;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [3:0]gfpga_pad_io_soc_dir;
output [3:0]gfpga_pad_io_soc_out;
output right_width_0_height_0_subtile_0__pin_inpad_0_;
output right_width_0_height_0_subtile_1__pin_inpad_0_;
output right_width_0_height_0_subtile_2__pin_inpad_0_;
output right_width_0_height_0_subtile_3__pin_inpad_0_;
wire IO_ISOL_N;
wire ccff_head_0;
wire ccff_tail;
wire ccff_tail_0;
@ -45,15 +44,16 @@ module cby_0__1_
wire [29:0]chany_bottom_out;
wire [29:0]chany_top_in;
wire [29:0]chany_top_out;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire [3:0]gfpga_pad_io_soc_dir;
wire [3:0]gfpga_pad_io_soc_in;
wire [3:0]gfpga_pad_io_soc_out;
wire isol_n;
wire left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_;
wire left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_;
wire left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_;
wire left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_;
wire pReset;
wire prog_clk;
wire prog_reset;
wire right_width_0_height_0_subtile_0__pin_inpad_0_;
wire right_width_0_height_0_subtile_1__pin_inpad_0_;
wire right_width_0_height_0_subtile_2__pin_inpad_0_;
@ -64,8 +64,8 @@ module cby_0__1_
.ccff_head(ccff_head_0),
.chany_bottom_in(chany_bottom_in),
.chany_top_in(chany_top_in),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail_0),
.chany_bottom_out(chany_bottom_out),
.chany_top_out(chany_top_out),
@ -76,18 +76,18 @@ module cby_0__1_
);
grid_io_left_left grid_io_left_left_0__1_
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(ccff_tail_0),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.pReset(pReset),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.right_width_0_height_0_subtile_0__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
.right_width_0_height_0_subtile_1__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
.right_width_0_height_0_subtile_2__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
.right_width_0_height_0_subtile_3__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_tail(ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
.right_width_0_height_0_subtile_0__pin_inpad_0_(right_width_0_height_0_subtile_0__pin_inpad_0_),
.right_width_0_height_0_subtile_1__pin_inpad_0_(right_width_0_height_0_subtile_1__pin_inpad_0_),
.right_width_0_height_0_subtile_2__pin_inpad_0_(right_width_0_height_0_subtile_2__pin_inpad_0_),

14
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_0__1__old.v
View File

@ -5,8 +5,8 @@ module cby_0__1__old
ccff_head,
chany_bottom_in,
chany_top_in,
pReset,
prog_clk,
prog_reset,
ccff_tail,
chany_bottom_out,
chany_top_out,
@ -19,8 +19,8 @@ module cby_0__1__old
input ccff_head;
input [0:29]chany_bottom_in;
input [0:29]chany_top_in;
input pReset;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:29]chany_bottom_out;
output [0:29]chany_top_out;
@ -50,8 +50,8 @@ module cby_0__1__old
wire mux_tree_tapbuf_size12_mem_0_ccff_tail;
wire mux_tree_tapbuf_size12_mem_1_ccff_tail;
wire mux_tree_tapbuf_size12_mem_2_ccff_tail;
wire pReset;
wire prog_clk;
wire prog_reset;
assign chany_top_out[0] = chany_bottom_in[0];
assign chany_top_out[1] = chany_bottom_in[1];
@ -116,32 +116,32 @@ assign chany_top_out[9] = chany_bottom_in[9];
mux_tree_tapbuf_size12_mem mem_right_ipin_0
(
.ccff_head(ccff_head),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_0_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_1
(
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_1_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_2
(
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_2_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_3
(
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size12_3_sram)
);

38
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_1__1_.v
View File

@ -5,8 +5,8 @@ module cby_1__1_
ccff_head,
chany_bottom_in,
chany_top_in,
pReset,
prog_clk,
prog_reset,
ccff_tail,
chany_bottom_out,
chany_top_out,
@ -31,8 +31,8 @@ module cby_1__1_
input ccff_head;
input [0:29]chany_bottom_in;
input [0:29]chany_top_in;
input pReset;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:29]chany_bottom_out;
output [0:29]chany_top_out;
@ -122,8 +122,8 @@ module cby_1__1_
wire mux_tree_tapbuf_size12_mem_5_ccff_tail;
wire mux_tree_tapbuf_size12_mem_6_ccff_tail;
wire mux_tree_tapbuf_size12_mem_7_ccff_tail;
wire pReset;
wire prog_clk;
wire prog_reset;
assign chany_top_out[0] = chany_bottom_in[0];
assign chany_top_out[1] = chany_bottom_in[1];
@ -188,128 +188,128 @@ assign chany_top_out[9] = chany_bottom_in[9];
mux_tree_tapbuf_size12_mem mem_right_ipin_0
(
.ccff_head(ccff_head),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_0_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_1
(
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_0_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_10
(
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_5_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_11
(
.ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_5_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_12
(
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_6_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_13
(
.ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_6_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_14
(
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_7_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_15
(
.ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size10_7_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_2
(
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_1_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_3
(
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_1_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_4
(
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_2_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_5
(
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_2_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_6
(
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_3_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_7
(
.ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_3_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_8
(
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_4_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_9
(
.ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_4_sram)
);

42
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_8__1_.v
View File

@ -2,20 +2,20 @@
//netlist name: FPGA88_SOFA_A
module cby_8__1_
(
IO_ISOL_N,
ccff_head,
ccff_head_0,
chany_bottom_in,
chany_top_in,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
pReset,
gfpga_pad_io_soc_in,
isol_n,
prog_clk,
prog_reset,
ccff_tail,
ccff_tail_0,
chany_bottom_out,
chany_top_out,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out,
left_grid_right_width_0_height_0_subtile_0__pin_I4_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I4_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_,
@ -38,20 +38,20 @@ module cby_8__1_
left_width_0_height_0_subtile_3__pin_inpad_0_
);
input IO_ISOL_N;
input ccff_head;
input ccff_head_0;
input [29:0]chany_bottom_in;
input [29:0]chany_top_in;
input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
input pReset;
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input prog_clk;
input prog_reset;
output ccff_tail;
output ccff_tail_0;
output [29:0]chany_bottom_out;
output [29:0]chany_top_out;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [3:0]gfpga_pad_io_soc_dir;
output [3:0]gfpga_pad_io_soc_out;
output left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
output left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
output left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
@ -73,7 +73,6 @@ module cby_8__1_
output left_width_0_height_0_subtile_2__pin_inpad_0_;
output left_width_0_height_0_subtile_3__pin_inpad_0_;
wire IO_ISOL_N;
wire ccff_head;
wire ccff_head_0;
wire ccff_tail;
@ -82,9 +81,10 @@ module cby_8__1_
wire [29:0]chany_bottom_out;
wire [29:0]chany_top_in;
wire [29:0]chany_top_out;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire [3:0]gfpga_pad_io_soc_dir;
wire [3:0]gfpga_pad_io_soc_in;
wire [3:0]gfpga_pad_io_soc_out;
wire isol_n;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
@ -105,8 +105,8 @@ module cby_8__1_
wire left_width_0_height_0_subtile_1__pin_inpad_0_;
wire left_width_0_height_0_subtile_2__pin_inpad_0_;
wire left_width_0_height_0_subtile_3__pin_inpad_0_;
wire pReset;
wire prog_clk;
wire prog_reset;
wire right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_;
wire right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_;
wire right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_;
@ -117,8 +117,8 @@ module cby_8__1_
.ccff_head(ccff_head_0),
.chany_bottom_in(chany_bottom_in),
.chany_top_in(chany_top_in),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail_0),
.chany_bottom_out(chany_bottom_out),
.chany_top_out(chany_top_out),
@ -145,18 +145,18 @@ module cby_8__1_
);
grid_io_right_right grid_io_right_right_9__8_
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(ccff_head),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
.isol_n(isol_n),
.left_width_0_height_0_subtile_0__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
.left_width_0_height_0_subtile_1__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
.left_width_0_height_0_subtile_2__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
.left_width_0_height_0_subtile_3__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
.left_width_0_height_0_subtile_0__pin_inpad_0_(left_width_0_height_0_subtile_0__pin_inpad_0_),
.left_width_0_height_0_subtile_1__pin_inpad_0_(left_width_0_height_0_subtile_1__pin_inpad_0_),
.left_width_0_height_0_subtile_2__pin_inpad_0_(left_width_0_height_0_subtile_2__pin_inpad_0_),

46
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_8__1__old.v
View File

@ -5,8 +5,8 @@ module cby_8__1__old
ccff_head,
chany_bottom_in,
chany_top_in,
pReset,
prog_clk,
prog_reset,
ccff_tail,
chany_bottom_out,
chany_top_out,
@ -35,8 +35,8 @@ module cby_8__1__old
input ccff_head;
input [0:29]chany_bottom_in;
input [0:29]chany_top_in;
input pReset;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:29]chany_bottom_out;
output [0:29]chany_top_out;
@ -142,8 +142,8 @@ module cby_8__1__old
wire mux_tree_tapbuf_size12_mem_7_ccff_tail;
wire mux_tree_tapbuf_size12_mem_8_ccff_tail;
wire mux_tree_tapbuf_size12_mem_9_ccff_tail;
wire pReset;
wire prog_clk;
wire prog_reset;
wire right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_;
wire right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_;
wire right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_;
@ -212,160 +212,160 @@ assign chany_top_out[9] = chany_bottom_in[9];
mux_tree_tapbuf_size12_mem mem_left_ipin_0
(
.ccff_head(ccff_head),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_0_sram)
);
mux_tree_tapbuf_size12_mem mem_left_ipin_1
(
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_1_sram)
);
mux_tree_tapbuf_size12_mem mem_left_ipin_2
(
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_2_sram)
);
mux_tree_tapbuf_size12_mem mem_left_ipin_3
(
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_3_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_0
(
.ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_4_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_1
(
.ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_0_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_10
(
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_9_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_11
(
.ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_5_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_12
(
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_10_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_13
(
.ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_6_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_14
(
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_11_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_15
(
.ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size10_7_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_2
(
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_5_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_3
(
.ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_1_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_4
(
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_6_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_5
(
.ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_2_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_6
(
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_7_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_7
(
.ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_3_sram)
);
mux_tree_tapbuf_size12_mem mem_right_ipin_8
(
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_8_sram)
);
mux_tree_tapbuf_size10_mem mem_right_ipin_9
(
.ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_4_sram)
);

40
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.v
View File

@ -3,142 +3,142 @@
module frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem
(
ccff_head,
pReset,
prog_clk,
prog_reset,
ccff_tail,
mem_out
);
input ccff_head;
input pReset;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:16]mem_out;
wire ccff_head;
wire ccff_tail;
wire [0:16]mem_out;
wire pReset;
wire prog_clk;
wire prog_reset;
assign ccff_tail = mem_out[16];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.CLK(prog_clk),
.D(ccff_head),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_
(
.CLK(prog_clk),
.D(mem_out[9]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[10])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_
(
.CLK(prog_clk),
.D(mem_out[10]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[11])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_
(
.CLK(prog_clk),
.D(mem_out[11]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[12])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_
(
.CLK(prog_clk),
.D(mem_out[12]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[13])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_
(
.CLK(prog_clk),
.D(mem_out[13]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[14])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_
(
.CLK(prog_clk),
.D(mem_out[14]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[15])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_
(
.CLK(prog_clk),
.D(mem_out[15]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[16])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.CLK(prog_clk),
.D(mem_out[0]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.CLK(prog_clk),
.D(mem_out[1]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[2])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
(
.CLK(prog_clk),
.D(mem_out[2]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[3])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_
(
.CLK(prog_clk),
.D(mem_out[3]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[4])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_
(
.CLK(prog_clk),
.D(mem_out[4]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[5])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_
(
.CLK(prog_clk),
.D(mem_out[5]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[6])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_
(
.CLK(prog_clk),
.D(mem_out[6]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[7])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_
(
.CLK(prog_clk),
.D(mem_out[7]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[8])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_
(
.CLK(prog_clk),
.D(mem_out[8]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[9])
);
endmodule

16
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_clb.v
View File

@ -2,12 +2,11 @@
//netlist name: FPGA88_SOFA_A
module grid_clb
(
Test_en,
ccff_head,
left_width_0_height_0_subtile_0__pin_clk_0_,
left_width_0_height_0_subtile_0__pin_reset_0_,
pReset,
prog_clk,
prog_reset,
right_width_0_height_0_subtile_0__pin_I4_0_,
right_width_0_height_0_subtile_0__pin_I4_1_,
right_width_0_height_0_subtile_0__pin_I4i_0_,
@ -24,6 +23,7 @@ module grid_clb
right_width_0_height_0_subtile_0__pin_I7_1_,
right_width_0_height_0_subtile_0__pin_I7i_0_,
right_width_0_height_0_subtile_0__pin_I7i_1_,
scan_enable,
top_width_0_height_0_subtile_0__pin_I0_0_,
top_width_0_height_0_subtile_0__pin_I0_1_,
top_width_0_height_0_subtile_0__pin_I0i_0_,
@ -65,12 +65,11 @@ module grid_clb
top_width_0_height_0_subtile_0__pin_O_7_
);
input Test_en;
input ccff_head;
input left_width_0_height_0_subtile_0__pin_clk_0_;
input left_width_0_height_0_subtile_0__pin_reset_0_;
input pReset;
input prog_clk;
input prog_reset;
input right_width_0_height_0_subtile_0__pin_I4_0_;
input right_width_0_height_0_subtile_0__pin_I4_1_;
input right_width_0_height_0_subtile_0__pin_I4i_0_;
@ -87,6 +86,7 @@ module grid_clb
input right_width_0_height_0_subtile_0__pin_I7_1_;
input right_width_0_height_0_subtile_0__pin_I7i_0_;
input right_width_0_height_0_subtile_0__pin_I7i_1_;
input scan_enable;
input top_width_0_height_0_subtile_0__pin_I0_0_;
input top_width_0_height_0_subtile_0__pin_I0_1_;
input top_width_0_height_0_subtile_0__pin_I0i_0_;
@ -127,7 +127,6 @@ module grid_clb
output top_width_0_height_0_subtile_0__pin_O_6_;
output top_width_0_height_0_subtile_0__pin_O_7_;
wire Test_en;
wire bottom_width_0_height_0_subtile_0__pin_cout_0_;
wire bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
wire bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
@ -135,8 +134,8 @@ module grid_clb
wire ccff_tail;
wire left_width_0_height_0_subtile_0__pin_clk_0_;
wire left_width_0_height_0_subtile_0__pin_reset_0_;
wire pReset;
wire prog_clk;
wire prog_reset;
wire right_width_0_height_0_subtile_0__pin_I4_0_;
wire right_width_0_height_0_subtile_0__pin_I4_1_;
wire right_width_0_height_0_subtile_0__pin_I4i_0_;
@ -161,6 +160,7 @@ module grid_clb
wire right_width_0_height_0_subtile_0__pin_O_15_;
wire right_width_0_height_0_subtile_0__pin_O_8_;
wire right_width_0_height_0_subtile_0__pin_O_9_;
wire scan_enable;
wire top_width_0_height_0_subtile_0__pin_I0_0_;
wire top_width_0_height_0_subtile_0__pin_I0_1_;
wire top_width_0_height_0_subtile_0__pin_I0i_0_;
@ -191,7 +191,6 @@ module grid_clb
logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0
(
.Test_en(Test_en),
.ccff_head(ccff_head),
.clb_I0({top_width_0_height_0_subtile_0__pin_I0_0_, top_width_0_height_0_subtile_0__pin_I0_1_}),
.clb_I0i({top_width_0_height_0_subtile_0__pin_I0i_0_, top_width_0_height_0_subtile_0__pin_I0i_1_}),
@ -214,8 +213,9 @@ module grid_clb
.clb_reg_in(top_width_0_height_0_subtile_0__pin_reg_in_0_),
.clb_reset(left_width_0_height_0_subtile_0__pin_reset_0_),
.clb_sc_in(top_width_0_height_0_subtile_0__pin_sc_in_0_),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.scan_enable(scan_enable),
.ccff_tail(ccff_tail),
.clb_O({top_width_0_height_0_subtile_0__pin_O_0_, top_width_0_height_0_subtile_0__pin_O_1_, top_width_0_height_0_subtile_0__pin_O_2_, top_width_0_height_0_subtile_0__pin_O_3_, top_width_0_height_0_subtile_0__pin_O_4_, top_width_0_height_0_subtile_0__pin_O_5_, top_width_0_height_0_subtile_0__pin_O_6_, top_width_0_height_0_subtile_0__pin_O_7_, right_width_0_height_0_subtile_0__pin_O_8_, right_width_0_height_0_subtile_0__pin_O_9_, right_width_0_height_0_subtile_0__pin_O_10_, right_width_0_height_0_subtile_0__pin_O_11_, right_width_0_height_0_subtile_0__pin_O_12_, right_width_0_height_0_subtile_0__pin_O_13_, right_width_0_height_0_subtile_0__pin_O_14_, right_width_0_height_0_subtile_0__pin_O_15_}),
.clb_cout(bottom_width_0_height_0_subtile_0__pin_cout_0_),

70
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_bottom_bottom.v
View File

@ -2,52 +2,52 @@
//netlist name: FPGA88_SOFA_A
module grid_io_bottom_bottom
(
IO_ISOL_N,
ccff_head,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
pReset,
gfpga_pad_io_soc_in,
isol_n,
prog_clk,
prog_reset,
top_width_0_height_0_subtile_0__pin_outpad_0_,
top_width_0_height_0_subtile_1__pin_outpad_0_,
top_width_0_height_0_subtile_2__pin_outpad_0_,
top_width_0_height_0_subtile_3__pin_outpad_0_,
ccff_tail,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out,
top_width_0_height_0_subtile_0__pin_inpad_0_,
top_width_0_height_0_subtile_1__pin_inpad_0_,
top_width_0_height_0_subtile_2__pin_inpad_0_,
top_width_0_height_0_subtile_3__pin_inpad_0_
);
input IO_ISOL_N;
input ccff_head;
input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
input pReset;
input [0:3]gfpga_pad_io_soc_in;
input isol_n;
input prog_clk;
input prog_reset;
input top_width_0_height_0_subtile_0__pin_outpad_0_;
input top_width_0_height_0_subtile_1__pin_outpad_0_;
input top_width_0_height_0_subtile_2__pin_outpad_0_;
input top_width_0_height_0_subtile_3__pin_outpad_0_;
output ccff_tail;
output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [0:3]gfpga_pad_io_soc_dir;
output [0:3]gfpga_pad_io_soc_out;
output top_width_0_height_0_subtile_0__pin_inpad_0_;
output top_width_0_height_0_subtile_1__pin_inpad_0_;
output top_width_0_height_0_subtile_2__pin_inpad_0_;
output top_width_0_height_0_subtile_3__pin_inpad_0_;
wire IO_ISOL_N;
wire ccff_head;
wire ccff_tail;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire [0:3]gfpga_pad_io_soc_dir;
wire [0:3]gfpga_pad_io_soc_in;
wire [0:3]gfpga_pad_io_soc_out;
wire isol_n;
wire logical_tile_io_mode_io__0_ccff_tail;
wire logical_tile_io_mode_io__1_ccff_tail;
wire logical_tile_io_mode_io__2_ccff_tail;
wire pReset;
wire prog_clk;
wire prog_reset;
wire top_width_0_height_0_subtile_0__pin_inpad_0_;
wire top_width_0_height_0_subtile_0__pin_outpad_0_;
wire top_width_0_height_0_subtile_1__pin_inpad_0_;
@ -59,54 +59,54 @@ module grid_io_bottom_bottom
logical_tile_io_mode_io_ logical_tile_io_mode_io__0
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(ccff_head),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
.io_outpad(top_width_0_height_0_subtile_0__pin_outpad_0_),
.pReset(pReset),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
.io_inpad(top_width_0_height_0_subtile_0__pin_inpad_0_)
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__1
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
.io_outpad(top_width_0_height_0_subtile_1__pin_outpad_0_),
.pReset(pReset),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
.io_inpad(top_width_0_height_0_subtile_1__pin_inpad_0_)
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__2
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
.io_outpad(top_width_0_height_0_subtile_2__pin_outpad_0_),
.pReset(pReset),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
.io_inpad(top_width_0_height_0_subtile_2__pin_inpad_0_)
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__3
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
.io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_),
.pReset(pReset),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
.io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_)
);
endmodule

70
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_left_left.v
View File

@ -2,52 +2,52 @@
//netlist name: FPGA88_SOFA_A
module grid_io_left_left
(
IO_ISOL_N,
ccff_head,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
pReset,
gfpga_pad_io_soc_in,
isol_n,
prog_clk,
prog_reset,
right_width_0_height_0_subtile_0__pin_outpad_0_,
right_width_0_height_0_subtile_1__pin_outpad_0_,
right_width_0_height_0_subtile_2__pin_outpad_0_,
right_width_0_height_0_subtile_3__pin_outpad_0_,
ccff_tail,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out,
right_width_0_height_0_subtile_0__pin_inpad_0_,
right_width_0_height_0_subtile_1__pin_inpad_0_,
right_width_0_height_0_subtile_2__pin_inpad_0_,
right_width_0_height_0_subtile_3__pin_inpad_0_
);
input IO_ISOL_N;
input ccff_head;
input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
input pReset;
input [0:3]gfpga_pad_io_soc_in;
input isol_n;
input prog_clk;
input prog_reset;
input right_width_0_height_0_subtile_0__pin_outpad_0_;
input right_width_0_height_0_subtile_1__pin_outpad_0_;
input right_width_0_height_0_subtile_2__pin_outpad_0_;
input right_width_0_height_0_subtile_3__pin_outpad_0_;
output ccff_tail;
output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [0:3]gfpga_pad_io_soc_dir;
output [0:3]gfpga_pad_io_soc_out;
output right_width_0_height_0_subtile_0__pin_inpad_0_;
output right_width_0_height_0_subtile_1__pin_inpad_0_;
output right_width_0_height_0_subtile_2__pin_inpad_0_;
output right_width_0_height_0_subtile_3__pin_inpad_0_;
wire IO_ISOL_N;
wire ccff_head;
wire ccff_tail;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire [0:3]gfpga_pad_io_soc_dir;
wire [0:3]gfpga_pad_io_soc_in;
wire [0:3]gfpga_pad_io_soc_out;
wire isol_n;
wire logical_tile_io_mode_io__0_ccff_tail;
wire logical_tile_io_mode_io__1_ccff_tail;
wire logical_tile_io_mode_io__2_ccff_tail;
wire pReset;
wire prog_clk;
wire prog_reset;
wire right_width_0_height_0_subtile_0__pin_inpad_0_;
wire right_width_0_height_0_subtile_0__pin_outpad_0_;
wire right_width_0_height_0_subtile_1__pin_inpad_0_;
@ -59,54 +59,54 @@ module grid_io_left_left
logical_tile_io_mode_io_ logical_tile_io_mode_io__0
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(ccff_head),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
.io_outpad(right_width_0_height_0_subtile_0__pin_outpad_0_),
.pReset(pReset),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
.io_inpad(right_width_0_height_0_subtile_0__pin_inpad_0_)
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__1
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
.io_outpad(right_width_0_height_0_subtile_1__pin_outpad_0_),
.pReset(pReset),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
.io_inpad(right_width_0_height_0_subtile_1__pin_inpad_0_)
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__2
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
.io_outpad(right_width_0_height_0_subtile_2__pin_outpad_0_),
.pReset(pReset),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
.io_inpad(right_width_0_height_0_subtile_2__pin_inpad_0_)
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__3
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
.io_outpad(right_width_0_height_0_subtile_3__pin_outpad_0_),
.pReset(pReset),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
.io_inpad(right_width_0_height_0_subtile_3__pin_inpad_0_)
);
endmodule

70
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_right_right.v
View File

@ -2,47 +2,47 @@
//netlist name: FPGA88_SOFA_A
module grid_io_right_right
(
IO_ISOL_N,
ccff_head,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_io_soc_in,
isol_n,
left_width_0_height_0_subtile_0__pin_outpad_0_,
left_width_0_height_0_subtile_1__pin_outpad_0_,
left_width_0_height_0_subtile_2__pin_outpad_0_,
left_width_0_height_0_subtile_3__pin_outpad_0_,
pReset,
prog_clk,
prog_reset,
ccff_tail,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out,
left_width_0_height_0_subtile_0__pin_inpad_0_,
left_width_0_height_0_subtile_1__pin_inpad_0_,
left_width_0_height_0_subtile_2__pin_inpad_0_,
left_width_0_height_0_subtile_3__pin_inpad_0_
);
input IO_ISOL_N;
input ccff_head;
input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
input [0:3]gfpga_pad_io_soc_in;
input isol_n;
input left_width_0_height_0_subtile_0__pin_outpad_0_;
input left_width_0_height_0_subtile_1__pin_outpad_0_;
input left_width_0_height_0_subtile_2__pin_outpad_0_;
input left_width_0_height_0_subtile_3__pin_outpad_0_;
input pReset;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [0:3]gfpga_pad_io_soc_dir;
output [0:3]gfpga_pad_io_soc_out;
output left_width_0_height_0_subtile_0__pin_inpad_0_;
output left_width_0_height_0_subtile_1__pin_inpad_0_;
output left_width_0_height_0_subtile_2__pin_inpad_0_;
output left_width_0_height_0_subtile_3__pin_inpad_0_;
wire IO_ISOL_N;
wire ccff_head;
wire ccff_tail;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire [0:3]gfpga_pad_io_soc_dir;
wire [0:3]gfpga_pad_io_soc_in;
wire [0:3]gfpga_pad_io_soc_out;
wire isol_n;
wire left_width_0_height_0_subtile_0__pin_inpad_0_;
wire left_width_0_height_0_subtile_0__pin_outpad_0_;
wire left_width_0_height_0_subtile_1__pin_inpad_0_;
@ -54,59 +54,59 @@ module grid_io_right_right
wire logical_tile_io_mode_io__0_ccff_tail;
wire logical_tile_io_mode_io__1_ccff_tail;
wire logical_tile_io_mode_io__2_ccff_tail;
wire pReset;
wire prog_clk;
wire prog_reset;
logical_tile_io_mode_io_ logical_tile_io_mode_io__0
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(ccff_head),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
.io_outpad(left_width_0_height_0_subtile_0__pin_outpad_0_),
.pReset(pReset),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
.io_inpad(left_width_0_height_0_subtile_0__pin_inpad_0_)
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__1
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
.io_outpad(left_width_0_height_0_subtile_1__pin_outpad_0_),
.pReset(pReset),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
.io_inpad(left_width_0_height_0_subtile_1__pin_inpad_0_)
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__2
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
.io_outpad(left_width_0_height_0_subtile_2__pin_outpad_0_),
.pReset(pReset),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
.io_inpad(left_width_0_height_0_subtile_2__pin_inpad_0_)
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__3
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
.io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_),
.pReset(pReset),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
.io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_)
);
endmodule

70
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_top_top.v
View File

@ -2,42 +2,41 @@
//netlist name: FPGA88_SOFA_A
module grid_io_top_top
(
IO_ISOL_N,
bottom_width_0_height_0_subtile_0__pin_outpad_0_,
bottom_width_0_height_0_subtile_1__pin_outpad_0_,
bottom_width_0_height_0_subtile_2__pin_outpad_0_,
bottom_width_0_height_0_subtile_3__pin_outpad_0_,
ccff_head,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
pReset,
gfpga_pad_io_soc_in,
isol_n,
prog_clk,
prog_reset,
bottom_width_0_height_0_subtile_0__pin_inpad_0_,
bottom_width_0_height_0_subtile_1__pin_inpad_0_,
bottom_width_0_height_0_subtile_2__pin_inpad_0_,
bottom_width_0_height_0_subtile_3__pin_inpad_0_,
ccff_tail,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out
);
input IO_ISOL_N;
input bottom_width_0_height_0_subtile_0__pin_outpad_0_;
input bottom_width_0_height_0_subtile_1__pin_outpad_0_;
input bottom_width_0_height_0_subtile_2__pin_outpad_0_;
input bottom_width_0_height_0_subtile_3__pin_outpad_0_;
input ccff_head;
input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
input pReset;
input [0:3]gfpga_pad_io_soc_in;
input isol_n;
input prog_clk;
input prog_reset;
output bottom_width_0_height_0_subtile_0__pin_inpad_0_;
output bottom_width_0_height_0_subtile_1__pin_inpad_0_;
output bottom_width_0_height_0_subtile_2__pin_inpad_0_;
output bottom_width_0_height_0_subtile_3__pin_inpad_0_;
output ccff_tail;
output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [0:3]gfpga_pad_io_soc_dir;
output [0:3]gfpga_pad_io_soc_out;
wire IO_ISOL_N;
wire bottom_width_0_height_0_subtile_0__pin_inpad_0_;
wire bottom_width_0_height_0_subtile_0__pin_outpad_0_;
wire bottom_width_0_height_0_subtile_1__pin_inpad_0_;
@ -48,65 +47,66 @@ module grid_io_top_top
wire bottom_width_0_height_0_subtile_3__pin_outpad_0_;
wire ccff_head;
wire ccff_tail;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire [0:3]gfpga_pad_io_soc_dir;
wire [0:3]gfpga_pad_io_soc_in;
wire [0:3]gfpga_pad_io_soc_out;
wire isol_n;
wire logical_tile_io_mode_io__0_ccff_tail;
wire logical_tile_io_mode_io__1_ccff_tail;
wire logical_tile_io_mode_io__2_ccff_tail;
wire pReset;
wire prog_clk;
wire prog_reset;
logical_tile_io_mode_io_ logical_tile_io_mode_io__0
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(ccff_head),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
.io_outpad(bottom_width_0_height_0_subtile_0__pin_outpad_0_),
.pReset(pReset),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
.io_inpad(bottom_width_0_height_0_subtile_0__pin_inpad_0_)
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__1
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
.io_outpad(bottom_width_0_height_0_subtile_1__pin_outpad_0_),
.pReset(pReset),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
.io_inpad(bottom_width_0_height_0_subtile_1__pin_inpad_0_)
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__2
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
.io_outpad(bottom_width_0_height_0_subtile_2__pin_outpad_0_),
.pReset(pReset),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
.io_inpad(bottom_width_0_height_0_subtile_2__pin_inpad_0_)
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__3
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
.io_outpad(bottom_width_0_height_0_subtile_3__pin_outpad_0_),
.pReset(pReset),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
.io_inpad(bottom_width_0_height_0_subtile_3__pin_inpad_0_)
);
endmodule

10
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.v → SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/io_sky130_fd_sc_hd__dfrtp_1_mem.v
View File

@ -1,32 +1,32 @@
//Generated from netlist by SpyDrNet
//netlist name: FPGA88_SOFA_A
module EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem
module io_sky130_fd_sc_hd__dfrtp_1_mem
(
ccff_head,
pReset,
prog_clk,
prog_reset,
ccff_tail,
mem_out
);
input ccff_head;
input pReset;
input prog_clk;
input prog_reset;
output ccff_tail;
output mem_out;
wire ccff_head;
wire ccff_tail;
wire mem_out;
wire pReset;
wire prog_clk;
wire prog_reset;
assign ccff_tail = mem_out;
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.CLK(prog_clk),
.D(ccff_head),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out)
);
endmodule

44
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_clb_.v
View File

@ -2,7 +2,6 @@
//netlist name: FPGA88_SOFA_A
module logical_tile_clb_mode_clb_
(
Test_en,
ccff_head,
clb_I0,
clb_I0i,
@ -25,8 +24,9 @@ module logical_tile_clb_mode_clb_
clb_reg_in,
clb_reset,
clb_sc_in,
pReset,
prog_clk,
prog_reset,
scan_enable,
ccff_tail,
clb_O,
clb_cout,
@ -34,7 +34,6 @@ module logical_tile_clb_mode_clb_
clb_sc_out
);
input Test_en;
input ccff_head;
input [0:1]clb_I0;
input [0:1]clb_I0i;
@ -57,15 +56,15 @@ module logical_tile_clb_mode_clb_
input clb_reg_in;
input clb_reset;
input clb_sc_in;
input pReset;
input prog_clk;
input prog_reset;
input scan_enable;
output ccff_tail;
output [0:15]clb_O;
output clb_cout;
output clb_reg_out;
output clb_sc_out;
wire Test_en;
wire ccff_head;
wire ccff_tail;
wire [0:1]clb_I0;
@ -204,8 +203,9 @@ module logical_tile_clb_mode_clb_
wire [0:1]logical_tile_clb_mode_default__fle_7_fle_out;
wire logical_tile_clb_mode_default__fle_7_fle_reg_out;
wire logical_tile_clb_mode_default__fle_7_fle_sc_out;
wire pReset;
wire prog_clk;
wire prog_reset;
wire scan_enable;
direct_interc direct_interc_0_
(
@ -664,7 +664,6 @@ module logical_tile_clb_mode_clb_
);
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0
(
.Test_en(Test_en),
.ccff_head(ccff_head),
.fle_cin(direct_interc_25_out),
.fle_clk(direct_interc_27_out),
@ -672,8 +671,9 @@ module logical_tile_clb_mode_clb_
.fle_reg_in(direct_interc_23_out),
.fle_reset(direct_interc_26_out),
.fle_sc_in(direct_interc_24_out),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.scan_enable(scan_enable),
.ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail),
.fle_cout(logical_tile_clb_mode_default__fle_0_fle_cout),
.fle_out(logical_tile_clb_mode_default__fle_0_fle_out),
@ -682,7 +682,6 @@ module logical_tile_clb_mode_clb_
);
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1
(
.Test_en(Test_en),
.ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail),
.fle_cin(direct_interc_34_out),
.fle_clk(direct_interc_36_out),
@ -690,8 +689,9 @@ module logical_tile_clb_mode_clb_
.fle_reg_in(direct_interc_32_out),
.fle_reset(direct_interc_35_out),
.fle_sc_in(direct_interc_33_out),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.scan_enable(scan_enable),
.ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail),
.fle_cout(logical_tile_clb_mode_default__fle_1_fle_cout),
.fle_out(logical_tile_clb_mode_default__fle_1_fle_out),
@ -700,7 +700,6 @@ module logical_tile_clb_mode_clb_
);
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2
(
.Test_en(Test_en),
.ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail),
.fle_cin(direct_interc_43_out),
.fle_clk(direct_interc_45_out),
@ -708,8 +707,9 @@ module logical_tile_clb_mode_clb_
.fle_reg_in(direct_interc_41_out),
.fle_reset(direct_interc_44_out),
.fle_sc_in(direct_interc_42_out),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.scan_enable(scan_enable),
.ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail),
.fle_cout(logical_tile_clb_mode_default__fle_2_fle_cout),
.fle_out(logical_tile_clb_mode_default__fle_2_fle_out),
@ -718,7 +718,6 @@ module logical_tile_clb_mode_clb_
);
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3
(
.Test_en(Test_en),
.ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail),
.fle_cin(direct_interc_52_out),
.fle_clk(direct_interc_54_out),
@ -726,8 +725,9 @@ module logical_tile_clb_mode_clb_
.fle_reg_in(direct_interc_50_out),
.fle_reset(direct_interc_53_out),
.fle_sc_in(direct_interc_51_out),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.scan_enable(scan_enable),
.ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail),
.fle_cout(logical_tile_clb_mode_default__fle_3_fle_cout),
.fle_out(logical_tile_clb_mode_default__fle_3_fle_out),
@ -736,7 +736,6 @@ module logical_tile_clb_mode_clb_
);
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4
(
.Test_en(Test_en),
.ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail),
.fle_cin(direct_interc_61_out),
.fle_clk(direct_interc_63_out),
@ -744,8 +743,9 @@ module logical_tile_clb_mode_clb_
.fle_reg_in(direct_interc_59_out),
.fle_reset(direct_interc_62_out),
.fle_sc_in(direct_interc_60_out),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.scan_enable(scan_enable),
.ccff_tail(logical_tile_clb_mode_default__fle_4_ccff_tail),
.fle_cout(logical_tile_clb_mode_default__fle_4_fle_cout),
.fle_out(logical_tile_clb_mode_default__fle_4_fle_out),
@ -754,7 +754,6 @@ module logical_tile_clb_mode_clb_
);
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5
(
.Test_en(Test_en),
.ccff_head(logical_tile_clb_mode_default__fle_4_ccff_tail),
.fle_cin(direct_interc_70_out),
.fle_clk(direct_interc_72_out),
@ -762,8 +761,9 @@ module logical_tile_clb_mode_clb_
.fle_reg_in(direct_interc_68_out),
.fle_reset(direct_interc_71_out),
.fle_sc_in(direct_interc_69_out),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.scan_enable(scan_enable),
.ccff_tail(logical_tile_clb_mode_default__fle_5_ccff_tail),
.fle_cout(logical_tile_clb_mode_default__fle_5_fle_cout),
.fle_out(logical_tile_clb_mode_default__fle_5_fle_out),
@ -772,7 +772,6 @@ module logical_tile_clb_mode_clb_
);
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6
(
.Test_en(Test_en),
.ccff_head(logical_tile_clb_mode_default__fle_5_ccff_tail),
.fle_cin(direct_interc_79_out),
.fle_clk(direct_interc_81_out),
@ -780,8 +779,9 @@ module logical_tile_clb_mode_clb_
.fle_reg_in(direct_interc_77_out),
.fle_reset(direct_interc_80_out),
.fle_sc_in(direct_interc_78_out),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.scan_enable(scan_enable),
.ccff_tail(logical_tile_clb_mode_default__fle_6_ccff_tail),
.fle_cout(logical_tile_clb_mode_default__fle_6_fle_cout),
.fle_out(logical_tile_clb_mode_default__fle_6_fle_out),
@ -790,7 +790,6 @@ module logical_tile_clb_mode_clb_
);
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7
(
.Test_en(Test_en),
.ccff_head(logical_tile_clb_mode_default__fle_6_ccff_tail),
.fle_cin(direct_interc_88_out),
.fle_clk(direct_interc_90_out),
@ -798,8 +797,9 @@ module logical_tile_clb_mode_clb_
.fle_reg_in(direct_interc_86_out),
.fle_reset(direct_interc_89_out),
.fle_sc_in(direct_interc_87_out),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.scan_enable(scan_enable),
.ccff_tail(ccff_tail),
.fle_cout(logical_tile_clb_mode_default__fle_7_fle_cout),
.fle_out(logical_tile_clb_mode_default__fle_7_fle_out),

16
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle.v
View File

@ -2,7 +2,6 @@
//netlist name: FPGA88_SOFA_A
module logical_tile_clb_mode_default__fle
(
Test_en,
ccff_head,
fle_cin,
fle_clk,
@ -10,8 +9,9 @@ module logical_tile_clb_mode_default__fle
fle_reg_in,
fle_reset,
fle_sc_in,
pReset,
prog_clk,
prog_reset,
scan_enable,
ccff_tail,
fle_cout,
fle_out,
@ -19,7 +19,6 @@ module logical_tile_clb_mode_default__fle
fle_sc_out
);
input Test_en;
input ccff_head;
input fle_cin;
input fle_clk;
@ -27,15 +26,15 @@ module logical_tile_clb_mode_default__fle
input fle_reg_in;
input fle_reset;
input fle_sc_in;
input pReset;
input prog_clk;
input prog_reset;
input scan_enable;
output ccff_tail;
output fle_cout;
output [0:1]fle_out;
output fle_reg_out;
output fle_sc_out;
wire Test_en;
wire ccff_head;
wire ccff_tail;
wire direct_interc_10_out;
@ -61,8 +60,9 @@ module logical_tile_clb_mode_default__fle
wire [0:1]logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out;
wire logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out;
wire logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out;
wire pReset;
wire prog_clk;
wire prog_reset;
wire scan_enable;
direct_interc direct_interc_0_
(
@ -136,7 +136,6 @@ module logical_tile_clb_mode_default__fle
);
logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0
(
.Test_en(Test_en),
.ccff_head(ccff_head),
.fabric_cin(direct_interc_11_out),
.fabric_clk(direct_interc_13_out),
@ -144,8 +143,9 @@ module logical_tile_clb_mode_default__fle
.fabric_reg_in(direct_interc_9_out),
.fabric_reset(direct_interc_12_out),
.fabric_sc_in(direct_interc_10_out),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.scan_enable(scan_enable),
.ccff_tail(ccff_tail),
.fabric_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout),
.fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out),

26
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
View File

@ -2,7 +2,6 @@
//netlist name: FPGA88_SOFA_A
module logical_tile_clb_mode_default__fle_mode_physical__fabric
(
Test_en,
ccff_head,
fabric_cin,
fabric_clk,
@ -10,8 +9,9 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
fabric_reg_in,
fabric_reset,
fabric_sc_in,
pReset,
prog_clk,
prog_reset,
scan_enable,
ccff_tail,
fabric_cout,
fabric_out,
@ -19,7 +19,6 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
fabric_sc_out
);
input Test_en;
input ccff_head;
input fabric_cin;
input fabric_clk;
@ -27,15 +26,15 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
input fabric_reg_in;
input fabric_reset;
input fabric_sc_in;
input pReset;
input prog_clk;
input prog_reset;
input scan_enable;
output ccff_tail;
output fabric_cout;
output [0:1]fabric_out;
output fabric_reg_out;
output fabric_sc_out;
wire Test_en;
wire ccff_head;
wire ccff_tail;
wire direct_interc_10_out;
@ -77,8 +76,9 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
wire mux_tree_size2_mem_0_ccff_tail;
wire mux_tree_size2_mem_1_ccff_tail;
wire mux_tree_size2_mem_2_ccff_tail;
wire pReset;
wire prog_clk;
wire prog_reset;
wire scan_enable;
direct_interc direct_interc_0_
(
@ -152,20 +152,20 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
);
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0
(
.Test_en(Test_en),
.ff_D(mux_tree_size2_2_out),
.ff_DI(direct_interc_8_out),
.ff_clk(direct_interc_10_out),
.ff_reset(direct_interc_9_out),
.scan_enable(scan_enable),
.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q)
);
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1
(
.Test_en(Test_en),
.ff_D(mux_tree_size2_3_out),
.ff_DI(direct_interc_11_out),
.ff_clk(direct_interc_13_out),
.ff_reset(direct_interc_12_out),
.scan_enable(scan_enable),
.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q)
);
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0
@ -173,8 +173,8 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
.ccff_head(ccff_head),
.frac_logic_cin(direct_interc_7_out),
.frac_logic_in({direct_interc_3_out, direct_interc_4_out, direct_interc_5_out, direct_interc_6_out}),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail),
.frac_logic_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout),
.frac_logic_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out)
@ -182,32 +182,32 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
mux_tree_size2_mem mem_fabric_out_0
(
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_size2_mem_0_ccff_tail),
.mem_out(mux_tree_size2_0_sram)
);
mux_tree_size2_mem mem_fabric_out_1
(
.ccff_head(mux_tree_size2_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_size2_mem_1_ccff_tail),
.mem_out(mux_tree_size2_1_sram)
);
mux_tree_size2_mem mem_ff_0_D_0
(
.ccff_head(mux_tree_size2_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_size2_mem_2_ccff_tail),
.mem_out(mux_tree_size2_2_sram)
);
mux_tree_size2_mem mem_ff_1_D_0
(
.ccff_head(mux_tree_size2_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_size2_3_sram)
);

8
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v
View File

@ -2,27 +2,27 @@
//netlist name: FPGA88_SOFA_A
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
(
Test_en,
ff_D,
ff_DI,
ff_clk,
ff_reset,
scan_enable,
ff_Q
);
input Test_en;
input ff_D;
input ff_DI;
input ff_clk;
input ff_reset;
input scan_enable;
output ff_Q;
wire Test_en;
wire ff_D;
wire ff_DI;
wire ff_Q;
wire ff_clk;
wire ff_reset;
wire scan_enable;
sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_
(
@ -30,7 +30,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
.D(ff_D),
.RESET_B(ff_reset),
.SCD(ff_DI),
.SCE(Test_en),
.SCE(scan_enable),
.Q(ff_Q)
);
endmodule

12
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v
View File

@ -5,8 +5,8 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
ccff_head,
frac_logic_cin,
frac_logic_in,
pReset,
prog_clk,
prog_reset,
ccff_tail,
frac_logic_cout,
frac_logic_out
@ -15,8 +15,8 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
input ccff_head;
input frac_logic_cin;
input [0:3]frac_logic_in;
input pReset;
input prog_clk;
input prog_reset;
output ccff_tail;
output frac_logic_cout;
output [0:1]frac_logic_out;
@ -44,8 +44,8 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
wire mux_tree_size2_1_out;
wire [0:1]mux_tree_size2_1_sram;
wire mux_tree_size2_mem_0_ccff_tail;
wire pReset;
wire prog_clk;
wire prog_reset;
direct_interc direct_interc_0_
(
@ -98,8 +98,8 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
(
.ccff_head(ccff_head),
.frac_lut4_in({direct_interc_2_out, direct_interc_3_out, mux_tree_size2_1_out, direct_interc_4_out}),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail),
.frac_lut4_lut2_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out),
.frac_lut4_lut3_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out),
@ -108,16 +108,16 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
mux_tree_size2_mem mem_frac_logic_out_0
(
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_size2_mem_0_ccff_tail),
.mem_out(mux_tree_size2_0_sram)
);
mux_tree_size2_mem mem_frac_lut4_0_in_2
(
.ccff_head(mux_tree_size2_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_size2_1_sram)
);

8
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v
View File

@ -4,8 +4,8 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
(
ccff_head,
frac_lut4_in,
pReset,
prog_clk,
prog_reset,
ccff_tail,
frac_lut4_lut2_out,
frac_lut4_lut3_out,
@ -14,8 +14,8 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
input ccff_head;
input [0:3]frac_lut4_in;
input pReset;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:1]frac_lut4_lut2_out;
output [0:1]frac_lut4_lut3_out;
@ -31,8 +31,8 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
wire [0:1]frac_lut4_lut2_out;
wire [0:1]frac_lut4_lut3_out;
wire frac_lut4_lut4_out;
wire pReset;
wire prog_clk;
wire prog_reset;
frac_lut4 frac_lut4_0_
(
@ -48,8 +48,8 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem
(
.ccff_head(ccff_head),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out({frac_lut4_0_sram[0], frac_lut4_0_sram[1], frac_lut4_0_sram[2], frac_lut4_0_sram[3], frac_lut4_0_sram[4], frac_lut4_0_sram[5], frac_lut4_0_sram[6], frac_lut4_0_sram[7], frac_lut4_0_sram[8], frac_lut4_0_sram[9], frac_lut4_0_sram[10], frac_lut4_0_sram[11], frac_lut4_0_sram[12], frac_lut4_0_sram[13], frac_lut4_0_sram[14], frac_lut4_0_sram[15], frac_lut4_0_mode})
);

40
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_io_mode_io_.v
View File

@ -2,41 +2,41 @@
//netlist name: FPGA88_SOFA_A
module logical_tile_io_mode_io_
(
IO_ISOL_N,
ccff_head,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_io_soc_in,
io_outpad,
pReset,
isol_n,
prog_clk,
prog_reset,
ccff_tail,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out,
io_inpad
);
input IO_ISOL_N;
input ccff_head;
input gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
input gfpga_pad_io_soc_in;
input io_outpad;
input pReset;
input isol_n;
input prog_clk;
input prog_reset;
output ccff_tail;
output gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
output gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output gfpga_pad_io_soc_dir;
output gfpga_pad_io_soc_out;
output io_inpad;
wire IO_ISOL_N;
wire ccff_head;
wire ccff_tail;
wire direct_interc_1_out;
wire gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire gfpga_pad_io_soc_dir;
wire gfpga_pad_io_soc_in;
wire gfpga_pad_io_soc_out;
wire io_inpad;
wire io_outpad;
wire isol_n;
wire logical_tile_io_mode_physical__iopad_0_iopad_inpad;
wire pReset;
wire prog_clk;
wire prog_reset;
direct_interc direct_interc_0_
(
@ -50,15 +50,15 @@ module logical_tile_io_mode_io_
);
logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(ccff_head),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
.iopad_outpad(direct_interc_1_out),
.pReset(pReset),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
.iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad)
);
endmodule

50
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_io_mode_physical__iopad.v
View File

@ -2,58 +2,58 @@
//netlist name: FPGA88_SOFA_A
module logical_tile_io_mode_physical__iopad
(
IO_ISOL_N,
ccff_head,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_io_soc_in,
iopad_outpad,
pReset,
isol_n,
prog_clk,
prog_reset,
ccff_tail,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out,
iopad_inpad
);
input IO_ISOL_N;
input ccff_head;
input gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
input gfpga_pad_io_soc_in;
input iopad_outpad;
input pReset;
input isol_n;
input prog_clk;
input prog_reset;
output ccff_tail;
output gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
output gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output gfpga_pad_io_soc_dir;
output gfpga_pad_io_soc_out;
output iopad_inpad;
wire EMBEDDED_IO_HD_0_en;
wire IO_ISOL_N;
wire ccff_head;
wire ccff_tail;
wire gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire gfpga_pad_io_soc_dir;
wire gfpga_pad_io_soc_in;
wire gfpga_pad_io_soc_out;
wire io_0_en;
wire iopad_inpad;
wire iopad_outpad;
wire pReset;
wire isol_n;
wire prog_clk;
wire prog_reset;
EMBEDDED_IO_HD EMBEDDED_IO_HD_0_
io io_0_
(
.FPGA_DIR(EMBEDDED_IO_HD_0_en),
.FPGA_DIR(io_0_en),
.FPGA_OUT(iopad_outpad),
.IO_ISOL_N(IO_ISOL_N),
.SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.IO_ISOL_N(isol_n),
.SOC_IN(gfpga_pad_io_soc_in),
.FPGA_IN(iopad_inpad),
.SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT)
.SOC_DIR(gfpga_pad_io_soc_dir),
.SOC_OUT(gfpga_pad_io_soc_out)
);
EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem
io_sky130_fd_sc_hd__dfrtp_1_mem io_sky130_fd_sc_hd__dfrtp_1_mem
(
.ccff_head(ccff_head),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(EMBEDDED_IO_HD_0_en)
.mem_out(io_0_en)
);
endmodule

10
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_size2_mem.v
View File

@ -3,37 +3,37 @@
module mux_tree_size2_mem
(
ccff_head,
pReset,
prog_clk,
prog_reset,
ccff_tail,
mem_out
);
input ccff_head;
input pReset;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:1]mem_out;
wire ccff_head;
wire ccff_tail;
wire [0:1]mem_out;
wire pReset;
wire prog_clk;
wire prog_reset;
assign ccff_tail = mem_out[1];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.CLK(prog_clk),
.D(ccff_head),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.CLK(prog_clk),
.D(mem_out[0]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[1])
);
endmodule

14
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size10_mem.v
View File

@ -3,51 +3,51 @@
module mux_tree_tapbuf_size10_mem
(
ccff_head,
pReset,
prog_clk,
prog_reset,
ccff_tail,
mem_out
);
input ccff_head;
input pReset;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:3]mem_out;
wire ccff_head;
wire ccff_tail;
wire [0:3]mem_out;
wire pReset;
wire prog_clk;
wire prog_reset;
assign ccff_tail = mem_out[3];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.CLK(prog_clk),
.D(ccff_head),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.CLK(prog_clk),
.D(mem_out[0]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.CLK(prog_clk),
.D(mem_out[1]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[2])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
(
.CLK(prog_clk),
.D(mem_out[2]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[3])
);
endmodule

14
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size11_mem.v
View File

@ -3,51 +3,51 @@
module mux_tree_tapbuf_size11_mem
(
ccff_head,
pReset,
prog_clk,
prog_reset,
ccff_tail,
mem_out
);
input ccff_head;
input pReset;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:3]mem_out;
wire ccff_head;
wire ccff_tail;
wire [0:3]mem_out;
wire pReset;
wire prog_clk;
wire prog_reset;
assign ccff_tail = mem_out[3];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.CLK(prog_clk),
.D(ccff_head),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.CLK(prog_clk),
.D(mem_out[0]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.CLK(prog_clk),
.D(mem_out[1]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[2])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
(
.CLK(prog_clk),
.D(mem_out[2]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[3])
);
endmodule

14
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size12_mem.v
View File

@ -3,51 +3,51 @@
module mux_tree_tapbuf_size12_mem
(
ccff_head,
pReset,
prog_clk,
prog_reset,
ccff_tail,
mem_out
);
input ccff_head;
input pReset;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:3]mem_out;
wire ccff_head;
wire ccff_tail;
wire [0:3]mem_out;
wire pReset;
wire prog_clk;
wire prog_reset;
assign ccff_tail = mem_out[3];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.CLK(prog_clk),
.D(ccff_head),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.CLK(prog_clk),
.D(mem_out[0]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.CLK(prog_clk),
.D(mem_out[1]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[2])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
(
.CLK(prog_clk),
.D(mem_out[2]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[3])
);
endmodule

10
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size2_mem.v
View File

@ -3,37 +3,37 @@
module mux_tree_tapbuf_size2_mem
(
ccff_head,
pReset,
prog_clk,
prog_reset,
ccff_tail,
mem_out
);
input ccff_head;
input pReset;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:1]mem_out;
wire ccff_head;
wire ccff_tail;
wire [0:1]mem_out;
wire pReset;
wire prog_clk;
wire prog_reset;
assign ccff_tail = mem_out[1];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.CLK(prog_clk),
.D(ccff_head),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.CLK(prog_clk),
.D(mem_out[0]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[1])
);
endmodule

10
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size3_mem.v
View File

@ -3,37 +3,37 @@
module mux_tree_tapbuf_size3_mem
(
ccff_head,
pReset,
prog_clk,
prog_reset,
ccff_tail,
mem_out
);
input ccff_head;
input pReset;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:1]mem_out;
wire ccff_head;
wire ccff_tail;
wire [0:1]mem_out;
wire pReset;
wire prog_clk;
wire prog_reset;
assign ccff_tail = mem_out[1];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.CLK(prog_clk),
.D(ccff_head),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.CLK(prog_clk),
.D(mem_out[0]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[1])
);
endmodule

12
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size4_mem.v
View File

@ -3,44 +3,44 @@
module mux_tree_tapbuf_size4_mem
(
ccff_head,
pReset,
prog_clk,
prog_reset,
ccff_tail,
mem_out
);
input ccff_head;
input pReset;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:2]mem_out;
wire ccff_head;
wire ccff_tail;
wire [0:2]mem_out;
wire pReset;
wire prog_clk;
wire prog_reset;
assign ccff_tail = mem_out[2];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.CLK(prog_clk),
.D(ccff_head),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.CLK(prog_clk),
.D(mem_out[0]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.CLK(prog_clk),
.D(mem_out[1]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[2])
);
endmodule

12
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size5_mem.v
View File

@ -3,44 +3,44 @@
module mux_tree_tapbuf_size5_mem
(
ccff_head,
pReset,
prog_clk,
prog_reset,
ccff_tail,
mem_out
);
input ccff_head;
input pReset;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:2]mem_out;
wire ccff_head;
wire ccff_tail;
wire [0:2]mem_out;
wire pReset;
wire prog_clk;
wire prog_reset;
assign ccff_tail = mem_out[2];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.CLK(prog_clk),
.D(ccff_head),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.CLK(prog_clk),
.D(mem_out[0]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.CLK(prog_clk),
.D(mem_out[1]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[2])
);
endmodule

12
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size6_mem.v
View File

@ -3,44 +3,44 @@
module mux_tree_tapbuf_size6_mem
(
ccff_head,
pReset,
prog_clk,
prog_reset,
ccff_tail,
mem_out
);
input ccff_head;
input pReset;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:2]mem_out;
wire ccff_head;
wire ccff_tail;
wire [0:2]mem_out;
wire pReset;
wire prog_clk;
wire prog_reset;
assign ccff_tail = mem_out[2];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.CLK(prog_clk),
.D(ccff_head),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.CLK(prog_clk),
.D(mem_out[0]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.CLK(prog_clk),
.D(mem_out[1]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[2])
);
endmodule

12
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size7_mem.v
View File

@ -3,44 +3,44 @@
module mux_tree_tapbuf_size7_mem
(
ccff_head,
pReset,
prog_clk,
prog_reset,
ccff_tail,
mem_out
);
input ccff_head;
input pReset;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:2]mem_out;
wire ccff_head;
wire ccff_tail;
wire [0:2]mem_out;
wire pReset;
wire prog_clk;
wire prog_reset;
assign ccff_tail = mem_out[2];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.CLK(prog_clk),
.D(ccff_head),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.CLK(prog_clk),
.D(mem_out[0]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.CLK(prog_clk),
.D(mem_out[1]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[2])
);
endmodule

14
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size8_mem.v
View File

@ -3,51 +3,51 @@
module mux_tree_tapbuf_size8_mem
(
ccff_head,
pReset,
prog_clk,
prog_reset,
ccff_tail,
mem_out
);
input ccff_head;
input pReset;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:3]mem_out;
wire ccff_head;
wire ccff_tail;
wire [0:3]mem_out;
wire pReset;
wire prog_clk;
wire prog_reset;
assign ccff_tail = mem_out[3];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.CLK(prog_clk),
.D(ccff_head),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.CLK(prog_clk),
.D(mem_out[0]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.CLK(prog_clk),
.D(mem_out[1]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[2])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
(
.CLK(prog_clk),
.D(mem_out[2]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[3])
);
endmodule

14
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size9_mem.v
View File

@ -3,51 +3,51 @@
module mux_tree_tapbuf_size9_mem
(
ccff_head,
pReset,
prog_clk,
prog_reset,
ccff_tail,
mem_out
);
input ccff_head;
input pReset;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:3]mem_out;
wire ccff_head;
wire ccff_tail;
wire [0:3]mem_out;
wire pReset;
wire prog_clk;
wire prog_reset;
assign ccff_tail = mem_out[3];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.CLK(prog_clk),
.D(ccff_head),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.CLK(prog_clk),
.D(mem_out[0]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.CLK(prog_clk),
.D(mem_out[1]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[2])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
(
.CLK(prog_clk),
.D(mem_out[2]),
.RESET_B(pReset),
.RESET_B(prog_reset),
.Q(mem_out[3])
);
endmodule

78
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__0_.v
View File

@ -5,8 +5,8 @@ module sb_0__0_
ccff_head,
chanx_right_in,
chany_top_in,
pReset,
prog_clk,
prog_reset,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
@ -23,8 +23,8 @@ module sb_0__0_
input ccff_head;
input [0:29]chanx_right_in;
input [0:29]chany_top_in;
input pReset;
input prog_clk;
input prog_reset;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
@ -150,8 +150,8 @@ module sb_0__0_
wire mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire pReset;
wire prog_clk;
wire prog_reset;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
@ -188,288 +188,288 @@ assign chanx_right_out[27] = chany_top_in[26];
mux_tree_tapbuf_size3_mem mem_right_track_0
(
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_2_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_10
(
.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_19_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_12
(
.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_20_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_14
(
.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_21_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_16
(
.ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_22_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_18
(
.ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_23_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_2
(
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_16_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_28
(
.ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_24_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_30
(
.ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_25_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_32
(
.ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_26_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_34
(
.ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_27_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_4
(
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_17_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_44
(
.ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_28_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_28_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_46
(
.ccff_head(mux_tree_tapbuf_size2_mem_28_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_29_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_29_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_48
(
.ccff_head(mux_tree_tapbuf_size2_mem_29_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_30_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_30_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_50
(
.ccff_head(mux_tree_tapbuf_size2_mem_30_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_31_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_6
(
.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_3_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_8
(
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_18_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_0
(
.ccff_head(ccff_head),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_10
(
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_12
(
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_14
(
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_16
(
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_18
(
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_7_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_2
(
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_28
(
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_8_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_30
(
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_9_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_32
(
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_10_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_34
(
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_11_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_4
(
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_44
(
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_12_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_46
(
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_13_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_48
(
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_14_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_50
(
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_15_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_6
(
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_8
(
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram)
);

106
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__1_.v
View File

@ -10,8 +10,8 @@ module sb_0__1_
chanx_right_in,
chany_bottom_in,
chany_top_in,
pReset,
prog_clk,
prog_reset,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
@ -38,8 +38,8 @@ module sb_0__1_
input [0:29]chanx_right_in;
input [0:29]chany_bottom_in;
input [0:29]chany_top_in;
input pReset;
input prog_clk;
input prog_reset;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -218,8 +218,8 @@ module sb_0__1_
wire mux_tree_tapbuf_size7_mem_2_ccff_tail;
wire mux_tree_tapbuf_size7_mem_3_ccff_tail;
wire mux_tree_tapbuf_size7_mem_4_ccff_tail;
wire pReset;
wire prog_clk;
wire prog_reset;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -275,400 +275,400 @@ assign chany_bottom_out[17] = chany_top_in[16];
mux_tree_tapbuf_size6_mem mem_bottom_track_1
(
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_7_sram)
);
mux_tree_tapbuf_size7_mem mem_bottom_track_11
(
.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_4_sram)
);
mux_tree_tapbuf_size6_mem mem_bottom_track_13
(
.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_9_sram)
);
mux_tree_tapbuf_size6_mem mem_bottom_track_21
(
.ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_10_sram)
);
mux_tree_tapbuf_size6_mem mem_bottom_track_29
(
.ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_11_sram)
);
mux_tree_tapbuf_size5_mem mem_bottom_track_3
(
.ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_4_sram)
);
mux_tree_tapbuf_size5_mem mem_bottom_track_37
(
.ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_5_sram)
);
mux_tree_tapbuf_size4_mem mem_bottom_track_45
(
.ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_9_sram)
);
mux_tree_tapbuf_size6_mem mem_bottom_track_5
(
.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_8_sram)
);
mux_tree_tapbuf_size3_mem mem_bottom_track_53
(
.ccff_head(mux_tree_tapbuf_size4_mem_9_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size3_8_sram)
);
mux_tree_tapbuf_size7_mem mem_bottom_track_7
(
.ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_3_sram)
);
mux_tree_tapbuf_size5_mem mem_right_track_0
(
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_1_sram)
);
mux_tree_tapbuf_size5_mem mem_right_track_10
(
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_3_sram)
);
mux_tree_tapbuf_size4_mem mem_right_track_12
(
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_2_sram)
);
mux_tree_tapbuf_size4_mem mem_right_track_14
(
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_3_sram)
);
mux_tree_tapbuf_size4_mem mem_right_track_16
(
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_4_sram)
);
mux_tree_tapbuf_size4_mem mem_right_track_18
(
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_5_sram)
);
mux_tree_tapbuf_size6_mem mem_right_track_2
(
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_4_sram)
);
mux_tree_tapbuf_size4_mem mem_right_track_20
(
.ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_6_sram)
);
mux_tree_tapbuf_size4_mem mem_right_track_22
(
.ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_7_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_24
(
.ccff_head(mux_tree_tapbuf_size4_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_26
(
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_2_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_28
(
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_3_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_30
(
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_4_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_32
(
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_5_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_34
(
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_6_sram)
);
mux_tree_tapbuf_size4_mem mem_right_track_36
(
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_8_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_38
(
.ccff_head(mux_tree_tapbuf_size4_mem_8_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram)
);
mux_tree_tapbuf_size5_mem mem_right_track_4
(
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_2_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_40
(
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_44
(
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_46
(
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_48
(
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_50
(
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_7_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_52
(
.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_54
(
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_56
(
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_7_sram)
);
mux_tree_tapbuf_size6_mem mem_right_track_6
(
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_5_sram)
);
mux_tree_tapbuf_size6_mem mem_right_track_8
(
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_6_sram)
);
mux_tree_tapbuf_size7_mem mem_top_track_0
(
.ccff_head(ccff_head),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_0_sram)
);
mux_tree_tapbuf_size7_mem mem_top_track_10
(
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_2_sram)
);
mux_tree_tapbuf_size6_mem mem_top_track_12
(
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_2_sram)
);
mux_tree_tapbuf_size6_mem mem_top_track_2
(
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_0_sram)
);
mux_tree_tapbuf_size6_mem mem_top_track_20
(
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_3_sram)
);
mux_tree_tapbuf_size5_mem mem_top_track_28
(
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_0_sram)
);
mux_tree_tapbuf_size4_mem mem_top_track_36
(
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_0_sram)
);
mux_tree_tapbuf_size6_mem mem_top_track_4
(
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_1_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_44
(
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram)
);
mux_tree_tapbuf_size4_mem mem_top_track_52
(
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_1_sram)
);
mux_tree_tapbuf_size7_mem mem_top_track_6
(
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_1_sram)
);

102
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__8_.v
View File

@ -9,8 +9,8 @@ module sb_0__8_
ccff_head,
chanx_right_in,
chany_bottom_in,
pReset,
prog_clk,
prog_reset,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
@ -35,8 +35,8 @@ module sb_0__8_
input ccff_head;
input [0:29]chanx_right_in;
input [0:29]chany_bottom_in;
input pReset;
input prog_clk;
input prog_reset;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -206,8 +206,8 @@ module sb_0__8_
wire mux_tree_tapbuf_size5_mem_3_ccff_tail;
wire mux_tree_tapbuf_size5_mem_4_ccff_tail;
wire mux_tree_tapbuf_size5_mem_5_ccff_tail;
wire pReset;
wire prog_clk;
wire prog_reset;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -236,384 +236,384 @@ assign chany_bottom_out[11] = chanx_right_in[17];
mux_tree_tapbuf_size3_mem mem_bottom_track_1
(
.ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_11_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_11
(
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_16_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_13
(
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_17_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_15
(
.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_18_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_17
(
.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_19_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_19
(
.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_20_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_29
(
.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_21_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_3
(
.ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_13_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_31
(
.ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_22_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_33
(
.ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_23_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_35
(
.ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_24_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_45
(
.ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_25_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_47
(
.ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_26_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_49
(
.ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_27_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_5
(
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_14_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_51
(
.ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_28_sram)
);
mux_tree_tapbuf_size3_mem mem_bottom_track_7
(
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_12_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_9
(
.ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_15_sram)
);
mux_tree_tapbuf_size5_mem mem_right_track_0
(
.ccff_head(ccff_head),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_0_sram)
);
mux_tree_tapbuf_size5_mem mem_right_track_10
(
.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_5_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_12
(
.ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_14
(
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_16
(
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_2_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_18
(
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram)
);
mux_tree_tapbuf_size5_mem mem_right_track_2
(
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_1_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_20
(
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_22
(
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_24
(
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_26
(
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_28
(
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_3_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_30
(
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_4_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_32
(
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_5_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_34
(
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_6_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_36
(
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_38
(
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram)
);
mux_tree_tapbuf_size5_mem mem_right_track_4
(
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_2_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_40
(
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_7_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_42
(
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_8_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_44
(
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_7_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_46
(
.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_8_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_48
(
.ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_9_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_50
(
.ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_9_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_52
(
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_10_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_54
(
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_11_sram)
);
mux_tree_tapbuf_size2_mem mem_right_track_56
(
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_12_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_58
(
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_10_sram)
);
mux_tree_tapbuf_size5_mem mem_right_track_6
(
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_3_sram)
);
mux_tree_tapbuf_size5_mem mem_right_track_8
(
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_4_sram)
);

102
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__0_.v
View File

@ -10,8 +10,8 @@ module sb_1__0_
left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
pReset,
prog_clk,
prog_reset,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
@ -38,8 +38,8 @@ module sb_1__0_
input left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
input left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
input left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
input pReset;
input prog_clk;
input prog_reset;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
@ -212,8 +212,8 @@ module sb_1__0_
wire mux_tree_tapbuf_size7_mem_2_ccff_tail;
wire mux_tree_tapbuf_size7_mem_3_ccff_tail;
wire mux_tree_tapbuf_size7_mem_4_ccff_tail;
wire pReset;
wire prog_clk;
wire prog_reset;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
@ -272,384 +272,384 @@ assign chanx_left_out[16] = chanx_right_in[15];
mux_tree_tapbuf_size7_mem mem_left_track_1
(
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_3_sram)
);
mux_tree_tapbuf_size7_mem mem_left_track_11
(
.ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_4_sram)
);
mux_tree_tapbuf_size6_mem mem_left_track_13
(
.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_10_sram)
);
mux_tree_tapbuf_size6_mem mem_left_track_21
(
.ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_11_sram)
);
mux_tree_tapbuf_size6_mem mem_left_track_29
(
.ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_12_sram)
);
mux_tree_tapbuf_size5_mem mem_left_track_3
(
.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_3_sram)
);
mux_tree_tapbuf_size5_mem mem_left_track_37
(
.ccff_head(mux_tree_tapbuf_size6_mem_12_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_5_sram)
);
mux_tree_tapbuf_size4_mem mem_left_track_45
(
.ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_4_sram)
);
mux_tree_tapbuf_size5_mem mem_left_track_5
(
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_4_sram)
);
mux_tree_tapbuf_size4_mem mem_left_track_53
(
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size4_5_sram)
);
mux_tree_tapbuf_size6_mem mem_left_track_7
(
.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_9_sram)
);
mux_tree_tapbuf_size6_mem mem_right_track_0
(
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_3_sram)
);
mux_tree_tapbuf_size7_mem mem_right_track_10
(
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_2_sram)
);
mux_tree_tapbuf_size6_mem mem_right_track_12
(
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_6_sram)
);
mux_tree_tapbuf_size6_mem mem_right_track_2
(
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_4_sram)
);
mux_tree_tapbuf_size6_mem mem_right_track_20
(
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_7_sram)
);
mux_tree_tapbuf_size6_mem mem_right_track_28
(
.ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_8_sram)
);
mux_tree_tapbuf_size5_mem mem_right_track_36
(
.ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_2_sram)
);
mux_tree_tapbuf_size6_mem mem_right_track_4
(
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_5_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_44
(
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_5_sram)
);
mux_tree_tapbuf_size3_mem mem_right_track_52
(
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_6_sram)
);
mux_tree_tapbuf_size7_mem mem_right_track_6
(
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_1_sram)
);
mux_tree_tapbuf_size7_mem mem_top_track_0
(
.ccff_head(ccff_head),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_0_sram)
);
mux_tree_tapbuf_size5_mem mem_top_track_10
(
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_1_sram)
);
mux_tree_tapbuf_size4_mem mem_top_track_12
(
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_0_sram)
);
mux_tree_tapbuf_size4_mem mem_top_track_14
(
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_1_sram)
);
mux_tree_tapbuf_size4_mem mem_top_track_16
(
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_2_sram)
);
mux_tree_tapbuf_size4_mem mem_top_track_18
(
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_3_sram)
);
mux_tree_tapbuf_size6_mem mem_top_track_2
(
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_0_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_20
(
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_22
(
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_24
(
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_2_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_26
(
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_3_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_28
(
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_30
(
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_32
(
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_34
(
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_36
(
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_4_sram)
);
mux_tree_tapbuf_size5_mem mem_top_track_4
(
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_0_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_40
(
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_42
(
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_44
(
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_46
(
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_7_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_48
(
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_8_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_50
(
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_9_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_58
(
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_10_sram)
);
mux_tree_tapbuf_size6_mem mem_top_track_6
(
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_1_sram)
);
mux_tree_tapbuf_size6_mem mem_top_track_8
(
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_2_sram)
);

94
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__1_.v
View File

@ -23,8 +23,8 @@ module sb_1__1_
left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_,
pReset,
prog_clk,
prog_reset,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
@ -69,8 +69,8 @@ module sb_1__1_
input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_;
input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_;
input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_;
input pReset;
input prog_clk;
input prog_reset;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -250,8 +250,8 @@ module sb_1__1_
wire mux_tree_tapbuf_size9_mem_1_ccff_tail;
wire mux_tree_tapbuf_size9_mem_2_ccff_tail;
wire mux_tree_tapbuf_size9_mem_3_ccff_tail;
wire pReset;
wire prog_clk;
wire prog_reset;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -348,352 +348,352 @@ assign chany_bottom_out[17] = chany_top_in[16];
mux_tree_tapbuf_size11_mem mem_bottom_track_1
(
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size11_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size11_4_sram)
);
mux_tree_tapbuf_size12_mem mem_bottom_track_11
(
.ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_5_sram)
);
mux_tree_tapbuf_size10_mem mem_bottom_track_13
(
.ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_7_sram)
);
mux_tree_tapbuf_size10_mem mem_bottom_track_21
(
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_8_sram)
);
mux_tree_tapbuf_size9_mem mem_bottom_track_29
(
.ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_2_sram)
);
mux_tree_tapbuf_size11_mem mem_bottom_track_3
(
.ccff_head(mux_tree_tapbuf_size11_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size11_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size11_5_sram)
);
mux_tree_tapbuf_size6_mem mem_bottom_track_37
(
.ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_6_sram)
);
mux_tree_tapbuf_size6_mem mem_bottom_track_45
(
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_7_sram)
);
mux_tree_tapbuf_size10_mem mem_bottom_track_5
(
.ccff_head(mux_tree_tapbuf_size11_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_6_sram)
);
mux_tree_tapbuf_size6_mem mem_bottom_track_53
(
.ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_8_sram)
);
mux_tree_tapbuf_size12_mem mem_bottom_track_7
(
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_4_sram)
);
mux_tree_tapbuf_size11_mem mem_left_track_1
(
.ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size11_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size11_6_sram)
);
mux_tree_tapbuf_size12_mem mem_left_track_11
(
.ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_7_sram)
);
mux_tree_tapbuf_size10_mem mem_left_track_13
(
.ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_10_sram)
);
mux_tree_tapbuf_size10_mem mem_left_track_21
(
.ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_11_sram)
);
mux_tree_tapbuf_size9_mem mem_left_track_29
(
.ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_3_sram)
);
mux_tree_tapbuf_size11_mem mem_left_track_3
(
.ccff_head(mux_tree_tapbuf_size11_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size11_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size11_7_sram)
);
mux_tree_tapbuf_size6_mem mem_left_track_37
(
.ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_9_sram)
);
mux_tree_tapbuf_size6_mem mem_left_track_45
(
.ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_10_sram)
);
mux_tree_tapbuf_size10_mem mem_left_track_5
(
.ccff_head(mux_tree_tapbuf_size11_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_9_sram)
);
mux_tree_tapbuf_size6_mem mem_left_track_53
(
.ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size6_11_sram)
);
mux_tree_tapbuf_size12_mem mem_left_track_7
(
.ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_6_sram)
);
mux_tree_tapbuf_size11_mem mem_right_track_0
(
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size11_2_sram)
);
mux_tree_tapbuf_size12_mem mem_right_track_10
(
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_3_sram)
);
mux_tree_tapbuf_size10_mem mem_right_track_12
(
.ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_4_sram)
);
mux_tree_tapbuf_size11_mem mem_right_track_2
(
.ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size11_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size11_3_sram)
);
mux_tree_tapbuf_size10_mem mem_right_track_20
(
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_5_sram)
);
mux_tree_tapbuf_size9_mem mem_right_track_28
(
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_1_sram)
);
mux_tree_tapbuf_size6_mem mem_right_track_36
(
.ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_3_sram)
);
mux_tree_tapbuf_size10_mem mem_right_track_4
(
.ccff_head(mux_tree_tapbuf_size11_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_3_sram)
);
mux_tree_tapbuf_size6_mem mem_right_track_44
(
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_4_sram)
);
mux_tree_tapbuf_size6_mem mem_right_track_52
(
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_5_sram)
);
mux_tree_tapbuf_size12_mem mem_right_track_6
(
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_2_sram)
);
mux_tree_tapbuf_size11_mem mem_top_track_0
(
.ccff_head(ccff_head),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size11_0_sram)
);
mux_tree_tapbuf_size12_mem mem_top_track_10
(
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_1_sram)
);
mux_tree_tapbuf_size10_mem mem_top_track_12
(
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_1_sram)
);
mux_tree_tapbuf_size11_mem mem_top_track_2
(
.ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size11_1_sram)
);
mux_tree_tapbuf_size10_mem mem_top_track_20
(
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_2_sram)
);
mux_tree_tapbuf_size9_mem mem_top_track_28
(
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_0_sram)
);
mux_tree_tapbuf_size6_mem mem_top_track_36
(
.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_0_sram)
);
mux_tree_tapbuf_size10_mem mem_top_track_4
(
.ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_0_sram)
);
mux_tree_tapbuf_size6_mem mem_top_track_44
(
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_1_sram)
);
mux_tree_tapbuf_size6_mem mem_top_track_52
(
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_2_sram)
);
mux_tree_tapbuf_size12_mem mem_top_track_6
(
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size12_0_sram)
);

102
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__8_.v
View File

@ -26,8 +26,8 @@ module sb_1__8_
left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
pReset,
prog_clk,
prog_reset,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
@ -70,8 +70,8 @@ module sb_1__8_
input left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
input left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
input left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
input pReset;
input prog_clk;
input prog_reset;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -260,8 +260,8 @@ module sb_1__8_
wire mux_tree_tapbuf_size9_mem_0_ccff_tail;
wire mux_tree_tapbuf_size9_mem_1_ccff_tail;
wire mux_tree_tapbuf_size9_mem_2_ccff_tail;
wire pReset;
wire prog_clk;
wire prog_reset;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -320,384 +320,384 @@ assign chanx_left_out[13] = chanx_right_in[12];
mux_tree_tapbuf_size6_mem mem_bottom_track_1
(
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_2_sram)
);
mux_tree_tapbuf_size5_mem mem_bottom_track_11
(
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_2_sram)
);
mux_tree_tapbuf_size4_mem mem_bottom_track_13
(
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_0_sram)
);
mux_tree_tapbuf_size4_mem mem_bottom_track_15
(
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_1_sram)
);
mux_tree_tapbuf_size4_mem mem_bottom_track_17
(
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_2_sram)
);
mux_tree_tapbuf_size4_mem mem_bottom_track_19
(
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_3_sram)
);
mux_tree_tapbuf_size3_mem mem_bottom_track_21
(
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram)
);
mux_tree_tapbuf_size3_mem mem_bottom_track_23
(
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram)
);
mux_tree_tapbuf_size3_mem mem_bottom_track_25
(
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_2_sram)
);
mux_tree_tapbuf_size3_mem mem_bottom_track_27
(
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_3_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_29
(
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram)
);
mux_tree_tapbuf_size6_mem mem_bottom_track_3
(
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_3_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_31
(
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_33
(
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_35
(
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram)
);
mux_tree_tapbuf_size4_mem mem_bottom_track_37
(
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_4_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_39
(
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_41
(
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_43
(
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_45
(
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_7_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_47
(
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_8_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_49
(
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_9_sram)
);
mux_tree_tapbuf_size5_mem mem_bottom_track_5
(
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_1_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_51
(
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_10_sram)
);
mux_tree_tapbuf_size6_mem mem_bottom_track_7
(
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_4_sram)
);
mux_tree_tapbuf_size6_mem mem_bottom_track_9
(
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_5_sram)
);
mux_tree_tapbuf_size8_mem mem_left_track_1
(
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size8_2_sram)
);
mux_tree_tapbuf_size11_mem mem_left_track_11
(
.ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size11_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size11_3_sram)
);
mux_tree_tapbuf_size7_mem mem_left_track_13
(
.ccff_head(mux_tree_tapbuf_size11_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_3_sram)
);
mux_tree_tapbuf_size7_mem mem_left_track_21
(
.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_4_sram)
);
mux_tree_tapbuf_size7_mem mem_left_track_29
(
.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_5_sram)
);
mux_tree_tapbuf_size9_mem mem_left_track_3
(
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_1_sram)
);
mux_tree_tapbuf_size6_mem mem_left_track_37
(
.ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_6_sram)
);
mux_tree_tapbuf_size5_mem mem_left_track_45
(
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_3_sram)
);
mux_tree_tapbuf_size9_mem mem_left_track_5
(
.ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_2_sram)
);
mux_tree_tapbuf_size5_mem mem_left_track_53
(
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size5_4_sram)
);
mux_tree_tapbuf_size11_mem mem_left_track_7
(
.ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size11_2_sram)
);
mux_tree_tapbuf_size8_mem mem_right_track_0
(
.ccff_head(ccff_head),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size8_0_sram)
);
mux_tree_tapbuf_size11_mem mem_right_track_10
(
.ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size11_1_sram)
);
mux_tree_tapbuf_size7_mem mem_right_track_12
(
.ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_0_sram)
);
mux_tree_tapbuf_size8_mem mem_right_track_2
(
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size8_1_sram)
);
mux_tree_tapbuf_size7_mem mem_right_track_20
(
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_1_sram)
);
mux_tree_tapbuf_size7_mem mem_right_track_28
(
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_2_sram)
);
mux_tree_tapbuf_size6_mem mem_right_track_36
(
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_0_sram)
);
mux_tree_tapbuf_size9_mem mem_right_track_4
(
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_0_sram)
);
mux_tree_tapbuf_size6_mem mem_right_track_44
(
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_1_sram)
);
mux_tree_tapbuf_size5_mem mem_right_track_52
(
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_0_sram)
);
mux_tree_tapbuf_size11_mem mem_right_track_6
(
.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size11_0_sram)
);

94
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__0_.v
View File

@ -9,8 +9,8 @@ module sb_8__0_
left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
pReset,
prog_clk,
prog_reset,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
@ -35,8 +35,8 @@ module sb_8__0_
input left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
input left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
input left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
input pReset;
input prog_clk;
input prog_reset;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@ -194,8 +194,8 @@ module sb_8__0_
wire mux_tree_tapbuf_size5_mem_3_ccff_tail;
wire mux_tree_tapbuf_size5_mem_4_ccff_tail;
wire mux_tree_tapbuf_size5_mem_5_ccff_tail;
wire pReset;
wire prog_clk;
wire prog_reset;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@ -228,352 +228,352 @@ assign chanx_left_out[12] = chany_top_in[18];
mux_tree_tapbuf_size3_mem mem_left_track_1
(
.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_8_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_11
(
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_15_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_13
(
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_16_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_15
(
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_17_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_17
(
.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_18_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_19
(
.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_19_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_29
(
.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_20_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_3
(
.ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_12_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_31
(
.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_21_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_33
(
.ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_22_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_35
(
.ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_23_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_45
(
.ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_24_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_47
(
.ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_25_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_49
(
.ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_26_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_5
(
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_13_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_51
(
.ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_27_sram)
);
mux_tree_tapbuf_size3_mem mem_left_track_7
(
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_9_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_9
(
.ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_14_sram)
);
mux_tree_tapbuf_size5_mem mem_top_track_0
(
.ccff_head(ccff_head),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_0_sram)
);
mux_tree_tapbuf_size5_mem mem_top_track_10
(
.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_5_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_12
(
.ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_14
(
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_16
(
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_2_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_18
(
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_3_sram)
);
mux_tree_tapbuf_size5_mem mem_top_track_2
(
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_1_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_20
(
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_22
(
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_24
(
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_26
(
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_28
(
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_30
(
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_32
(
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_34
(
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_7_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_36
(
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_8_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_38
(
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_9_sram)
);
mux_tree_tapbuf_size5_mem mem_top_track_4
(
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_2_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_40
(
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_10_sram)
);
mux_tree_tapbuf_size2_mem mem_top_track_42
(
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_11_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_44
(
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_4_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_46
(
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_5_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_48
(
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_6_sram)
);
mux_tree_tapbuf_size3_mem mem_top_track_50
(
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_7_sram)
);
mux_tree_tapbuf_size5_mem mem_top_track_6
(
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_3_sram)
);
mux_tree_tapbuf_size5_mem mem_top_track_8
(
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_4_sram)
);

104
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__1_.v
View File

@ -26,8 +26,8 @@ module sb_8__1_
left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_,
pReset,
prog_clk,
prog_reset,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
@ -70,8 +70,8 @@ module sb_8__1_
input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_;
input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_;
input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_;
input pReset;
input prog_clk;
input prog_reset;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@ -263,8 +263,8 @@ module sb_8__1_
wire mux_tree_tapbuf_size9_mem_1_ccff_tail;
wire mux_tree_tapbuf_size9_mem_2_ccff_tail;
wire mux_tree_tapbuf_size9_mem_3_ccff_tail;
wire pReset;
wire prog_clk;
wire prog_reset;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@ -322,392 +322,392 @@ assign chany_bottom_out[16] = chany_top_in[15];
mux_tree_tapbuf_size9_mem mem_bottom_track_1
(
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_1_sram)
);
mux_tree_tapbuf_size11_mem mem_bottom_track_11
(
.ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size11_2_sram)
);
mux_tree_tapbuf_size7_mem mem_bottom_track_13
(
.ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_3_sram)
);
mux_tree_tapbuf_size7_mem mem_bottom_track_21
(
.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_4_sram)
);
mux_tree_tapbuf_size6_mem mem_bottom_track_29
(
.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_3_sram)
);
mux_tree_tapbuf_size9_mem mem_bottom_track_3
(
.ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_2_sram)
);
mux_tree_tapbuf_size5_mem mem_bottom_track_37
(
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_0_sram)
);
mux_tree_tapbuf_size5_mem mem_bottom_track_45
(
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_1_sram)
);
mux_tree_tapbuf_size9_mem mem_bottom_track_5
(
.ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_3_sram)
);
mux_tree_tapbuf_size6_mem mem_bottom_track_53
(
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_4_sram)
);
mux_tree_tapbuf_size11_mem mem_bottom_track_7
(
.ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size11_1_sram)
);
mux_tree_tapbuf_size6_mem mem_left_track_1
(
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_5_sram)
);
mux_tree_tapbuf_size5_mem mem_left_track_11
(
.ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_3_sram)
);
mux_tree_tapbuf_size4_mem mem_left_track_13
(
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_0_sram)
);
mux_tree_tapbuf_size4_mem mem_left_track_15
(
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_1_sram)
);
mux_tree_tapbuf_size4_mem mem_left_track_17
(
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_2_sram)
);
mux_tree_tapbuf_size4_mem mem_left_track_19
(
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_3_sram)
);
mux_tree_tapbuf_size4_mem mem_left_track_21
(
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_4_sram)
);
mux_tree_tapbuf_size4_mem mem_left_track_23
(
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_5_sram)
);
mux_tree_tapbuf_size3_mem mem_left_track_25
(
.ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram)
);
mux_tree_tapbuf_size3_mem mem_left_track_27
(
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram)
);
mux_tree_tapbuf_size3_mem mem_left_track_29
(
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_2_sram)
);
mux_tree_tapbuf_size6_mem mem_left_track_3
(
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_6_sram)
);
mux_tree_tapbuf_size3_mem mem_left_track_31
(
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_3_sram)
);
mux_tree_tapbuf_size3_mem mem_left_track_33
(
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_4_sram)
);
mux_tree_tapbuf_size3_mem mem_left_track_35
(
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_5_sram)
);
mux_tree_tapbuf_size3_mem mem_left_track_37
(
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_6_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_41
(
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_45
(
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_47
(
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_49
(
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram)
);
mux_tree_tapbuf_size5_mem mem_left_track_5
(
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_2_sram)
);
mux_tree_tapbuf_size3_mem mem_left_track_51
(
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_7_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_53
(
.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_55
(
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_57
(
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram)
);
mux_tree_tapbuf_size6_mem mem_left_track_7
(
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_7_sram)
);
mux_tree_tapbuf_size6_mem mem_left_track_9
(
.ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_8_sram)
);
mux_tree_tapbuf_size9_mem mem_top_track_0
(
.ccff_head(ccff_head),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_0_sram)
);
mux_tree_tapbuf_size11_mem mem_top_track_10
(
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size11_0_sram)
);
mux_tree_tapbuf_size7_mem mem_top_track_12
(
.ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_0_sram)
);
mux_tree_tapbuf_size8_mem mem_top_track_2
(
.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size8_0_sram)
);
mux_tree_tapbuf_size7_mem mem_top_track_20
(
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_1_sram)
);
mux_tree_tapbuf_size7_mem mem_top_track_28
(
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size7_2_sram)
);
mux_tree_tapbuf_size6_mem mem_top_track_36
(
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_0_sram)
);
mux_tree_tapbuf_size8_mem mem_top_track_4
(
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size8_1_sram)
);
mux_tree_tapbuf_size6_mem mem_top_track_44
(
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_1_sram)
);
mux_tree_tapbuf_size6_mem mem_top_track_52
(
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_2_sram)
);
mux_tree_tapbuf_size10_mem mem_top_track_6
(
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_0_sram)
);

118
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__8_.v
View File

@ -29,8 +29,8 @@ module sb_8__8_
left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
pReset,
prog_clk,
prog_reset,
ccff_tail,
chanx_left_out,
chany_bottom_out
@ -63,8 +63,8 @@ module sb_8__8_
input left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
input left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
input left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
input pReset;
input prog_clk;
input prog_reset;
output ccff_tail;
output [0:29]chanx_left_out;
output [0:29]chany_bottom_out;
@ -266,8 +266,8 @@ module sb_8__8_
wire mux_tree_tapbuf_size5_mem_7_ccff_tail;
wire mux_tree_tapbuf_size5_mem_8_ccff_tail;
wire mux_tree_tapbuf_size5_mem_9_ccff_tail;
wire pReset;
wire prog_clk;
wire prog_reset;
assign chany_bottom_out[18] = chanx_left_in[19];
assign chany_bottom_out[19] = chanx_left_in[20];
@ -276,448 +276,448 @@ assign chany_bottom_out[21] = chanx_left_in[22];
mux_tree_tapbuf_size5_mem mem_bottom_track_1
(
.ccff_head(ccff_head),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_0_sram)
);
mux_tree_tapbuf_size5_mem mem_bottom_track_11
(
.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_5_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_13
(
.ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_15
(
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_17
(
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_19
(
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_21
(
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_23
(
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_25
(
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_27
(
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_7_sram)
);
mux_tree_tapbuf_size3_mem mem_bottom_track_29
(
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram)
);
mux_tree_tapbuf_size5_mem mem_bottom_track_3
(
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_1_sram)
);
mux_tree_tapbuf_size3_mem mem_bottom_track_31
(
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram)
);
mux_tree_tapbuf_size3_mem mem_bottom_track_33
(
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_2_sram)
);
mux_tree_tapbuf_size3_mem mem_bottom_track_35
(
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_3_sram)
);
mux_tree_tapbuf_size3_mem mem_bottom_track_45
(
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_4_sram)
);
mux_tree_tapbuf_size3_mem mem_bottom_track_47
(
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_5_sram)
);
mux_tree_tapbuf_size3_mem mem_bottom_track_49
(
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_6_sram)
);
mux_tree_tapbuf_size5_mem mem_bottom_track_5
(
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_2_sram)
);
mux_tree_tapbuf_size3_mem mem_bottom_track_51
(
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_7_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_53
(
.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_8_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_55
(
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_9_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_57
(
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_10_sram)
);
mux_tree_tapbuf_size2_mem mem_bottom_track_59
(
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_11_sram)
);
mux_tree_tapbuf_size5_mem mem_bottom_track_7
(
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_3_sram)
);
mux_tree_tapbuf_size5_mem mem_bottom_track_9
(
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_4_sram)
);
mux_tree_tapbuf_size5_mem mem_left_track_1
(
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_6_sram)
);
mux_tree_tapbuf_size5_mem mem_left_track_11
(
.ccff_head(mux_tree_tapbuf_size5_mem_10_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_11_sram)
);
mux_tree_tapbuf_size3_mem mem_left_track_13
(
.ccff_head(mux_tree_tapbuf_size5_mem_11_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_8_sram)
);
mux_tree_tapbuf_size3_mem mem_left_track_15
(
.ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_9_sram)
);
mux_tree_tapbuf_size3_mem mem_left_track_17
(
.ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_10_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_19
(
.ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_12_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_21
(
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_13_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_23
(
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_14_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_25
(
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_15_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_27
(
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_16_sram)
);
mux_tree_tapbuf_size3_mem mem_left_track_29
(
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_11_sram)
);
mux_tree_tapbuf_size5_mem mem_left_track_3
(
.ccff_head(mux_tree_tapbuf_size5_mem_6_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_7_sram)
);
mux_tree_tapbuf_size3_mem mem_left_track_31
(
.ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_12_sram)
);
mux_tree_tapbuf_size3_mem mem_left_track_33
(
.ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_13_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_13_sram)
);
mux_tree_tapbuf_size3_mem mem_left_track_35
(
.ccff_head(mux_tree_tapbuf_size3_mem_13_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_14_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_14_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_37
(
.ccff_head(mux_tree_tapbuf_size3_mem_14_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_17_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_39
(
.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_18_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_41
(
.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_19_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_43
(
.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_20_sram)
);
mux_tree_tapbuf_size3_mem mem_left_track_45
(
.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_15_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_15_sram)
);
mux_tree_tapbuf_size3_mem mem_left_track_47
(
.ccff_head(mux_tree_tapbuf_size3_mem_15_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_16_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_16_sram)
);
mux_tree_tapbuf_size3_mem mem_left_track_49
(
.ccff_head(mux_tree_tapbuf_size3_mem_16_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size3_mem_17_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_17_sram)
);
mux_tree_tapbuf_size5_mem mem_left_track_5
(
.ccff_head(mux_tree_tapbuf_size5_mem_7_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_8_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_51
(
.ccff_head(mux_tree_tapbuf_size3_mem_17_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_21_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_53
(
.ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_22_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_55
(
.ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_23_sram)
);
mux_tree_tapbuf_size2_mem mem_left_track_57
(
.ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_24_sram)
);
mux_tree_tapbuf_size3_mem mem_left_track_59
(
.ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size3_18_sram)
);
mux_tree_tapbuf_size5_mem mem_left_track_7
(
.ccff_head(mux_tree_tapbuf_size5_mem_8_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_9_sram)
);
mux_tree_tapbuf_size5_mem mem_left_track_9
(
.ccff_head(mux_tree_tapbuf_size5_mem_9_ccff_tail),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(mux_tree_tapbuf_size5_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_10_sram)
);

8
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_left_tile.v
View File

@ -5,8 +5,8 @@ module bottom_left_tile
ccff_head,
chanx_right_in,
chany_top_in,
pReset,
prog_clk,
prog_reset,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
@ -23,8 +23,8 @@ module bottom_left_tile
input ccff_head;
input [29:0]chanx_right_in;
input [29:0]chany_top_in;
input pReset;
input prog_clk;
input prog_reset;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
@ -43,8 +43,8 @@ module bottom_left_tile
wire [29:0]chanx_right_out;
wire [29:0]chany_top_in;
wire [29:0]chany_top_out;
wire pReset;
wire prog_clk;
wire prog_reset;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
@ -59,8 +59,8 @@ module bottom_left_tile
.ccff_head(ccff_head),
.chanx_right_in(chanx_right_in),
.chany_top_in(chany_top_in),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_),

42
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_right_tile.v
View File

@ -2,14 +2,14 @@
//netlist name: FPGA88_SOFA_A
module bottom_right_tile
(
IO_ISOL_N,
ccff_head,
ccff_head_1,
chanx_left_in,
chany_top_in,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
pReset,
gfpga_pad_io_soc_in,
isol_n,
prog_clk,
prog_reset,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
@ -26,22 +26,22 @@ module bottom_right_tile
ccff_tail_0,
chanx_left_out,
chany_top_out,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out,
top_width_0_height_0_subtile_0__pin_inpad_0_,
top_width_0_height_0_subtile_1__pin_inpad_0_,
top_width_0_height_0_subtile_2__pin_inpad_0_,
top_width_0_height_0_subtile_3__pin_inpad_0_
);
input IO_ISOL_N;
input ccff_head;
input ccff_head_1;
input [29:0]chanx_left_in;
input [29:0]chany_top_in;
input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
input pReset;
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input prog_clk;
input prog_reset;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@ -58,14 +58,13 @@ module bottom_right_tile
output ccff_tail_0;
output [29:0]chanx_left_out;
output [29:0]chany_top_out;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [3:0]gfpga_pad_io_soc_dir;
output [3:0]gfpga_pad_io_soc_out;
output top_width_0_height_0_subtile_0__pin_inpad_0_;
output top_width_0_height_0_subtile_1__pin_inpad_0_;
output top_width_0_height_0_subtile_2__pin_inpad_0_;
output top_width_0_height_0_subtile_3__pin_inpad_0_;
wire IO_ISOL_N;
wire ccff_head;
wire ccff_head_1;
wire ccff_tail;
@ -77,11 +76,12 @@ module bottom_right_tile
wire [29:0]chanx_right_out;
wire [29:0]chany_top_in;
wire [29:0]chany_top_out;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire pReset;
wire [3:0]gfpga_pad_io_soc_dir;
wire [3:0]gfpga_pad_io_soc_in;
wire [3:0]gfpga_pad_io_soc_out;
wire isol_n;
wire prog_clk;
wire prog_reset;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@ -101,20 +101,20 @@ module bottom_right_tile
cbx_1__0_ cbx_8__0_
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(ccff_head),
.ccff_head_0(ccff_tail_1),
.chanx_left_in(chanx_left_in),
.chanx_right_in(chanx_left_out_0),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.pReset(pReset),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.ccff_tail_0(ccff_tail_0),
.chanx_left_out(chanx_left_out),
.chanx_right_out(chanx_right_out),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
.top_width_0_height_0_subtile_0__pin_inpad_0_(top_width_0_height_0_subtile_0__pin_inpad_0_),
.top_width_0_height_0_subtile_1__pin_inpad_0_(top_width_0_height_0_subtile_1__pin_inpad_0_),
.top_width_0_height_0_subtile_2__pin_inpad_0_(top_width_0_height_0_subtile_2__pin_inpad_0_),
@ -129,8 +129,8 @@ module bottom_right_tile
.left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(top_width_0_height_0_subtile_1__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(top_width_0_height_0_subtile_2__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(top_width_0_height_0_subtile_3__pin_inpad_0_),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_),

42
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_tile.v
View File

@ -2,15 +2,15 @@
//netlist name: FPGA88_SOFA_A
module bottom_tile
(
IO_ISOL_N,
ccff_head,
ccff_head_1,
chanx_left_in,
chanx_right_in_0,
chany_top_in,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
pReset,
gfpga_pad_io_soc_in,
isol_n,
prog_clk,
prog_reset,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
@ -28,23 +28,23 @@ module bottom_tile
chanx_left_out,
chanx_right_out_0,
chany_top_out,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out,
top_width_0_height_0_subtile_0__pin_inpad_0_,
top_width_0_height_0_subtile_1__pin_inpad_0_,
top_width_0_height_0_subtile_2__pin_inpad_0_,
top_width_0_height_0_subtile_3__pin_inpad_0_
);
input IO_ISOL_N;
input ccff_head;
input ccff_head_1;
input [29:0]chanx_left_in;
input [29:0]chanx_right_in_0;
input [29:0]chany_top_in;
input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
input pReset;
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input prog_clk;
input prog_reset;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
@ -62,14 +62,13 @@ module bottom_tile
output [29:0]chanx_left_out;
output [29:0]chanx_right_out_0;
output [29:0]chany_top_out;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [3:0]gfpga_pad_io_soc_dir;
output [3:0]gfpga_pad_io_soc_out;
output top_width_0_height_0_subtile_0__pin_inpad_0_;
output top_width_0_height_0_subtile_1__pin_inpad_0_;
output top_width_0_height_0_subtile_2__pin_inpad_0_;
output top_width_0_height_0_subtile_3__pin_inpad_0_;
wire IO_ISOL_N;
wire ccff_head;
wire ccff_head_1;
wire ccff_tail;
@ -83,11 +82,12 @@ module bottom_tile
wire [29:0]chanx_right_out_0;
wire [29:0]chany_top_in;
wire [29:0]chany_top_out;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire pReset;
wire [3:0]gfpga_pad_io_soc_dir;
wire [3:0]gfpga_pad_io_soc_in;
wire [3:0]gfpga_pad_io_soc_out;
wire isol_n;
wire prog_clk;
wire prog_reset;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
@ -107,20 +107,20 @@ module bottom_tile
cbx_1__0_ cbx_1__0_
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(ccff_head),
.ccff_head_0(ccff_tail_1),
.chanx_left_in(chanx_left_in),
.chanx_right_in(chanx_left_out_0),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.pReset(pReset),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.ccff_tail_0(ccff_tail_0),
.chanx_left_out(chanx_left_out),
.chanx_right_out(chanx_right_out),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
.top_width_0_height_0_subtile_0__pin_inpad_0_(top_width_0_height_0_subtile_0__pin_inpad_0_),
.top_width_0_height_0_subtile_1__pin_inpad_0_(top_width_0_height_0_subtile_1__pin_inpad_0_),
.top_width_0_height_0_subtile_2__pin_inpad_0_(top_width_0_height_0_subtile_2__pin_inpad_0_),
@ -136,8 +136,8 @@ module bottom_tile
.left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(top_width_0_height_0_subtile_1__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(top_width_0_height_0_subtile_2__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(top_width_0_height_0_subtile_3__pin_inpad_0_),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_),

42
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/left_tile.v
View File

@ -2,15 +2,15 @@
//netlist name: FPGA88_SOFA_A
module left_tile
(
IO_ISOL_N,
ccff_head,
ccff_head_0,
chanx_right_in,
chany_bottom_in,
chany_top_in_0,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
pReset,
gfpga_pad_io_soc_in,
isol_n,
prog_clk,
prog_reset,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
@ -28,23 +28,23 @@ module left_tile
chanx_right_out,
chany_bottom_out,
chany_top_out_0,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out,
right_width_0_height_0_subtile_0__pin_inpad_0_,
right_width_0_height_0_subtile_1__pin_inpad_0_,
right_width_0_height_0_subtile_2__pin_inpad_0_,
right_width_0_height_0_subtile_3__pin_inpad_0_
);
input IO_ISOL_N;
input ccff_head;
input ccff_head_0;
input [29:0]chanx_right_in;
input [29:0]chany_bottom_in;
input [29:0]chany_top_in_0;
input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
input pReset;
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input prog_clk;
input prog_reset;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -62,14 +62,13 @@ module left_tile
output [29:0]chanx_right_out;
output [29:0]chany_bottom_out;
output [29:0]chany_top_out_0;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [3:0]gfpga_pad_io_soc_dir;
output [3:0]gfpga_pad_io_soc_out;
output right_width_0_height_0_subtile_0__pin_inpad_0_;
output right_width_0_height_0_subtile_1__pin_inpad_0_;
output right_width_0_height_0_subtile_2__pin_inpad_0_;
output right_width_0_height_0_subtile_3__pin_inpad_0_;
wire IO_ISOL_N;
wire ccff_head;
wire ccff_head_0;
wire ccff_tail;
@ -82,11 +81,12 @@ module left_tile
wire [29:0]chany_top_in_0;
wire [29:0]chany_top_out;
wire [29:0]chany_top_out_0;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire pReset;
wire [3:0]gfpga_pad_io_soc_dir;
wire [3:0]gfpga_pad_io_soc_in;
wire [3:0]gfpga_pad_io_soc_out;
wire isol_n;
wire prog_clk;
wire prog_reset;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -106,18 +106,18 @@ module left_tile
cby_0__1_ cby_0__1_
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head_0(ccff_head_0),
.chany_bottom_in(chany_bottom_in),
.chany_top_in(chany_bottom_out_0),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.pReset(pReset),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail),
.chany_bottom_out(chany_bottom_out),
.chany_top_out(chany_top_out),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
.right_width_0_height_0_subtile_0__pin_inpad_0_(right_width_0_height_0_subtile_0__pin_inpad_0_),
.right_width_0_height_0_subtile_1__pin_inpad_0_(right_width_0_height_0_subtile_1__pin_inpad_0_),
.right_width_0_height_0_subtile_2__pin_inpad_0_(right_width_0_height_0_subtile_2__pin_inpad_0_),
@ -133,8 +133,8 @@ module left_tile
.chanx_right_in(chanx_right_in),
.chany_bottom_in(chany_top_out),
.chany_top_in(chany_top_in_0),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_),

54
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/right_tile.v
View File

@ -2,19 +2,19 @@
//netlist name: FPGA88_SOFA_A
module right_tile
(
IO_ISOL_N,
Test_en,
ccff_head_0_0,
ccff_head_1,
ccff_head_2,
chanx_left_in,
chany_bottom_in,
chany_top_in_0,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_io_soc_in,
isol_n,
left_width_0_height_0_subtile_0__pin_clk_0_,
left_width_0_height_0_subtile_0__pin_reset_0_,
pReset,
prog_clk,
prog_reset,
scan_enable,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
@ -39,8 +39,8 @@ module right_tile
chanx_left_out,
chany_bottom_out,
chany_top_out_0,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out,
left_width_0_height_0_subtile_0__pin_inpad_0_,
left_width_0_height_0_subtile_1__pin_inpad_0_,
left_width_0_height_0_subtile_2__pin_inpad_0_,
@ -63,19 +63,19 @@ module right_tile
top_width_0_height_0_subtile_0__pin_O_7_
);
input IO_ISOL_N;
input Test_en;
input ccff_head_0_0;
input ccff_head_1;
input ccff_head_2;
input [29:0]chanx_left_in;
input [29:0]chany_bottom_in;
input [29:0]chany_top_in_0;
input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input left_width_0_height_0_subtile_0__pin_clk_0_;
input left_width_0_height_0_subtile_0__pin_reset_0_;
input pReset;
input prog_clk;
input prog_reset;
input scan_enable;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@ -100,8 +100,8 @@ module right_tile
output [29:0]chanx_left_out;
output [29:0]chany_bottom_out;
output [29:0]chany_top_out_0;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [3:0]gfpga_pad_io_soc_dir;
output [3:0]gfpga_pad_io_soc_out;
output left_width_0_height_0_subtile_0__pin_inpad_0_;
output left_width_0_height_0_subtile_1__pin_inpad_0_;
output left_width_0_height_0_subtile_2__pin_inpad_0_;
@ -123,8 +123,6 @@ module right_tile
output top_width_0_height_0_subtile_0__pin_O_6_;
output top_width_0_height_0_subtile_0__pin_O_7_;
wire IO_ISOL_N;
wire Test_en;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
@ -162,9 +160,10 @@ module right_tile
wire [29:0]chany_top_in_0;
wire [29:0]chany_top_out;
wire [29:0]chany_top_out_0;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire [3:0]gfpga_pad_io_soc_dir;
wire [3:0]gfpga_pad_io_soc_in;
wire [3:0]gfpga_pad_io_soc_out;
wire isol_n;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
@ -187,8 +186,8 @@ module right_tile
wire left_width_0_height_0_subtile_1__pin_inpad_0_;
wire left_width_0_height_0_subtile_2__pin_inpad_0_;
wire left_width_0_height_0_subtile_3__pin_inpad_0_;
wire pReset;
wire prog_clk;
wire prog_reset;
wire right_width_0_height_0_subtile_0__pin_O_10_;
wire right_width_0_height_0_subtile_0__pin_O_11_;
wire right_width_0_height_0_subtile_0__pin_O_12_;
@ -197,6 +196,7 @@ module right_tile
wire right_width_0_height_0_subtile_0__pin_O_15_;
wire right_width_0_height_0_subtile_0__pin_O_8_;
wire right_width_0_height_0_subtile_0__pin_O_9_;
wire scan_enable;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@ -226,8 +226,8 @@ module right_tile
.ccff_head(ccff_tail_2),
.chanx_left_in(chanx_left_in),
.chanx_right_in(chanx_left_out_0),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@ -250,20 +250,20 @@ module right_tile
);
cby_8__1_ cby_8__1_
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(ccff_head_1),
.ccff_head_0(ccff_head_0_0),
.chany_bottom_in(chany_bottom_in),
.chany_top_in(chany_bottom_out_0),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.pReset(pReset),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail_1),
.ccff_tail_0(ccff_tail_0_0),
.chany_bottom_out(chany_bottom_out),
.chany_top_out(chany_top_out),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
.left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
.left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
.left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),
@ -287,12 +287,11 @@ module right_tile
);
grid_clb grid_clb_8__1_
(
.Test_en(Test_en),
.ccff_head(ccff_tail_0_0),
.left_width_0_height_0_subtile_0__pin_clk_0_(left_width_0_height_0_subtile_0__pin_clk_0_),
.left_width_0_height_0_subtile_0__pin_reset_0_(left_width_0_height_0_subtile_0__pin_reset_0_),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
.right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
.right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),
@ -309,6 +308,7 @@ module right_tile
.right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
.right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
.right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
.scan_enable(scan_enable),
.top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
.top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
.top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@ -375,8 +375,8 @@ module right_tile
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(top_width_0_height_0_subtile_0__pin_O_5_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(top_width_0_height_0_subtile_0__pin_O_6_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(top_width_0_height_0_subtile_0__pin_O_7_),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_),

22
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/tile.v
View File

@ -2,7 +2,6 @@
//netlist name: FPGA88_SOFA_A
module tile
(
Test_en,
ccff_head_1,
ccff_head_2,
chanx_left_in,
@ -11,8 +10,8 @@ module tile
chany_top_in_0,
left_width_0_height_0_subtile_0__pin_clk_0_,
left_width_0_height_0_subtile_0__pin_reset_0_,
pReset,
prog_clk,
prog_reset,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
@ -21,6 +20,7 @@ module tile
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_,
scan_enable,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
@ -59,7 +59,6 @@ module tile
top_width_0_height_0_subtile_0__pin_O_7_
);
input Test_en;
input ccff_head_1;
input ccff_head_2;
input [29:0]chanx_left_in;
@ -68,8 +67,8 @@ module tile
input [29:0]chany_top_in_0;
input left_width_0_height_0_subtile_0__pin_clk_0_;
input left_width_0_height_0_subtile_0__pin_reset_0_;
input pReset;
input prog_clk;
input prog_reset;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -78,6 +77,7 @@ module tile
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_;
input scan_enable;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@ -115,7 +115,6 @@ module tile
output top_width_0_height_0_subtile_0__pin_O_6_;
output top_width_0_height_0_subtile_0__pin_O_7_;
wire Test_en;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
@ -171,8 +170,8 @@ module tile
wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
wire left_width_0_height_0_subtile_0__pin_clk_0_;
wire left_width_0_height_0_subtile_0__pin_reset_0_;
wire pReset;
wire prog_clk;
wire prog_reset;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -189,6 +188,7 @@ module tile
wire right_width_0_height_0_subtile_0__pin_O_15_;
wire right_width_0_height_0_subtile_0__pin_O_8_;
wire right_width_0_height_0_subtile_0__pin_O_9_;
wire scan_enable;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@ -214,8 +214,8 @@ module tile
.ccff_head(ccff_tail_2),
.chanx_left_in(chanx_left_in),
.chanx_right_in(chanx_left_out_0),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@ -241,8 +241,8 @@ module tile
.ccff_head(ccff_head_1),
.chany_bottom_in(chany_bottom_in),
.chany_top_in(chany_bottom_out_0),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail_1),
.chany_bottom_out(chany_bottom_out),
.chany_top_out(chany_top_out),
@ -265,12 +265,11 @@ module tile
);
grid_clb grid_clb_1__1_
(
.Test_en(Test_en),
.ccff_head(ccff_tail_1),
.left_width_0_height_0_subtile_0__pin_clk_0_(left_width_0_height_0_subtile_0__pin_clk_0_),
.left_width_0_height_0_subtile_0__pin_reset_0_(left_width_0_height_0_subtile_0__pin_reset_0_),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
.right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
.right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),
@ -287,6 +286,7 @@ module tile
.right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
.right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
.right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
.scan_enable(scan_enable),
.top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
.top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
.top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@ -350,8 +350,8 @@ module tile
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(top_width_0_height_0_subtile_0__pin_O_5_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(top_width_0_height_0_subtile_0__pin_O_6_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(top_width_0_height_0_subtile_0__pin_O_7_),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_),

42
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_left_tile.v
View File

@ -2,14 +2,14 @@
//netlist name: FPGA88_SOFA_A
module top_left_tile
(
IO_ISOL_N,
ccff_head,
ccff_head_0,
chanx_right_in,
chany_bottom_in_0,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
pReset,
gfpga_pad_io_soc_in,
isol_n,
prog_clk,
prog_reset,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
@ -26,22 +26,22 @@ module top_left_tile
ccff_tail_0,
chanx_right_out,
chany_bottom_out_0,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out,
right_width_0_height_0_subtile_0__pin_inpad_0_,
right_width_0_height_0_subtile_1__pin_inpad_0_,
right_width_0_height_0_subtile_2__pin_inpad_0_,
right_width_0_height_0_subtile_3__pin_inpad_0_
);
input IO_ISOL_N;
input ccff_head;
input ccff_head_0;
input [29:0]chanx_right_in;
input [29:0]chany_bottom_in_0;
input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
input pReset;
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input prog_clk;
input prog_reset;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -58,14 +58,13 @@ module top_left_tile
output ccff_tail_0;
output [29:0]chanx_right_out;
output [29:0]chany_bottom_out_0;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [3:0]gfpga_pad_io_soc_dir;
output [3:0]gfpga_pad_io_soc_out;
output right_width_0_height_0_subtile_0__pin_inpad_0_;
output right_width_0_height_0_subtile_1__pin_inpad_0_;
output right_width_0_height_0_subtile_2__pin_inpad_0_;
output right_width_0_height_0_subtile_3__pin_inpad_0_;
wire IO_ISOL_N;
wire ccff_head;
wire ccff_head_0;
wire ccff_tail;
@ -76,11 +75,12 @@ module top_left_tile
wire [29:0]chany_bottom_out;
wire [29:0]chany_bottom_out_0;
wire [29:0]chany_top_out;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire pReset;
wire [3:0]gfpga_pad_io_soc_dir;
wire [3:0]gfpga_pad_io_soc_in;
wire [3:0]gfpga_pad_io_soc_out;
wire isol_n;
wire prog_clk;
wire prog_reset;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -100,18 +100,18 @@ module top_left_tile
cby_0__1_ cby_0__8_
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head_0(ccff_head_0),
.chany_bottom_in(chany_bottom_in_0),
.chany_top_in(chany_bottom_out),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.pReset(pReset),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail_0),
.chany_bottom_out(chany_bottom_out_0),
.chany_top_out(chany_top_out),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
.right_width_0_height_0_subtile_0__pin_inpad_0_(right_width_0_height_0_subtile_0__pin_inpad_0_),
.right_width_0_height_0_subtile_1__pin_inpad_0_(right_width_0_height_0_subtile_1__pin_inpad_0_),
.right_width_0_height_0_subtile_2__pin_inpad_0_(right_width_0_height_0_subtile_2__pin_inpad_0_),
@ -126,8 +126,8 @@ module top_left_tile
.ccff_head(ccff_head),
.chanx_right_in(chanx_right_in),
.chany_bottom_in(chany_top_out),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_),

80
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_right_tile.v
View File

@ -2,18 +2,18 @@
//netlist name: FPGA88_SOFA_A
module top_right_tile
(
IO_ISOL_N,
Test_en,
ccff_head_0_0,
ccff_head_1,
chanx_left_in,
chany_bottom_in,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN_0,
gfpga_pad_io_soc_in,
gfpga_pad_io_soc_in_0,
isol_n,
left_width_0_height_0_subtile_0__pin_clk_0_,
left_width_0_height_0_subtile_0__pin_reset_0_,
pReset,
prog_clk,
prog_reset,
scan_enable,
top_width_0_height_0_subtile_0__pin_cin_0_,
top_width_0_height_0_subtile_0__pin_reg_in_0_,
top_width_0_height_0_subtile_0__pin_sc_in_0_,
@ -28,10 +28,10 @@ module top_right_tile
ccff_tail_0,
chanx_left_out,
chany_bottom_out,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR_0,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_0,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_dir_0,
gfpga_pad_io_soc_out,
gfpga_pad_io_soc_out_0,
left_width_0_height_0_subtile_0__pin_inpad_0_,
left_width_0_height_0_subtile_1__pin_inpad_0_,
left_width_0_height_0_subtile_2__pin_inpad_0_,
@ -54,18 +54,18 @@ module top_right_tile
top_width_0_height_0_subtile_0__pin_O_7_
);
input IO_ISOL_N;
input Test_en;
input ccff_head_0_0;
input ccff_head_1;
input [29:0]chanx_left_in;
input [29:0]chany_bottom_in;
input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN_0;
input [3:0]gfpga_pad_io_soc_in;
input [3:0]gfpga_pad_io_soc_in_0;
input isol_n;
input left_width_0_height_0_subtile_0__pin_clk_0_;
input left_width_0_height_0_subtile_0__pin_reset_0_;
input pReset;
input prog_clk;
input prog_reset;
input scan_enable;
input top_width_0_height_0_subtile_0__pin_cin_0_;
input top_width_0_height_0_subtile_0__pin_reg_in_0_;
input top_width_0_height_0_subtile_0__pin_sc_in_0_;
@ -80,10 +80,10 @@ module top_right_tile
output ccff_tail_0;
output [29:0]chanx_left_out;
output [29:0]chany_bottom_out;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR_0;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_0;
output [3:0]gfpga_pad_io_soc_dir;
output [3:0]gfpga_pad_io_soc_dir_0;
output [3:0]gfpga_pad_io_soc_out;
output [3:0]gfpga_pad_io_soc_out_0;
output left_width_0_height_0_subtile_0__pin_inpad_0_;
output left_width_0_height_0_subtile_1__pin_inpad_0_;
output left_width_0_height_0_subtile_2__pin_inpad_0_;
@ -105,8 +105,6 @@ module top_right_tile
output top_width_0_height_0_subtile_0__pin_O_6_;
output top_width_0_height_0_subtile_0__pin_O_7_;
wire IO_ISOL_N;
wire Test_en;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
@ -145,12 +143,13 @@ module top_right_tile
wire [29:0]chany_bottom_out;
wire [29:0]chany_bottom_out_0;
wire [29:0]chany_top_out;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR_0;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN_0;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_0;
wire [3:0]gfpga_pad_io_soc_dir;
wire [3:0]gfpga_pad_io_soc_dir_0;
wire [3:0]gfpga_pad_io_soc_in;
wire [3:0]gfpga_pad_io_soc_in_0;
wire [3:0]gfpga_pad_io_soc_out;
wire [3:0]gfpga_pad_io_soc_out_0;
wire isol_n;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
@ -173,8 +172,8 @@ module top_right_tile
wire left_width_0_height_0_subtile_1__pin_inpad_0_;
wire left_width_0_height_0_subtile_2__pin_inpad_0_;
wire left_width_0_height_0_subtile_3__pin_inpad_0_;
wire pReset;
wire prog_clk;
wire prog_reset;
wire right_width_0_height_0_subtile_0__pin_O_10_;
wire right_width_0_height_0_subtile_0__pin_O_11_;
wire right_width_0_height_0_subtile_0__pin_O_12_;
@ -183,6 +182,7 @@ module top_right_tile
wire right_width_0_height_0_subtile_0__pin_O_15_;
wire right_width_0_height_0_subtile_0__pin_O_8_;
wire right_width_0_height_0_subtile_0__pin_O_9_;
wire scan_enable;
wire top_width_0_height_0_subtile_0__pin_O_0_;
wire top_width_0_height_0_subtile_0__pin_O_1_;
wire top_width_0_height_0_subtile_0__pin_O_2_;
@ -197,13 +197,13 @@ module top_right_tile
cbx_1__8_ cbx_8__8_
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head_0(ccff_tail_2),
.chanx_left_in(chanx_left_in),
.chanx_right_in(chanx_left_out_0),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.pReset(pReset),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@ -227,25 +227,25 @@ module top_right_tile
.ccff_tail(ccff_tail_0),
.chanx_left_out(chanx_left_out),
.chanx_right_out(chanx_right_out),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT)
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out)
);
cby_8__1_ cby_8__8_
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head(ccff_head_1),
.ccff_head_0(ccff_head_0_0),
.chany_bottom_in(chany_bottom_in),
.chany_top_in(chany_bottom_out_0),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN_0),
.pReset(pReset),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in_0),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail_1),
.ccff_tail_0(ccff_tail_0_0),
.chany_bottom_out(chany_bottom_out),
.chany_top_out(chany_top_out),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR_0),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_0),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir_0),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out_0),
.left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
.left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
.left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),
@ -269,12 +269,11 @@ module top_right_tile
);
grid_clb grid_clb_8__8_
(
.Test_en(Test_en),
.ccff_head(ccff_tail_0_0),
.left_width_0_height_0_subtile_0__pin_clk_0_(left_width_0_height_0_subtile_0__pin_clk_0_),
.left_width_0_height_0_subtile_0__pin_reset_0_(left_width_0_height_0_subtile_0__pin_reset_0_),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
.right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
.right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),
@ -291,6 +290,7 @@ module top_right_tile
.right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
.right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
.right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
.scan_enable(scan_enable),
.top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
.top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
.top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@ -360,8 +360,8 @@ module top_right_tile
.left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(bottom_width_0_height_0_subtile_2__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(bottom_width_0_height_0_subtile_3__pin_inpad_0_),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail_2),
.chanx_left_out(chanx_left_out_0),
.chany_bottom_out(chany_bottom_out_0)

54
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_tile.v
View File

@ -2,18 +2,17 @@
//netlist name: FPGA88_SOFA_A
module top_tile
(
IO_ISOL_N,
Test_en,
ccff_head_1,
ccff_head_2,
chanx_left_in,
chanx_right_in_0,
chany_bottom_in,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_io_soc_in,
isol_n,
left_width_0_height_0_subtile_0__pin_clk_0_,
left_width_0_height_0_subtile_0__pin_reset_0_,
pReset,
prog_clk,
prog_reset,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
@ -26,6 +25,7 @@ module top_tile
right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
scan_enable,
top_width_0_height_0_subtile_0__pin_cin_0_,
top_width_0_height_0_subtile_0__pin_reg_in_0_,
top_width_0_height_0_subtile_0__pin_sc_in_0_,
@ -41,8 +41,8 @@ module top_tile
chanx_left_out,
chanx_right_out_0,
chany_bottom_out,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_io_soc_dir,
gfpga_pad_io_soc_out,
right_width_0_height_0_subtile_0__pin_O_10_,
right_width_0_height_0_subtile_0__pin_O_11_,
right_width_0_height_0_subtile_0__pin_O_12_,
@ -61,18 +61,17 @@ module top_tile
top_width_0_height_0_subtile_0__pin_O_7_
);
input IO_ISOL_N;
input Test_en;
input ccff_head_1;
input ccff_head_2;
input [29:0]chanx_left_in;
input [29:0]chanx_right_in_0;
input [29:0]chany_bottom_in;
input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
input [3:0]gfpga_pad_io_soc_in;
input isol_n;
input left_width_0_height_0_subtile_0__pin_clk_0_;
input left_width_0_height_0_subtile_0__pin_reset_0_;
input pReset;
input prog_clk;
input prog_reset;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -85,6 +84,7 @@ module top_tile
input right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
input right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
input right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
input scan_enable;
input top_width_0_height_0_subtile_0__pin_cin_0_;
input top_width_0_height_0_subtile_0__pin_reg_in_0_;
input top_width_0_height_0_subtile_0__pin_sc_in_0_;
@ -100,8 +100,8 @@ module top_tile
output [29:0]chanx_left_out;
output [29:0]chanx_right_out_0;
output [29:0]chany_bottom_out;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [3:0]gfpga_pad_io_soc_dir;
output [3:0]gfpga_pad_io_soc_out;
output right_width_0_height_0_subtile_0__pin_O_10_;
output right_width_0_height_0_subtile_0__pin_O_11_;
output right_width_0_height_0_subtile_0__pin_O_12_;
@ -119,8 +119,6 @@ module top_tile
output top_width_0_height_0_subtile_0__pin_O_6_;
output top_width_0_height_0_subtile_0__pin_O_7_;
wire IO_ISOL_N;
wire Test_en;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
@ -160,9 +158,10 @@ module top_tile
wire [29:0]chany_bottom_out;
wire [29:0]chany_bottom_out_0;
wire [29:0]chany_top_out;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire [3:0]gfpga_pad_io_soc_dir;
wire [3:0]gfpga_pad_io_soc_in;
wire [3:0]gfpga_pad_io_soc_out;
wire isol_n;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
@ -181,8 +180,8 @@ module top_tile
wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
wire left_width_0_height_0_subtile_0__pin_clk_0_;
wire left_width_0_height_0_subtile_0__pin_reset_0_;
wire pReset;
wire prog_clk;
wire prog_reset;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@ -203,6 +202,7 @@ module top_tile
wire right_width_0_height_0_subtile_0__pin_O_15_;
wire right_width_0_height_0_subtile_0__pin_O_8_;
wire right_width_0_height_0_subtile_0__pin_O_9_;
wire scan_enable;
wire top_width_0_height_0_subtile_0__pin_O_0_;
wire top_width_0_height_0_subtile_0__pin_O_1_;
wire top_width_0_height_0_subtile_0__pin_O_2_;
@ -217,13 +217,13 @@ module top_tile
cbx_1__8_ cbx_1__8_
(
.IO_ISOL_N(IO_ISOL_N),
.ccff_head_0(ccff_tail_2),
.chanx_left_in(chanx_left_in),
.chanx_right_in(chanx_left_out_0),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.pReset(pReset),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
.isol_n(isol_n),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@ -247,16 +247,16 @@ module top_tile
.ccff_tail(ccff_tail_0),
.chanx_left_out(chanx_left_out),
.chanx_right_out(chanx_right_out),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT)
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out)
);
cby_1__1_ cby_1__8_
(
.ccff_head(ccff_head_1),
.chany_bottom_in(chany_bottom_in),
.chany_top_in(chany_bottom_out_0),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.ccff_tail(ccff_tail_1),
.chany_bottom_out(chany_bottom_out),
.chany_top_out(chany_top_out),
@ -279,12 +279,11 @@ module top_tile
);
grid_clb grid_clb_1__8_
(
.Test_en(Test_en),
.ccff_head(ccff_tail_1),
.left_width_0_height_0_subtile_0__pin_clk_0_(left_width_0_height_0_subtile_0__pin_clk_0_),
.left_width_0_height_0_subtile_0__pin_reset_0_(left_width_0_height_0_subtile_0__pin_reset_0_),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
.right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
.right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),
@ -301,6 +300,7 @@ module top_tile
.right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
.right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
.right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
.scan_enable(scan_enable),
.top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
.top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
.top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@ -367,8 +367,8 @@ module top_tile
.left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(bottom_width_0_height_0_subtile_2__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(bottom_width_0_height_0_subtile_3__pin_inpad_0_),
.pReset(pReset),
.prog_clk(prog_clk),
.prog_reset(prog_reset),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_),

1196
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/fpga_top.v
View File

File diff suppressed because it is too large Load Diff

16
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_clb.v
View File

@ -2,9 +2,9 @@
//netlist name: FPGA88_SOFA_A
module grid_clb
(
pReset,
prog_reset,
prog_clk,
Test_en,
scan_enable,
top_width_0_height_0_subtile_0__pin_I0_0_,
top_width_0_height_0_subtile_0__pin_I0_1_,
top_width_0_height_0_subtile_0__pin_I0i_0_,
@ -65,9 +65,9 @@ module grid_clb
ccff_tail
);
input pReset;
input prog_reset;
input prog_clk;
input Test_en;
input scan_enable;
input top_width_0_height_0_subtile_0__pin_I0_0_;
input top_width_0_height_0_subtile_0__pin_I0_1_;
input top_width_0_height_0_subtile_0__pin_I0i_0_;
@ -127,9 +127,9 @@ module grid_clb
output bottom_width_0_height_0_subtile_0__pin_cout_0_;
output ccff_tail;
wire pReset;
wire prog_reset;
wire prog_clk;
wire Test_en;
wire scan_enable;
wire top_width_0_height_0_subtile_0__pin_I0_0_;
wire top_width_0_height_0_subtile_0__pin_I0_1_;
wire top_width_0_height_0_subtile_0__pin_I0i_0_;
@ -191,9 +191,9 @@ module grid_clb
logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.scan_enable(scan_enable),
.clb_I0({top_width_0_height_0_subtile_0__pin_I0_0_, top_width_0_height_0_subtile_0__pin_I0_1_}),
.clb_I0i({top_width_0_height_0_subtile_0__pin_I0i_0_, top_width_0_height_0_subtile_0__pin_I0i_1_}),
.clb_I1({top_width_0_height_0_subtile_0__pin_I1_0_, top_width_0_height_0_subtile_0__pin_I1_1_}),

70
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_bottom_bottom.v
View File

@ -2,12 +2,12 @@
//netlist name: FPGA88_SOFA_A
module grid_io_bottom_bottom
(
IO_ISOL_N,
pReset,
isol_n,
prog_reset,
prog_clk,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_io_soc_in,
gfpga_pad_io_soc_out,
gfpga_pad_io_soc_dir,
top_width_0_height_0_subtile_0__pin_outpad_0_,
top_width_0_height_0_subtile_1__pin_outpad_0_,
top_width_0_height_0_subtile_2__pin_outpad_0_,
@ -20,12 +20,12 @@ module grid_io_bottom_bottom
ccff_tail
);
input IO_ISOL_N;
input pReset;
input isol_n;
input prog_reset;
input prog_clk;
input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
input [0:3]gfpga_pad_io_soc_in;
output [0:3]gfpga_pad_io_soc_out;
output [0:3]gfpga_pad_io_soc_dir;
input top_width_0_height_0_subtile_0__pin_outpad_0_;
input top_width_0_height_0_subtile_1__pin_outpad_0_;
input top_width_0_height_0_subtile_2__pin_outpad_0_;
@ -37,12 +37,12 @@ module grid_io_bottom_bottom
output top_width_0_height_0_subtile_3__pin_inpad_0_;
output ccff_tail;
wire IO_ISOL_N;
wire pReset;
wire isol_n;
wire prog_reset;
wire prog_clk;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire [0:3]gfpga_pad_io_soc_in;
wire [0:3]gfpga_pad_io_soc_out;
wire [0:3]gfpga_pad_io_soc_dir;
wire top_width_0_height_0_subtile_0__pin_outpad_0_;
wire top_width_0_height_0_subtile_1__pin_outpad_0_;
wire top_width_0_height_0_subtile_2__pin_outpad_0_;
@ -59,12 +59,12 @@ module grid_io_bottom_bottom
logical_tile_io_mode_io_ logical_tile_io_mode_io__0
(
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
.io_outpad(top_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(top_width_0_height_0_subtile_0__pin_inpad_0_),
@ -72,12 +72,12 @@ module grid_io_bottom_bottom
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__1
(
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
.io_outpad(top_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_1__pin_inpad_0_),
@ -85,12 +85,12 @@ module grid_io_bottom_bottom
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__2
(
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
.io_outpad(top_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_2__pin_inpad_0_),
@ -98,12 +98,12 @@ module grid_io_bottom_bottom
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__3
(
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
.io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_),

70
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_left_left.v
View File

@ -2,12 +2,12 @@
//netlist name: FPGA88_SOFA_A
module grid_io_left_left
(
IO_ISOL_N,
pReset,
isol_n,
prog_reset,
prog_clk,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_io_soc_in,
gfpga_pad_io_soc_out,
gfpga_pad_io_soc_dir,
right_width_0_height_0_subtile_0__pin_outpad_0_,
right_width_0_height_0_subtile_1__pin_outpad_0_,
right_width_0_height_0_subtile_2__pin_outpad_0_,
@ -20,12 +20,12 @@ module grid_io_left_left
ccff_tail
);
input IO_ISOL_N;
input pReset;
input isol_n;
input prog_reset;
input prog_clk;
input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
input [0:3]gfpga_pad_io_soc_in;
output [0:3]gfpga_pad_io_soc_out;
output [0:3]gfpga_pad_io_soc_dir;
input right_width_0_height_0_subtile_0__pin_outpad_0_;
input right_width_0_height_0_subtile_1__pin_outpad_0_;
input right_width_0_height_0_subtile_2__pin_outpad_0_;
@ -37,12 +37,12 @@ module grid_io_left_left
output right_width_0_height_0_subtile_3__pin_inpad_0_;
output ccff_tail;
wire IO_ISOL_N;
wire pReset;
wire isol_n;
wire prog_reset;
wire prog_clk;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire [0:3]gfpga_pad_io_soc_in;
wire [0:3]gfpga_pad_io_soc_out;
wire [0:3]gfpga_pad_io_soc_dir;
wire right_width_0_height_0_subtile_0__pin_outpad_0_;
wire right_width_0_height_0_subtile_1__pin_outpad_0_;
wire right_width_0_height_0_subtile_2__pin_outpad_0_;
@ -59,12 +59,12 @@ module grid_io_left_left
logical_tile_io_mode_io_ logical_tile_io_mode_io__0
(
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
.io_outpad(right_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(right_width_0_height_0_subtile_0__pin_inpad_0_),
@ -72,12 +72,12 @@ module grid_io_left_left
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__1
(
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
.io_outpad(right_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_1__pin_inpad_0_),
@ -85,12 +85,12 @@ module grid_io_left_left
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__2
(
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
.io_outpad(right_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_2__pin_inpad_0_),
@ -98,12 +98,12 @@ module grid_io_left_left
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__3
(
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
.io_outpad(right_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_3__pin_inpad_0_),

70
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_right_right.v
View File

@ -2,12 +2,12 @@
//netlist name: FPGA88_SOFA_A
module grid_io_right_right
(
IO_ISOL_N,
pReset,
isol_n,
prog_reset,
prog_clk,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_io_soc_in,
gfpga_pad_io_soc_out,
gfpga_pad_io_soc_dir,
left_width_0_height_0_subtile_0__pin_outpad_0_,
left_width_0_height_0_subtile_1__pin_outpad_0_,
left_width_0_height_0_subtile_2__pin_outpad_0_,
@ -20,12 +20,12 @@ module grid_io_right_right
ccff_tail
);
input IO_ISOL_N;
input pReset;
input isol_n;
input prog_reset;
input prog_clk;
input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
input [0:3]gfpga_pad_io_soc_in;
output [0:3]gfpga_pad_io_soc_out;
output [0:3]gfpga_pad_io_soc_dir;
input left_width_0_height_0_subtile_0__pin_outpad_0_;
input left_width_0_height_0_subtile_1__pin_outpad_0_;
input left_width_0_height_0_subtile_2__pin_outpad_0_;
@ -37,12 +37,12 @@ module grid_io_right_right
output left_width_0_height_0_subtile_3__pin_inpad_0_;
output ccff_tail;
wire IO_ISOL_N;
wire pReset;
wire isol_n;
wire prog_reset;
wire prog_clk;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire [0:3]gfpga_pad_io_soc_in;
wire [0:3]gfpga_pad_io_soc_out;
wire [0:3]gfpga_pad_io_soc_dir;
wire left_width_0_height_0_subtile_0__pin_outpad_0_;
wire left_width_0_height_0_subtile_1__pin_outpad_0_;
wire left_width_0_height_0_subtile_2__pin_outpad_0_;
@ -59,12 +59,12 @@ module grid_io_right_right
logical_tile_io_mode_io_ logical_tile_io_mode_io__0
(
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
.io_outpad(left_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(left_width_0_height_0_subtile_0__pin_inpad_0_),
@ -72,12 +72,12 @@ module grid_io_right_right
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__1
(
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
.io_outpad(left_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_1__pin_inpad_0_),
@ -85,12 +85,12 @@ module grid_io_right_right
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__2
(
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
.io_outpad(left_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_2__pin_inpad_0_),
@ -98,12 +98,12 @@ module grid_io_right_right
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__3
(
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
.io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_),

70
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_top_top.v
View File

@ -2,12 +2,12 @@
//netlist name: FPGA88_SOFA_A
module grid_io_top_top
(
IO_ISOL_N,
pReset,
isol_n,
prog_reset,
prog_clk,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_io_soc_in,
gfpga_pad_io_soc_out,
gfpga_pad_io_soc_dir,
bottom_width_0_height_0_subtile_0__pin_outpad_0_,
bottom_width_0_height_0_subtile_1__pin_outpad_0_,
bottom_width_0_height_0_subtile_2__pin_outpad_0_,
@ -20,12 +20,12 @@ module grid_io_top_top
ccff_tail
);
input IO_ISOL_N;
input pReset;
input isol_n;
input prog_reset;
input prog_clk;
input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
input [0:3]gfpga_pad_io_soc_in;
output [0:3]gfpga_pad_io_soc_out;
output [0:3]gfpga_pad_io_soc_dir;
input bottom_width_0_height_0_subtile_0__pin_outpad_0_;
input bottom_width_0_height_0_subtile_1__pin_outpad_0_;
input bottom_width_0_height_0_subtile_2__pin_outpad_0_;
@ -37,12 +37,12 @@ module grid_io_top_top
output bottom_width_0_height_0_subtile_3__pin_inpad_0_;
output ccff_tail;
wire IO_ISOL_N;
wire pReset;
wire isol_n;
wire prog_reset;
wire prog_clk;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire [0:3]gfpga_pad_io_soc_in;
wire [0:3]gfpga_pad_io_soc_out;
wire [0:3]gfpga_pad_io_soc_dir;
wire bottom_width_0_height_0_subtile_0__pin_outpad_0_;
wire bottom_width_0_height_0_subtile_1__pin_outpad_0_;
wire bottom_width_0_height_0_subtile_2__pin_outpad_0_;
@ -59,12 +59,12 @@ module grid_io_top_top
logical_tile_io_mode_io_ logical_tile_io_mode_io__0
(
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
.io_outpad(bottom_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@ -72,12 +72,12 @@ module grid_io_top_top
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__1
(
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
.io_outpad(bottom_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_1__pin_inpad_0_),
@ -85,12 +85,12 @@ module grid_io_top_top
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__2
(
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
.io_outpad(bottom_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_2__pin_inpad_0_),
@ -98,12 +98,12 @@ module grid_io_top_top
);
logical_tile_io_mode_io_ logical_tile_io_mode_io__3
(
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
.io_outpad(bottom_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_3__pin_inpad_0_),

44
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_clb_.v
View File

@ -2,9 +2,9 @@
//netlist name: FPGA88_SOFA_A
module logical_tile_clb_mode_clb_
(
pReset,
prog_reset,
prog_clk,
Test_en,
scan_enable,
clb_I0,
clb_I0i,
clb_I1,
@ -34,9 +34,9 @@ module logical_tile_clb_mode_clb_
ccff_tail
);
input pReset;
input prog_reset;
input prog_clk;
input Test_en;
input scan_enable;
input [0:1]clb_I0;
input [0:1]clb_I0i;
input [0:1]clb_I1;
@ -65,9 +65,9 @@ module logical_tile_clb_mode_clb_
output clb_cout;
output ccff_tail;
wire pReset;
wire prog_reset;
wire prog_clk;
wire Test_en;
wire scan_enable;
wire [0:1]clb_I0;
wire [0:1]clb_I0i;
wire [0:1]clb_I1;
@ -209,9 +209,9 @@ module logical_tile_clb_mode_clb_
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.scan_enable(scan_enable),
.fle_in({direct_interc_19_out, direct_interc_20_out, direct_interc_21_out, direct_interc_22_out}),
.fle_reg_in(direct_interc_23_out),
.fle_sc_in(direct_interc_24_out),
@ -227,9 +227,9 @@ module logical_tile_clb_mode_clb_
);
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.scan_enable(scan_enable),
.fle_in({direct_interc_28_out, direct_interc_29_out, direct_interc_30_out, direct_interc_31_out}),
.fle_reg_in(direct_interc_32_out),
.fle_sc_in(direct_interc_33_out),
@ -245,9 +245,9 @@ module logical_tile_clb_mode_clb_
);
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.scan_enable(scan_enable),
.fle_in({direct_interc_37_out, direct_interc_38_out, direct_interc_39_out, direct_interc_40_out}),
.fle_reg_in(direct_interc_41_out),
.fle_sc_in(direct_interc_42_out),
@ -263,9 +263,9 @@ module logical_tile_clb_mode_clb_
);
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.scan_enable(scan_enable),
.fle_in({direct_interc_46_out, direct_interc_47_out, direct_interc_48_out, direct_interc_49_out}),
.fle_reg_in(direct_interc_50_out),
.fle_sc_in(direct_interc_51_out),
@ -281,9 +281,9 @@ module logical_tile_clb_mode_clb_
);
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.scan_enable(scan_enable),
.fle_in({direct_interc_55_out, direct_interc_56_out, direct_interc_57_out, direct_interc_58_out}),
.fle_reg_in(direct_interc_59_out),
.fle_sc_in(direct_interc_60_out),
@ -299,9 +299,9 @@ module logical_tile_clb_mode_clb_
);
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.scan_enable(scan_enable),
.fle_in({direct_interc_64_out, direct_interc_65_out, direct_interc_66_out, direct_interc_67_out}),
.fle_reg_in(direct_interc_68_out),
.fle_sc_in(direct_interc_69_out),
@ -317,9 +317,9 @@ module logical_tile_clb_mode_clb_
);
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.scan_enable(scan_enable),
.fle_in({direct_interc_73_out, direct_interc_74_out, direct_interc_75_out, direct_interc_76_out}),
.fle_reg_in(direct_interc_77_out),
.fle_sc_in(direct_interc_78_out),
@ -335,9 +335,9 @@ module logical_tile_clb_mode_clb_
);
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.scan_enable(scan_enable),
.fle_in({direct_interc_82_out, direct_interc_83_out, direct_interc_84_out, direct_interc_85_out}),
.fle_reg_in(direct_interc_86_out),
.fle_sc_in(direct_interc_87_out),

16
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle.v
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@ -2,9 +2,9 @@
//netlist name: FPGA88_SOFA_A
module logical_tile_clb_mode_default__fle
(
pReset,
prog_reset,
prog_clk,
Test_en,
scan_enable,
fle_in,
fle_reg_in,
fle_sc_in,
@ -19,9 +19,9 @@ module logical_tile_clb_mode_default__fle
ccff_tail
);
input pReset;
input prog_reset;
input prog_clk;
input Test_en;
input scan_enable;
input [0:3]fle_in;
input fle_reg_in;
input fle_sc_in;
@ -35,9 +35,9 @@ module logical_tile_clb_mode_default__fle
output fle_cout;
output ccff_tail;
wire pReset;
wire prog_reset;
wire prog_clk;
wire Test_en;
wire scan_enable;
wire [0:3]fle_in;
wire fle_reg_in;
wire fle_sc_in;
@ -66,9 +66,9 @@ module logical_tile_clb_mode_default__fle
logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.scan_enable(scan_enable),
.fabric_in({direct_interc_5_out, direct_interc_6_out, direct_interc_7_out, direct_interc_8_out}),
.fabric_reg_in(direct_interc_9_out),
.fabric_sc_in(direct_interc_10_out),

26
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
View File

@ -2,9 +2,9 @@
//netlist name: FPGA88_SOFA_A
module logical_tile_clb_mode_default__fle_mode_physical__fabric
(
pReset,
prog_reset,
prog_clk,
Test_en,
scan_enable,
fabric_in,
fabric_reg_in,
fabric_sc_in,
@ -19,9 +19,9 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
ccff_tail
);
input pReset;
input prog_reset;
input prog_clk;
input Test_en;
input scan_enable;
input [0:3]fabric_in;
input fabric_reg_in;
input fabric_sc_in;
@ -35,9 +35,9 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
output fabric_cout;
output ccff_tail;
wire pReset;
wire prog_reset;
wire prog_clk;
wire Test_en;
wire scan_enable;
wire [0:3]fabric_in;
wire fabric_reg_in;
wire fabric_sc_in;
@ -82,7 +82,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.frac_logic_in({direct_interc_3_out, direct_interc_4_out, direct_interc_5_out, direct_interc_6_out}),
.frac_logic_cin(direct_interc_7_out),
@ -93,7 +93,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
);
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0
(
.Test_en(Test_en),
.scan_enable(scan_enable),
.ff_D(mux_tree_size2_2_out),
.ff_DI(direct_interc_8_out),
.ff_reset(direct_interc_9_out),
@ -102,7 +102,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
);
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1
(
.Test_en(Test_en),
.scan_enable(scan_enable),
.ff_D(mux_tree_size2_3_out),
.ff_DI(direct_interc_11_out),
.ff_reset(direct_interc_12_out),
@ -139,7 +139,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
);
mux_tree_size2_mem mem_fabric_out_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail),
.ccff_tail(mux_tree_size2_mem_0_ccff_tail),
@ -147,7 +147,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
);
mux_tree_size2_mem mem_fabric_out_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_size2_mem_1_ccff_tail),
@ -155,7 +155,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
);
mux_tree_size2_mem mem_ff_0_D_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_size2_mem_2_ccff_tail),
@ -163,7 +163,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
);
mux_tree_size2_mem mem_ff_1_D_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_size2_mem_2_ccff_tail),
.ccff_tail(ccff_tail),

8
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v
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@ -2,7 +2,7 @@
//netlist name: FPGA88_SOFA_A
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
(
Test_en,
scan_enable,
ff_D,
ff_DI,
ff_reset,
@ -10,14 +10,14 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
ff_clk
);
input Test_en;
input scan_enable;
input ff_D;
input ff_DI;
input ff_reset;
output ff_Q;
input ff_clk;
wire Test_en;
wire scan_enable;
wire ff_D;
wire ff_DI;
wire ff_reset;
@ -26,7 +26,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_
(
.SCE(Test_en),
.SCE(scan_enable),
.D(ff_D),
.SCD(ff_DI),
.RESET_B(ff_reset),

12
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v
View File

@ -2,7 +2,7 @@
//netlist name: FPGA88_SOFA_A
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic
(
pReset,
prog_reset,
prog_clk,
frac_logic_in,
frac_logic_cin,
@ -12,7 +12,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
ccff_tail
);
input pReset;
input prog_reset;
input prog_clk;
input [0:3]frac_logic_in;
input frac_logic_cin;
@ -21,7 +21,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
output frac_logic_cout;
output ccff_tail;
wire pReset;
wire prog_reset;
wire prog_clk;
wire [0:3]frac_logic_in;
wire frac_logic_cin;
@ -49,7 +49,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.frac_lut4_in({direct_interc_2_out, direct_interc_3_out, mux_tree_size2_1_out, direct_interc_4_out}),
.ccff_head(ccff_head),
@ -81,7 +81,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
);
mux_tree_size2_mem mem_frac_logic_out_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail),
.ccff_tail(mux_tree_size2_mem_0_ccff_tail),
@ -89,7 +89,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
);
mux_tree_size2_mem mem_frac_lut4_0_in_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_size2_mem_0_ccff_tail),
.ccff_tail(ccff_tail),

8
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v
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@ -2,7 +2,7 @@
//netlist name: FPGA88_SOFA_A
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4
(
pReset,
prog_reset,
prog_clk,
frac_lut4_in,
ccff_head,
@ -12,7 +12,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
ccff_tail
);
input pReset;
input prog_reset;
input prog_clk;
input [0:3]frac_lut4_in;
input ccff_head;
@ -21,7 +21,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
output frac_lut4_lut4_out;
output ccff_tail;
wire pReset;
wire prog_reset;
wire prog_clk;
wire [0:3]frac_lut4_in;
wire ccff_head;
@ -47,7 +47,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
);
frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(ccff_tail),

40
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_io_mode_io_.v
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@ -2,35 +2,35 @@
//netlist name: FPGA88_SOFA_A
module logical_tile_io_mode_io_
(
IO_ISOL_N,
pReset,
isol_n,
prog_reset,
prog_clk,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_io_soc_in,
gfpga_pad_io_soc_out,
gfpga_pad_io_soc_dir,
io_outpad,
ccff_head,
io_inpad,
ccff_tail
);
input IO_ISOL_N;
input pReset;
input isol_n;
input prog_reset;
input prog_clk;
input gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
output gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
input gfpga_pad_io_soc_in;
output gfpga_pad_io_soc_out;
output gfpga_pad_io_soc_dir;
input io_outpad;
input ccff_head;
output io_inpad;
output ccff_tail;
wire IO_ISOL_N;
wire pReset;
wire isol_n;
wire prog_reset;
wire prog_clk;
wire gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire gfpga_pad_io_soc_in;
wire gfpga_pad_io_soc_out;
wire gfpga_pad_io_soc_dir;
wire io_outpad;
wire ccff_head;
wire io_inpad;
@ -40,12 +40,12 @@ module logical_tile_io_mode_io_
logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0
(
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
.iopad_outpad(direct_interc_1_out),
.ccff_head(ccff_head),
.iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad),

50
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_io_mode_physical__iopad.v
View File

@ -2,58 +2,58 @@
//netlist name: FPGA88_SOFA_A
module logical_tile_io_mode_physical__iopad
(
IO_ISOL_N,
pReset,
isol_n,
prog_reset,
prog_clk,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_io_soc_in,
gfpga_pad_io_soc_out,
gfpga_pad_io_soc_dir,
iopad_outpad,
ccff_head,
iopad_inpad,
ccff_tail
);
input IO_ISOL_N;
input pReset;
input isol_n;
input prog_reset;
input prog_clk;
input gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
output gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
input gfpga_pad_io_soc_in;
output gfpga_pad_io_soc_out;
output gfpga_pad_io_soc_dir;
input iopad_outpad;
input ccff_head;
output iopad_inpad;
output ccff_tail;
wire IO_ISOL_N;
wire pReset;
wire isol_n;
wire prog_reset;
wire prog_clk;
wire gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire gfpga_pad_io_soc_in;
wire gfpga_pad_io_soc_out;
wire gfpga_pad_io_soc_dir;
wire iopad_outpad;
wire ccff_head;
wire iopad_inpad;
wire ccff_tail;
wire EMBEDDED_IO_HD_0_en;
wire io_0_en;
EMBEDDED_IO_HD EMBEDDED_IO_HD_0_
io io_0_
(
.IO_ISOL_N(IO_ISOL_N),
.SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
.SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.IO_ISOL_N(isol_n),
.SOC_IN(gfpga_pad_io_soc_in),
.SOC_OUT(gfpga_pad_io_soc_out),
.SOC_DIR(gfpga_pad_io_soc_dir),
.FPGA_OUT(iopad_outpad),
.FPGA_DIR(EMBEDDED_IO_HD_0_en),
.FPGA_DIR(io_0_en),
.FPGA_IN(iopad_inpad)
);
EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem
io_sky130_fd_sc_hd__dfrtp_1_mem io_sky130_fd_sc_hd__dfrtp_1_mem
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(ccff_tail),
.mem_out(EMBEDDED_IO_HD_0_en)
.mem_out(io_0_en)
);
endmodule

14
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__0_.v
View File

@ -2,7 +2,7 @@
//netlist name: FPGA88_SOFA_A
module cbx_1__0_
(
pReset,
prog_reset,
prog_clk,
chanx_left_in,
chanx_right_in,
@ -16,7 +16,7 @@ module cbx_1__0_
ccff_tail
);
input pReset;
input prog_reset;
input prog_clk;
input [0:29]chanx_left_in;
input [0:29]chanx_right_in;
@ -29,7 +29,7 @@ module cbx_1__0_
output bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_;
output ccff_tail;
wire pReset;
wire prog_reset;
wire prog_clk;
wire [0:29]chanx_left_in;
wire [0:29]chanx_right_in;
@ -143,7 +143,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_top_ipin_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
@ -151,7 +151,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_top_ipin_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
@ -159,7 +159,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_top_ipin_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
@ -167,7 +167,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_top_ipin_3
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.ccff_tail(ccff_tail),

38
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__1_.v
View File

@ -2,7 +2,7 @@
//netlist name: FPGA88_SOFA_A
module cbx_1__1_
(
pReset,
prog_reset,
prog_clk,
chanx_left_in,
chanx_right_in,
@ -28,7 +28,7 @@ module cbx_1__1_
ccff_tail
);
input pReset;
input prog_reset;
input prog_clk;
input [0:29]chanx_left_in;
input [0:29]chanx_right_in;
@ -53,7 +53,7 @@ module cbx_1__1_
output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_;
output ccff_tail;
wire pReset;
wire prog_reset;
wire prog_clk;
wire [0:29]chanx_left_in;
wire [0:29]chanx_right_in;
@ -243,7 +243,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_top_ipin_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
@ -251,7 +251,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_top_ipin_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
@ -259,7 +259,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_top_ipin_4
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
@ -267,7 +267,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_top_ipin_6
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
@ -275,7 +275,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_top_ipin_8
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
@ -283,7 +283,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_top_ipin_10
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
@ -291,7 +291,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_top_ipin_12
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
@ -299,7 +299,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_top_ipin_14
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
@ -363,7 +363,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size10_mem mem_top_ipin_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
@ -371,7 +371,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size10_mem mem_top_ipin_3
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
@ -379,7 +379,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size10_mem mem_top_ipin_5
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
@ -387,7 +387,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size10_mem mem_top_ipin_7
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
@ -395,7 +395,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size10_mem mem_top_ipin_9
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
@ -403,7 +403,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size10_mem mem_top_ipin_11
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
@ -411,7 +411,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size10_mem mem_top_ipin_13
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
@ -419,7 +419,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size10_mem mem_top_ipin_15
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
.ccff_tail(ccff_tail),

46
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__8_.v
View File

@ -2,7 +2,7 @@
//netlist name: FPGA88_SOFA_A
module cbx_1__8_
(
pReset,
prog_reset,
prog_clk,
chanx_left_in,
chanx_right_in,
@ -32,7 +32,7 @@ module cbx_1__8_
ccff_tail
);
input pReset;
input prog_reset;
input prog_clk;
input [0:29]chanx_left_in;
input [0:29]chanx_right_in;
@ -61,7 +61,7 @@ module cbx_1__8_
output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_;
output ccff_tail;
wire pReset;
wire prog_reset;
wire prog_clk;
wire [0:29]chanx_left_in;
wire [0:29]chanx_right_in;
@ -295,7 +295,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_bottom_ipin_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
@ -303,7 +303,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_bottom_ipin_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
@ -311,7 +311,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_bottom_ipin_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
@ -319,7 +319,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_bottom_ipin_3
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
@ -327,7 +327,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_top_ipin_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
@ -335,7 +335,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_top_ipin_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
@ -343,7 +343,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_top_ipin_4
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
@ -351,7 +351,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_top_ipin_6
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
@ -359,7 +359,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_top_ipin_8
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail),
@ -367,7 +367,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_top_ipin_10
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail),
@ -375,7 +375,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_top_ipin_12
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail),
@ -383,7 +383,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size12_mem mem_top_ipin_14
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail),
@ -447,7 +447,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size10_mem mem_top_ipin_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
@ -455,7 +455,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size10_mem mem_top_ipin_3
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
@ -463,7 +463,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size10_mem mem_top_ipin_5
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
@ -471,7 +471,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size10_mem mem_top_ipin_7
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
@ -479,7 +479,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size10_mem mem_top_ipin_9
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
@ -487,7 +487,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size10_mem mem_top_ipin_11
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
@ -495,7 +495,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size10_mem mem_top_ipin_13
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
@ -503,7 +503,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size10_mem mem_top_ipin_15
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail),
.ccff_tail(ccff_tail),

14
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_0__1_.v
View File

@ -2,7 +2,7 @@
//netlist name: FPGA88_SOFA_A
module cby_0__1_
(
pReset,
prog_reset,
prog_clk,
chany_bottom_in,
chany_top_in,
@ -16,7 +16,7 @@ module cby_0__1_
ccff_tail
);
input pReset;
input prog_reset;
input prog_clk;
input [0:29]chany_bottom_in;
input [0:29]chany_top_in;
@ -29,7 +29,7 @@ module cby_0__1_
output left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_;
output ccff_tail;
wire pReset;
wire prog_reset;
wire prog_clk;
wire [0:29]chany_bottom_in;
wire [0:29]chany_top_in;
@ -143,7 +143,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_right_ipin_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
@ -151,7 +151,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_right_ipin_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
@ -159,7 +159,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_right_ipin_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
@ -167,7 +167,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_right_ipin_3
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.ccff_tail(ccff_tail),

38
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_1__1_.v
View File

@ -2,7 +2,7 @@
//netlist name: FPGA88_SOFA_A
module cby_1__1_
(
pReset,
prog_reset,
prog_clk,
chany_bottom_in,
chany_top_in,
@ -28,7 +28,7 @@ module cby_1__1_
ccff_tail
);
input pReset;
input prog_reset;
input prog_clk;
input [0:29]chany_bottom_in;
input [0:29]chany_top_in;
@ -53,7 +53,7 @@ module cby_1__1_
output left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
output ccff_tail;
wire pReset;
wire prog_reset;
wire prog_clk;
wire [0:29]chany_bottom_in;
wire [0:29]chany_top_in;
@ -243,7 +243,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_right_ipin_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
@ -251,7 +251,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_right_ipin_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
@ -259,7 +259,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_right_ipin_4
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
@ -267,7 +267,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_right_ipin_6
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
@ -275,7 +275,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_right_ipin_8
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
@ -283,7 +283,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_right_ipin_10
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
@ -291,7 +291,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_right_ipin_12
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
@ -299,7 +299,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_right_ipin_14
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
@ -363,7 +363,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size10_mem mem_right_ipin_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
@ -371,7 +371,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size10_mem mem_right_ipin_3
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
@ -379,7 +379,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size10_mem mem_right_ipin_5
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
@ -387,7 +387,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size10_mem mem_right_ipin_7
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
@ -395,7 +395,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size10_mem mem_right_ipin_9
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
@ -403,7 +403,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size10_mem mem_right_ipin_11
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
@ -411,7 +411,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size10_mem mem_right_ipin_13
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
@ -419,7 +419,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size10_mem mem_right_ipin_15
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
.ccff_tail(ccff_tail),

46
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_8__1_.v
View File

@ -2,7 +2,7 @@
//netlist name: FPGA88_SOFA_A
module cby_8__1_
(
pReset,
prog_reset,
prog_clk,
chany_bottom_in,
chany_top_in,
@ -32,7 +32,7 @@ module cby_8__1_
ccff_tail
);
input pReset;
input prog_reset;
input prog_clk;
input [0:29]chany_bottom_in;
input [0:29]chany_top_in;
@ -61,7 +61,7 @@ module cby_8__1_
output left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
output ccff_tail;
wire pReset;
wire prog_reset;
wire prog_clk;
wire [0:29]chany_bottom_in;
wire [0:29]chany_top_in;
@ -295,7 +295,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_left_ipin_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
@ -303,7 +303,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_left_ipin_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
@ -311,7 +311,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_left_ipin_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
@ -319,7 +319,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_left_ipin_3
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
@ -327,7 +327,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_right_ipin_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
@ -335,7 +335,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_right_ipin_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
@ -343,7 +343,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_right_ipin_4
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
@ -351,7 +351,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_right_ipin_6
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
@ -359,7 +359,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_right_ipin_8
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail),
@ -367,7 +367,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_right_ipin_10
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail),
@ -375,7 +375,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_right_ipin_12
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail),
@ -383,7 +383,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size12_mem mem_right_ipin_14
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail),
@ -447,7 +447,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size10_mem mem_right_ipin_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
@ -455,7 +455,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size10_mem mem_right_ipin_3
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
@ -463,7 +463,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size10_mem mem_right_ipin_5
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
@ -471,7 +471,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size10_mem mem_right_ipin_7
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
@ -479,7 +479,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size10_mem mem_right_ipin_9
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
@ -487,7 +487,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size10_mem mem_right_ipin_11
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
@ -495,7 +495,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size10_mem mem_right_ipin_13
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
@ -503,7 +503,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
);
mux_tree_tapbuf_size10_mem mem_right_ipin_15
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail),
.ccff_tail(ccff_tail),

78
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__0_.v
View File

@ -2,7 +2,7 @@
//netlist name: FPGA88_SOFA_A
module sb_0__0_
(
pReset,
prog_reset,
prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
@ -20,7 +20,7 @@ module sb_0__0_
ccff_tail
);
input pReset;
input prog_reset;
input prog_clk;
input [0:29]chany_top_in;
input top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
@ -37,7 +37,7 @@ module sb_0__0_
output [0:29]chanx_right_out;
output ccff_tail;
wire pReset;
wire prog_reset;
wire prog_clk;
wire [0:29]chany_top_in;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
@ -215,7 +215,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size3_mem mem_top_track_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@ -223,7 +223,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size3_mem mem_top_track_6
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@ -231,7 +231,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size3_mem mem_right_track_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@ -239,7 +239,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size3_mem mem_right_track_6
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@ -471,7 +471,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_top_track_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@ -479,7 +479,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_top_track_4
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@ -487,7 +487,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_top_track_8
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@ -495,7 +495,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_top_track_10
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@ -503,7 +503,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_top_track_12
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@ -511,7 +511,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_top_track_14
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@ -519,7 +519,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_top_track_16
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
@ -527,7 +527,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_top_track_18
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
@ -535,7 +535,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_top_track_28
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
@ -543,7 +543,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_top_track_30
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
@ -551,7 +551,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_top_track_32
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
@ -559,7 +559,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_top_track_34
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
@ -567,7 +567,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_top_track_44
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
@ -575,7 +575,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_top_track_46
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
@ -583,7 +583,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_top_track_48
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
@ -591,7 +591,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_top_track_50
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
@ -599,7 +599,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
@ -607,7 +607,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_4
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
@ -615,7 +615,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_8
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
@ -623,7 +623,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_10
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
@ -631,7 +631,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_12
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
@ -639,7 +639,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_14
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
@ -647,7 +647,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_16
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
@ -655,7 +655,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_18
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
@ -663,7 +663,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_28
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
@ -671,7 +671,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_30
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
@ -679,7 +679,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_32
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
@ -687,7 +687,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_34
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail),
@ -695,7 +695,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_44
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_28_ccff_tail),
@ -703,7 +703,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_46
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_28_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_29_ccff_tail),
@ -711,7 +711,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_48
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_29_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_30_ccff_tail),
@ -719,7 +719,7 @@ assign chany_top_out[28] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_50
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_30_ccff_tail),
.ccff_tail(ccff_tail),

106
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__1_.v
View File

@ -2,7 +2,7 @@
//netlist name: FPGA88_SOFA_A
module sb_0__1_
(
pReset,
prog_reset,
prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
@ -30,7 +30,7 @@ module sb_0__1_
ccff_tail
);
input pReset;
input prog_reset;
input prog_clk;
input [0:29]chany_top_in;
input top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
@ -57,7 +57,7 @@ module sb_0__1_
output [0:29]chany_bottom_out;
output ccff_tail;
wire pReset;
wire prog_reset;
wire prog_clk;
wire [0:29]chany_top_in;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
@ -309,7 +309,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size7_mem mem_top_track_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
@ -317,7 +317,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size7_mem mem_top_track_6
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
@ -325,7 +325,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size7_mem mem_top_track_10
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
@ -333,7 +333,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size7_mem mem_bottom_track_7
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
@ -341,7 +341,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size7_mem mem_bottom_track_11
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
@ -433,7 +433,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size6_mem mem_top_track_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
@ -441,7 +441,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size6_mem mem_top_track_4
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
@ -449,7 +449,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size6_mem mem_top_track_12
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
@ -457,7 +457,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size6_mem mem_top_track_20
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
@ -465,7 +465,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size6_mem mem_right_track_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
@ -473,7 +473,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size6_mem mem_right_track_6
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
@ -481,7 +481,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size6_mem mem_right_track_8
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
@ -489,7 +489,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size6_mem mem_bottom_track_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
@ -497,7 +497,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size6_mem mem_bottom_track_5
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
@ -505,7 +505,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size6_mem mem_bottom_track_13
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
@ -513,7 +513,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size6_mem mem_bottom_track_21
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail),
@ -521,7 +521,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size6_mem mem_bottom_track_29
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail),
@ -571,7 +571,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size5_mem mem_top_track_28
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
@ -579,7 +579,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size5_mem mem_right_track_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
@ -587,7 +587,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size5_mem mem_right_track_4
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
@ -595,7 +595,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size5_mem mem_right_track_10
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@ -603,7 +603,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size5_mem mem_bottom_track_3
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
@ -611,7 +611,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size5_mem mem_bottom_track_37
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
@ -689,7 +689,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size4_mem mem_top_track_36
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
@ -697,7 +697,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size4_mem mem_top_track_52
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
@ -705,7 +705,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size4_mem mem_right_track_12
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
@ -713,7 +713,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size4_mem mem_right_track_14
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
@ -721,7 +721,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size4_mem mem_right_track_16
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
@ -729,7 +729,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size4_mem mem_right_track_18
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail),
@ -737,7 +737,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size4_mem mem_right_track_20
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail),
@ -745,7 +745,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size4_mem mem_right_track_22
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_7_ccff_tail),
@ -753,7 +753,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size4_mem mem_right_track_36
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_8_ccff_tail),
@ -761,7 +761,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size4_mem mem_bottom_track_45
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_9_ccff_tail),
@ -832,7 +832,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size3_mem mem_top_track_44
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@ -840,7 +840,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size3_mem mem_right_track_24
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@ -848,7 +848,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size3_mem mem_right_track_26
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@ -856,7 +856,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size3_mem mem_right_track_28
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@ -864,7 +864,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size3_mem mem_right_track_30
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
@ -872,7 +872,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size3_mem mem_right_track_32
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
@ -880,7 +880,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size3_mem mem_right_track_34
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
@ -888,7 +888,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size3_mem mem_right_track_50
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
@ -896,7 +896,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size3_mem mem_bottom_track_53
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_9_ccff_tail),
.ccff_tail(ccff_tail),
@ -960,7 +960,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size2_mem mem_right_track_38
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@ -968,7 +968,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size2_mem mem_right_track_40
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@ -976,7 +976,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size2_mem mem_right_track_44
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@ -984,7 +984,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size2_mem mem_right_track_46
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@ -992,7 +992,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size2_mem mem_right_track_48
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@ -1000,7 +1000,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size2_mem mem_right_track_52
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@ -1008,7 +1008,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size2_mem mem_right_track_54
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
@ -1016,7 +1016,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
);
mux_tree_tapbuf_size2_mem mem_right_track_56
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),

102
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__8_.v
View File

@ -2,7 +2,7 @@
//netlist name: FPGA88_SOFA_A
module sb_0__8_
(
pReset,
prog_reset,
prog_clk,
chanx_right_in,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
@ -28,7 +28,7 @@ module sb_0__8_
ccff_tail
);
input pReset;
input prog_reset;
input prog_clk;
input [0:29]chanx_right_in;
input right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
@ -53,7 +53,7 @@ module sb_0__8_
output [0:29]chany_bottom_out;
output ccff_tail;
wire pReset;
wire prog_reset;
wire prog_clk;
wire [0:29]chanx_right_in;
wire right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
@ -277,7 +277,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size5_mem mem_right_track_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
@ -285,7 +285,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size5_mem mem_right_track_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
@ -293,7 +293,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size5_mem mem_right_track_4
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
@ -301,7 +301,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size5_mem mem_right_track_6
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@ -309,7 +309,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size5_mem mem_right_track_8
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
@ -317,7 +317,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size5_mem mem_right_track_10
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
@ -416,7 +416,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size3_mem mem_right_track_12
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@ -424,7 +424,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size3_mem mem_right_track_14
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@ -432,7 +432,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size3_mem mem_right_track_16
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@ -440,7 +440,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size3_mem mem_right_track_28
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@ -448,7 +448,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size3_mem mem_right_track_30
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
@ -456,7 +456,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size3_mem mem_right_track_32
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
@ -464,7 +464,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size3_mem mem_right_track_34
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
@ -472,7 +472,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size3_mem mem_right_track_44
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
@ -480,7 +480,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size3_mem mem_right_track_46
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
@ -488,7 +488,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size3_mem mem_right_track_48
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
@ -496,7 +496,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size3_mem mem_right_track_58
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
@ -504,7 +504,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size3_mem mem_bottom_track_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail),
@ -512,7 +512,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size3_mem mem_bottom_track_7
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail),
@ -723,7 +723,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_18
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@ -731,7 +731,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_20
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@ -739,7 +739,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_22
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@ -747,7 +747,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_24
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@ -755,7 +755,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_26
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@ -763,7 +763,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_36
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@ -771,7 +771,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_38
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
@ -779,7 +779,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_40
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
@ -787,7 +787,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_42
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
@ -795,7 +795,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_50
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
@ -803,7 +803,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_52
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
@ -811,7 +811,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_54
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
@ -819,7 +819,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_right_track_56
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
@ -827,7 +827,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_3
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
@ -835,7 +835,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_5
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
@ -843,7 +843,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_9
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
@ -851,7 +851,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_11
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
@ -859,7 +859,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_13
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
@ -867,7 +867,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_15
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
@ -875,7 +875,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_17
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
@ -883,7 +883,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_19
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
@ -891,7 +891,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_29
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
@ -899,7 +899,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_31
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
@ -907,7 +907,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_33
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
@ -915,7 +915,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_35
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
@ -923,7 +923,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_45
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
@ -931,7 +931,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_47
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
@ -939,7 +939,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_49
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail),
@ -947,7 +947,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_51
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail),
.ccff_tail(ccff_tail),

102
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__0_.v
View File

@ -2,7 +2,7 @@
//netlist name: FPGA88_SOFA_A
module sb_1__0_
(
pReset,
prog_reset,
prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
@ -30,7 +30,7 @@ module sb_1__0_
ccff_tail
);
input pReset;
input prog_reset;
input prog_clk;
input [0:29]chany_top_in;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@ -57,7 +57,7 @@ module sb_1__0_
output [0:29]chanx_left_out;
output ccff_tail;
wire pReset;
wire prog_reset;
wire prog_clk;
wire [0:29]chany_top_in;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@ -306,7 +306,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size7_mem mem_top_track_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
@ -314,7 +314,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size7_mem mem_right_track_6
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
@ -322,7 +322,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size7_mem mem_right_track_10
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
@ -330,7 +330,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size7_mem mem_left_track_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
@ -338,7 +338,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size7_mem mem_left_track_11
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
@ -437,7 +437,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_top_track_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
@ -445,7 +445,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_top_track_6
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
@ -453,7 +453,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_top_track_8
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
@ -461,7 +461,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_right_track_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
@ -469,7 +469,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_right_track_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
@ -477,7 +477,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_right_track_4
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
@ -485,7 +485,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_right_track_12
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
@ -493,7 +493,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_right_track_20
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
@ -501,7 +501,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_right_track_28
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
@ -509,7 +509,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_left_track_7
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
@ -517,7 +517,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_left_track_13
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail),
@ -525,7 +525,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_left_track_21
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail),
@ -533,7 +533,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_left_track_29
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_12_ccff_tail),
@ -583,7 +583,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size5_mem mem_top_track_4
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
@ -591,7 +591,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size5_mem mem_top_track_10
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
@ -599,7 +599,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size5_mem mem_right_track_36
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
@ -607,7 +607,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size5_mem mem_left_track_3
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@ -615,7 +615,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size5_mem mem_left_track_5
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
@ -623,7 +623,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size5_mem mem_left_track_37
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_12_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
@ -673,7 +673,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size4_mem mem_top_track_12
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
@ -681,7 +681,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size4_mem mem_top_track_14
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
@ -689,7 +689,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size4_mem mem_top_track_16
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
@ -697,7 +697,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size4_mem mem_top_track_18
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
@ -705,7 +705,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size4_mem mem_left_track_45
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
@ -713,7 +713,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size4_mem mem_left_track_53
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.ccff_tail(ccff_tail),
@ -770,7 +770,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size3_mem mem_top_track_20
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@ -778,7 +778,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size3_mem mem_top_track_22
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@ -786,7 +786,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size3_mem mem_top_track_24
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@ -794,7 +794,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size3_mem mem_top_track_26
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@ -802,7 +802,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size3_mem mem_top_track_36
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
@ -810,7 +810,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size3_mem mem_right_track_44
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
@ -818,7 +818,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size3_mem mem_right_track_52
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
@ -903,7 +903,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_top_track_28
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@ -911,7 +911,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_top_track_30
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@ -919,7 +919,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_top_track_32
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@ -927,7 +927,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_top_track_34
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@ -935,7 +935,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_top_track_40
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@ -943,7 +943,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_top_track_42
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@ -951,7 +951,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_top_track_44
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
@ -959,7 +959,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_top_track_46
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
@ -967,7 +967,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_top_track_48
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
@ -975,7 +975,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_top_track_50
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
@ -983,7 +983,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_top_track_58
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),

94
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__1_.v
View File

@ -2,7 +2,7 @@
//netlist name: FPGA88_SOFA_A
module sb_1__1_
(
pReset,
prog_reset,
prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
@ -48,7 +48,7 @@ module sb_1__1_
ccff_tail
);
input pReset;
input prog_reset;
input prog_clk;
input [0:29]chany_top_in;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@ -93,7 +93,7 @@ module sb_1__1_
output [0:29]chanx_left_out;
output ccff_tail;
wire pReset;
wire prog_reset;
wire prog_clk;
wire [0:29]chany_top_in;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@ -403,7 +403,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size11_mem mem_top_track_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail),
@ -411,7 +411,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size11_mem mem_top_track_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail),
@ -419,7 +419,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size11_mem mem_right_track_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail),
@ -427,7 +427,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size11_mem mem_right_track_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size11_mem_3_ccff_tail),
@ -435,7 +435,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size11_mem mem_bottom_track_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size11_mem_4_ccff_tail),
@ -443,7 +443,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size11_mem mem_bottom_track_3
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size11_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size11_mem_5_ccff_tail),
@ -451,7 +451,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size11_mem mem_left_track_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size11_mem_6_ccff_tail),
@ -459,7 +459,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size11_mem mem_left_track_3
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size11_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size11_mem_7_ccff_tail),
@ -551,7 +551,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size10_mem mem_top_track_4
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
@ -559,7 +559,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size10_mem mem_top_track_12
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
@ -567,7 +567,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size10_mem mem_top_track_20
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
@ -575,7 +575,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size10_mem mem_right_track_4
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size11_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
@ -583,7 +583,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size10_mem mem_right_track_12
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
@ -591,7 +591,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size10_mem mem_right_track_20
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
@ -599,7 +599,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size10_mem mem_bottom_track_5
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size11_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
@ -607,7 +607,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size10_mem mem_bottom_track_13
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail),
@ -615,7 +615,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size10_mem mem_bottom_track_21
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail),
@ -623,7 +623,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size10_mem mem_left_track_5
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size11_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail),
@ -631,7 +631,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size10_mem mem_left_track_13
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail),
@ -639,7 +639,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size10_mem mem_left_track_21
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail),
@ -703,7 +703,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size12_mem mem_top_track_6
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
@ -711,7 +711,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size12_mem mem_top_track_10
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
@ -719,7 +719,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size12_mem mem_right_track_6
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
@ -727,7 +727,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size12_mem mem_right_track_10
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
@ -735,7 +735,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size12_mem mem_bottom_track_7
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
@ -743,7 +743,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size12_mem mem_bottom_track_11
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
@ -751,7 +751,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size12_mem mem_left_track_7
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
@ -759,7 +759,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size12_mem mem_left_track_11
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
@ -795,7 +795,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size9_mem mem_top_track_28
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
@ -803,7 +803,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size9_mem mem_right_track_28
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
@ -811,7 +811,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size9_mem mem_bottom_track_29
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail),
@ -819,7 +819,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size9_mem mem_left_track_29
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail),
@ -911,7 +911,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_top_track_36
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
@ -919,7 +919,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_top_track_44
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
@ -927,7 +927,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_top_track_52
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
@ -935,7 +935,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_right_track_36
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
@ -943,7 +943,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_right_track_44
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
@ -951,7 +951,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_right_track_52
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
@ -959,7 +959,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_bottom_track_37
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
@ -967,7 +967,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_bottom_track_45
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
@ -975,7 +975,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_bottom_track_53
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
@ -983,7 +983,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_left_track_37
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
@ -991,7 +991,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_left_track_45
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail),
@ -999,7 +999,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_left_track_53
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail),
.ccff_tail(ccff_tail),

102
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__8_.v
View File

@ -2,7 +2,7 @@
//netlist name: FPGA88_SOFA_A
module sb_1__8_
(
pReset,
prog_reset,
prog_clk,
chanx_right_in,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
@ -46,7 +46,7 @@ module sb_1__8_
ccff_tail
);
input pReset;
input prog_reset;
input prog_clk;
input [0:29]chanx_right_in;
input right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
@ -89,7 +89,7 @@ module sb_1__8_
output [0:29]chanx_left_out;
output ccff_tail;
wire pReset;
wire prog_reset;
wire prog_clk;
wire [0:29]chanx_right_in;
wire right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
@ -340,7 +340,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size8_mem mem_right_track_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail),
@ -348,7 +348,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size8_mem mem_right_track_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail),
@ -356,7 +356,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size8_mem mem_left_track_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail),
@ -385,7 +385,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size9_mem mem_right_track_4
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
@ -393,7 +393,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size9_mem mem_left_track_3
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
@ -401,7 +401,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size9_mem mem_left_track_5
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail),
@ -437,7 +437,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size11_mem mem_right_track_6
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail),
@ -445,7 +445,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size11_mem mem_right_track_10
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail),
@ -453,7 +453,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size11_mem mem_left_track_7
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail),
@ -461,7 +461,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size11_mem mem_left_track_11
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size11_mem_3_ccff_tail),
@ -511,7 +511,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size7_mem mem_right_track_12
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
@ -519,7 +519,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size7_mem mem_right_track_20
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
@ -527,7 +527,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size7_mem mem_right_track_28
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
@ -535,7 +535,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size7_mem mem_left_track_13
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size11_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
@ -543,7 +543,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size7_mem mem_left_track_21
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
@ -551,7 +551,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size7_mem mem_left_track_29
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail),
@ -608,7 +608,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_right_track_36
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
@ -616,7 +616,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_right_track_44
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
@ -624,7 +624,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_bottom_track_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
@ -632,7 +632,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_bottom_track_3
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
@ -640,7 +640,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_bottom_track_7
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
@ -648,7 +648,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_bottom_track_9
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
@ -656,7 +656,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size6_mem mem_left_track_37
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
@ -699,7 +699,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size5_mem mem_right_track_52
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
@ -707,7 +707,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size5_mem mem_bottom_track_5
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
@ -715,7 +715,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size5_mem mem_bottom_track_11
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
@ -723,7 +723,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size5_mem mem_left_track_45
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@ -731,7 +731,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size5_mem mem_left_track_53
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.ccff_tail(ccff_tail),
@ -774,7 +774,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size4_mem mem_bottom_track_13
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
@ -782,7 +782,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size4_mem mem_bottom_track_15
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
@ -790,7 +790,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size4_mem mem_bottom_track_17
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
@ -798,7 +798,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size4_mem mem_bottom_track_19
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
@ -806,7 +806,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size4_mem mem_bottom_track_37
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
@ -842,7 +842,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size3_mem mem_bottom_track_21
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@ -850,7 +850,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size3_mem mem_bottom_track_23
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@ -858,7 +858,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size3_mem mem_bottom_track_25
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@ -866,7 +866,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size3_mem mem_bottom_track_27
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@ -951,7 +951,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_29
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@ -959,7 +959,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_31
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@ -967,7 +967,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_33
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@ -975,7 +975,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_35
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@ -983,7 +983,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_39
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@ -991,7 +991,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_41
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@ -999,7 +999,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_43
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
@ -1007,7 +1007,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_45
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
@ -1015,7 +1015,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_47
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
@ -1023,7 +1023,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_49
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
@ -1031,7 +1031,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_51
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),

94
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__0_.v
View File

@ -2,7 +2,7 @@
//netlist name: FPGA88_SOFA_A
module sb_8__0_
(
pReset,
prog_reset,
prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
@ -28,7 +28,7 @@ module sb_8__0_
ccff_tail
);
input pReset;
input prog_reset;
input prog_clk;
input [0:29]chany_top_in;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@ -53,7 +53,7 @@ module sb_8__0_
output [0:29]chanx_left_out;
output ccff_tail;
wire pReset;
wire prog_reset;
wire prog_clk;
wire [0:29]chany_top_in;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@ -269,7 +269,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size5_mem mem_top_track_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
@ -277,7 +277,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size5_mem mem_top_track_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
@ -285,7 +285,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size5_mem mem_top_track_4
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
@ -293,7 +293,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size5_mem mem_top_track_6
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@ -301,7 +301,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size5_mem mem_top_track_8
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
@ -309,7 +309,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size5_mem mem_top_track_10
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
@ -387,7 +387,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size3_mem mem_top_track_12
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@ -395,7 +395,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size3_mem mem_top_track_14
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@ -403,7 +403,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size3_mem mem_top_track_16
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@ -411,7 +411,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size3_mem mem_top_track_18
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@ -419,7 +419,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size3_mem mem_top_track_44
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
@ -427,7 +427,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size3_mem mem_top_track_46
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
@ -435,7 +435,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size3_mem mem_top_track_48
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
@ -443,7 +443,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size3_mem mem_top_track_50
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
@ -451,7 +451,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size3_mem mem_left_track_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
@ -459,7 +459,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size3_mem mem_left_track_7
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
@ -663,7 +663,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_top_track_20
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@ -671,7 +671,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_top_track_22
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@ -679,7 +679,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_top_track_24
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@ -687,7 +687,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_top_track_26
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@ -695,7 +695,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_top_track_28
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@ -703,7 +703,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_top_track_30
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@ -711,7 +711,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_top_track_32
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
@ -719,7 +719,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_top_track_34
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
@ -727,7 +727,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_top_track_36
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
@ -735,7 +735,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_top_track_38
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
@ -743,7 +743,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_top_track_40
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
@ -751,7 +751,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_top_track_42
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
@ -759,7 +759,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_left_track_3
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
@ -767,7 +767,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_left_track_5
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
@ -775,7 +775,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_left_track_9
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
@ -783,7 +783,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_left_track_11
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
@ -791,7 +791,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_left_track_13
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
@ -799,7 +799,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_left_track_15
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
@ -807,7 +807,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_left_track_17
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
@ -815,7 +815,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_left_track_19
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
@ -823,7 +823,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_left_track_29
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
@ -831,7 +831,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_left_track_31
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
@ -839,7 +839,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_left_track_33
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
@ -847,7 +847,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_left_track_35
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
@ -855,7 +855,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_left_track_45
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
@ -863,7 +863,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_left_track_47
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
@ -871,7 +871,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_left_track_49
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
@ -879,7 +879,7 @@ assign chany_top_out[26] = chanx_left_in[4];
);
mux_tree_tapbuf_size2_mem mem_left_track_51
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
.ccff_tail(ccff_tail),

104
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__1_.v
View File

@ -2,7 +2,7 @@
//netlist name: FPGA88_SOFA_A
module sb_8__1_
(
pReset,
prog_reset,
prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
@ -46,7 +46,7 @@ module sb_8__1_
ccff_tail
);
input pReset;
input prog_reset;
input prog_clk;
input [0:29]chany_top_in;
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@ -89,7 +89,7 @@ module sb_8__1_
output [0:29]chanx_left_out;
output ccff_tail;
wire pReset;
wire prog_reset;
wire prog_clk;
wire [0:29]chany_top_in;
wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@ -349,7 +349,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size9_mem mem_top_track_0
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
@ -357,7 +357,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size9_mem mem_bottom_track_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
@ -365,7 +365,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size9_mem mem_bottom_track_3
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail),
@ -373,7 +373,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size9_mem mem_bottom_track_5
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail),
@ -395,7 +395,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size8_mem mem_top_track_2
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail),
@ -403,7 +403,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size8_mem mem_top_track_4
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail),
@ -418,7 +418,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size10_mem mem_top_track_6
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
@ -447,7 +447,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size11_mem mem_top_track_10
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail),
@ -455,7 +455,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size11_mem mem_bottom_track_7
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail),
@ -463,7 +463,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size11_mem mem_bottom_track_11
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail),
@ -506,7 +506,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size7_mem mem_top_track_12
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
@ -514,7 +514,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size7_mem mem_top_track_20
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
@ -522,7 +522,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size7_mem mem_top_track_28
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
@ -530,7 +530,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size7_mem mem_bottom_track_13
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
@ -538,7 +538,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size7_mem mem_bottom_track_21
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
@ -609,7 +609,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size6_mem mem_top_track_36
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
@ -617,7 +617,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size6_mem mem_top_track_44
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
@ -625,7 +625,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size6_mem mem_top_track_52
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
@ -633,7 +633,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size6_mem mem_bottom_track_29
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
@ -641,7 +641,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size6_mem mem_bottom_track_53
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
@ -649,7 +649,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size6_mem mem_left_track_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
@ -657,7 +657,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size6_mem mem_left_track_3
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
@ -665,7 +665,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size6_mem mem_left_track_7
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
@ -673,7 +673,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size6_mem mem_left_track_9
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
@ -709,7 +709,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size5_mem mem_bottom_track_37
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
@ -717,7 +717,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size5_mem mem_bottom_track_45
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
@ -725,7 +725,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size5_mem mem_left_track_5
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
@ -733,7 +733,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size5_mem mem_left_track_11
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@ -783,7 +783,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size4_mem mem_left_track_13
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
@ -791,7 +791,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size4_mem mem_left_track_15
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
@ -799,7 +799,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size4_mem mem_left_track_17
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
@ -807,7 +807,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size4_mem mem_left_track_19
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
@ -815,7 +815,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size4_mem mem_left_track_21
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
@ -823,7 +823,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size4_mem mem_left_track_23
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail),
@ -887,7 +887,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size3_mem mem_left_track_25
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@ -895,7 +895,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size3_mem mem_left_track_27
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@ -903,7 +903,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size3_mem mem_left_track_29
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@ -911,7 +911,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size3_mem mem_left_track_31
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@ -919,7 +919,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size3_mem mem_left_track_33
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
@ -927,7 +927,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size3_mem mem_left_track_35
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
@ -935,7 +935,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size3_mem mem_left_track_37
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
@ -943,7 +943,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size3_mem mem_left_track_51
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
@ -1000,7 +1000,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size2_mem mem_left_track_41
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@ -1008,7 +1008,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size2_mem mem_left_track_45
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@ -1016,7 +1016,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size2_mem mem_left_track_47
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@ -1024,7 +1024,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size2_mem mem_left_track_49
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@ -1032,7 +1032,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size2_mem mem_left_track_53
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@ -1040,7 +1040,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size2_mem mem_left_track_55
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@ -1048,7 +1048,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
);
mux_tree_tapbuf_size2_mem mem_left_track_57
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(ccff_tail),

118
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__8_.v
View File

@ -2,7 +2,7 @@
//netlist name: FPGA88_SOFA_A
module sb_8__8_
(
pReset,
prog_reset,
prog_clk,
chany_bottom_in,
bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
@ -36,7 +36,7 @@ module sb_8__8_
ccff_tail
);
input pReset;
input prog_reset;
input prog_clk;
input [0:29]chany_bottom_in;
input bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
@ -69,7 +69,7 @@ module sb_8__8_
output [0:29]chanx_left_out;
output ccff_tail;
wire pReset;
wire prog_reset;
wire prog_clk;
wire [0:29]chany_bottom_in;
wire bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
@ -359,7 +359,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size5_mem mem_bottom_track_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
@ -367,7 +367,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size5_mem mem_bottom_track_3
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
@ -375,7 +375,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size5_mem mem_bottom_track_5
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
@ -383,7 +383,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size5_mem mem_bottom_track_7
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@ -391,7 +391,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size5_mem mem_bottom_track_9
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
@ -399,7 +399,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size5_mem mem_bottom_track_11
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
@ -407,7 +407,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size5_mem mem_left_track_1
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_6_ccff_tail),
@ -415,7 +415,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size5_mem mem_left_track_3
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_7_ccff_tail),
@ -423,7 +423,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size5_mem mem_left_track_5
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_8_ccff_tail),
@ -431,7 +431,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size5_mem mem_left_track_7
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_9_ccff_tail),
@ -439,7 +439,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size5_mem mem_left_track_9
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_10_ccff_tail),
@ -447,7 +447,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size5_mem mem_left_track_11
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size5_mem_11_ccff_tail),
@ -630,7 +630,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_13
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@ -638,7 +638,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_15
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@ -646,7 +646,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_17
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@ -654,7 +654,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_19
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@ -662,7 +662,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_21
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@ -670,7 +670,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_23
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@ -678,7 +678,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_25
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
@ -686,7 +686,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_27
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
@ -694,7 +694,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_53
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
@ -702,7 +702,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_55
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
@ -710,7 +710,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_57
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
@ -718,7 +718,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_bottom_track_59
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
@ -726,7 +726,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_left_track_19
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
@ -734,7 +734,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_left_track_21
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
@ -742,7 +742,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_left_track_23
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
@ -750,7 +750,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_left_track_25
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
@ -758,7 +758,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_left_track_27
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
@ -766,7 +766,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_left_track_37
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_14_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
@ -774,7 +774,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_left_track_39
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
@ -782,7 +782,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_left_track_41
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
@ -790,7 +790,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_left_track_43
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
@ -798,7 +798,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_left_track_51
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_17_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
@ -806,7 +806,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_left_track_53
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
@ -814,7 +814,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_left_track_55
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
@ -822,7 +822,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size2_mem mem_left_track_57
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
@ -963,7 +963,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size3_mem mem_bottom_track_29
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@ -971,7 +971,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size3_mem mem_bottom_track_31
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@ -979,7 +979,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size3_mem mem_bottom_track_33
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@ -987,7 +987,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size3_mem mem_bottom_track_35
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@ -995,7 +995,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size3_mem mem_bottom_track_45
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
@ -1003,7 +1003,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size3_mem mem_bottom_track_47
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
@ -1011,7 +1011,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size3_mem mem_bottom_track_49
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
@ -1019,7 +1019,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size3_mem mem_bottom_track_51
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
@ -1027,7 +1027,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size3_mem mem_left_track_13
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_11_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
@ -1035,7 +1035,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size3_mem mem_left_track_15
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
@ -1043,7 +1043,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size3_mem mem_left_track_17
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
@ -1051,7 +1051,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size3_mem mem_left_track_29
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail),
@ -1059,7 +1059,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size3_mem mem_left_track_31
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail),
@ -1067,7 +1067,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size3_mem mem_left_track_33
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_13_ccff_tail),
@ -1075,7 +1075,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size3_mem mem_left_track_35
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_13_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_14_ccff_tail),
@ -1083,7 +1083,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size3_mem mem_left_track_45
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_15_ccff_tail),
@ -1091,7 +1091,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size3_mem mem_left_track_47
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_15_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_16_ccff_tail),
@ -1099,7 +1099,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size3_mem mem_left_track_49
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_16_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_17_ccff_tail),
@ -1107,7 +1107,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
);
mux_tree_tapbuf_size3_mem mem_left_track_59
(
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
.ccff_tail(ccff_tail),

198
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/memories.v
View File

@ -2,20 +2,20 @@
//netlist name: FPGA88_SOFA_A
module mux_tree_tapbuf_size12_mem
(
pReset,
prog_reset,
prog_clk,
ccff_head,
ccff_tail,
mem_out
);
input pReset;
input prog_reset;
input prog_clk;
input ccff_head;
output ccff_tail;
output [0:3]mem_out;
wire pReset;
wire prog_reset;
wire prog_clk;
wire ccff_head;
wire ccff_tail;
@ -24,28 +24,28 @@ module mux_tree_tapbuf_size12_mem
assign ccff_tail = mem_out[3];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[2]),
.Q(mem_out[3])
@ -54,20 +54,20 @@ endmodule
module mux_tree_tapbuf_size10_mem
(
pReset,
prog_reset,
prog_clk,
ccff_head,
ccff_tail,
mem_out
);
input pReset;
input prog_reset;
input prog_clk;
input ccff_head;
output ccff_tail;
output [0:3]mem_out;
wire pReset;
wire prog_reset;
wire prog_clk;
wire ccff_head;
wire ccff_tail;
@ -76,28 +76,28 @@ module mux_tree_tapbuf_size10_mem
assign ccff_tail = mem_out[3];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[2]),
.Q(mem_out[3])
@ -106,20 +106,20 @@ endmodule
module mux_tree_tapbuf_size3_mem
(
pReset,
prog_reset,
prog_clk,
ccff_head,
ccff_tail,
mem_out
);
input pReset;
input prog_reset;
input prog_clk;
input ccff_head;
output ccff_tail;
output [0:1]mem_out;
wire pReset;
wire prog_reset;
wire prog_clk;
wire ccff_head;
wire ccff_tail;
@ -128,14 +128,14 @@ module mux_tree_tapbuf_size3_mem
assign ccff_tail = mem_out[1];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1])
@ -144,20 +144,20 @@ endmodule
module mux_tree_tapbuf_size7_mem
(
pReset,
prog_reset,
prog_clk,
ccff_head,
ccff_tail,
mem_out
);
input pReset;
input prog_reset;
input prog_clk;
input ccff_head;
output ccff_tail;
output [0:2]mem_out;
wire pReset;
wire prog_reset;
wire prog_clk;
wire ccff_head;
wire ccff_tail;
@ -166,21 +166,21 @@ module mux_tree_tapbuf_size7_mem
assign ccff_tail = mem_out[2];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2])
@ -189,20 +189,20 @@ endmodule
module mux_tree_tapbuf_size2_mem
(
pReset,
prog_reset,
prog_clk,
ccff_head,
ccff_tail,
mem_out
);
input pReset;
input prog_reset;
input prog_clk;
input ccff_head;
output ccff_tail;
output [0:1]mem_out;
wire pReset;
wire prog_reset;
wire prog_clk;
wire ccff_head;
wire ccff_tail;
@ -211,14 +211,14 @@ module mux_tree_tapbuf_size2_mem
assign ccff_tail = mem_out[1];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1])
@ -227,20 +227,20 @@ endmodule
module mux_tree_tapbuf_size5_mem
(
pReset,
prog_reset,
prog_clk,
ccff_head,
ccff_tail,
mem_out
);
input pReset;
input prog_reset;
input prog_clk;
input ccff_head;
output ccff_tail;
output [0:2]mem_out;
wire pReset;
wire prog_reset;
wire prog_clk;
wire ccff_head;
wire ccff_tail;
@ -249,21 +249,21 @@ module mux_tree_tapbuf_size5_mem
assign ccff_tail = mem_out[2];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2])
@ -272,20 +272,20 @@ endmodule
module mux_tree_tapbuf_size6_mem
(
pReset,
prog_reset,
prog_clk,
ccff_head,
ccff_tail,
mem_out
);
input pReset;
input prog_reset;
input prog_clk;
input ccff_head;
output ccff_tail;
output [0:2]mem_out;
wire pReset;
wire prog_reset;
wire prog_clk;
wire ccff_head;
wire ccff_tail;
@ -294,21 +294,21 @@ module mux_tree_tapbuf_size6_mem
assign ccff_tail = mem_out[2];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2])
@ -317,20 +317,20 @@ endmodule
module mux_tree_tapbuf_size4_mem
(
pReset,
prog_reset,
prog_clk,
ccff_head,
ccff_tail,
mem_out
);
input pReset;
input prog_reset;
input prog_clk;
input ccff_head;
output ccff_tail;
output [0:2]mem_out;
wire pReset;
wire prog_reset;
wire prog_clk;
wire ccff_head;
wire ccff_tail;
@ -339,21 +339,21 @@ module mux_tree_tapbuf_size4_mem
assign ccff_tail = mem_out[2];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2])
@ -362,20 +362,20 @@ endmodule
module mux_tree_tapbuf_size11_mem
(
pReset,
prog_reset,
prog_clk,
ccff_head,
ccff_tail,
mem_out
);
input pReset;
input prog_reset;
input prog_clk;
input ccff_head;
output ccff_tail;
output [0:3]mem_out;
wire pReset;
wire prog_reset;
wire prog_clk;
wire ccff_head;
wire ccff_tail;
@ -384,28 +384,28 @@ module mux_tree_tapbuf_size11_mem
assign ccff_tail = mem_out[3];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[2]),
.Q(mem_out[3])
@ -414,20 +414,20 @@ endmodule
module mux_tree_tapbuf_size9_mem
(
pReset,
prog_reset,
prog_clk,
ccff_head,
ccff_tail,
mem_out
);
input pReset;
input prog_reset;
input prog_clk;
input ccff_head;
output ccff_tail;
output [0:3]mem_out;
wire pReset;
wire prog_reset;
wire prog_clk;
wire ccff_head;
wire ccff_tail;
@ -436,28 +436,28 @@ module mux_tree_tapbuf_size9_mem
assign ccff_tail = mem_out[3];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[2]),
.Q(mem_out[3])
@ -466,20 +466,20 @@ endmodule
module mux_tree_tapbuf_size8_mem
(
pReset,
prog_reset,
prog_clk,
ccff_head,
ccff_tail,
mem_out
);
input pReset;
input prog_reset;
input prog_clk;
input ccff_head;
output ccff_tail;
output [0:3]mem_out;
wire pReset;
wire prog_reset;
wire prog_clk;
wire ccff_head;
wire ccff_tail;
@ -488,28 +488,28 @@ module mux_tree_tapbuf_size8_mem
assign ccff_tail = mem_out[3];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[2]),
.Q(mem_out[3])
@ -518,20 +518,20 @@ endmodule
module mux_tree_size2_mem
(
pReset,
prog_reset,
prog_clk,
ccff_head,
ccff_tail,
mem_out
);
input pReset;
input prog_reset;
input prog_clk;
input ccff_head;
output ccff_tail;
output [0:1]mem_out;
wire pReset;
wire prog_reset;
wire prog_clk;
wire ccff_head;
wire ccff_tail;
@ -540,14 +540,14 @@ module mux_tree_size2_mem
assign ccff_tail = mem_out[1];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1])
@ -556,20 +556,20 @@ endmodule
module frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem
(
pReset,
prog_reset,
prog_clk,
ccff_head,
ccff_tail,
mem_out
);
input pReset;
input prog_reset;
input prog_clk;
input ccff_head;
output ccff_tail;
output [0:16]mem_out;
wire pReset;
wire prog_reset;
wire prog_clk;
wire ccff_head;
wire ccff_tail;
@ -578,141 +578,141 @@ module frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem
assign ccff_tail = mem_out[16];
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out[0])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[2]),
.Q(mem_out[3])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[3]),
.Q(mem_out[4])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[4]),
.Q(mem_out[5])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[5]),
.Q(mem_out[6])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[6]),
.Q(mem_out[7])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[7]),
.Q(mem_out[8])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[8]),
.Q(mem_out[9])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[9]),
.Q(mem_out[10])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[10]),
.Q(mem_out[11])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[11]),
.Q(mem_out[12])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[12]),
.Q(mem_out[13])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[13]),
.Q(mem_out[14])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[14]),
.Q(mem_out[15])
);
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(mem_out[15]),
.Q(mem_out[16])
);
endmodule
module EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem
module io_sky130_fd_sc_hd__dfrtp_1_mem
(
pReset,
prog_reset,
prog_clk,
ccff_head,
ccff_tail,
mem_out
);
input pReset;
input prog_reset;
input prog_clk;
input ccff_head;
output ccff_tail;
output mem_out;
wire pReset;
wire prog_reset;
wire prog_clk;
wire ccff_head;
wire ccff_tail;
@ -721,7 +721,7 @@ module EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem
assign ccff_tail = mem_out;
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
(
.RESET_B(pReset),
.RESET_B(prog_reset),
.CLK(prog_clk),
.D(ccff_head),
.Q(mem_out)

2
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/user_defined_templates.v
View File

@ -139,7 +139,7 @@ module sky130_fd_sc_hd__dfrtp_1
endmodule
module EMBEDDED_IO_HD
module io
(
IO_ISOL_N,
SOC_IN,

1182
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/fpga_top.v
View File

File diff suppressed because it is too large Load Diff

12
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_clb.v
View File

@ -12,9 +12,9 @@
`default_nettype none
// ----- Verilog module for grid_clb -----
module grid_clb(pReset,
module grid_clb(prog_reset,
prog_clk,
Test_en,
scan_enable,
top_width_0_height_0_subtile_0__pin_I0_0_,
top_width_0_height_0_subtile_0__pin_I0_1_,
top_width_0_height_0_subtile_0__pin_I0i_0_,
@ -74,11 +74,11 @@ module grid_clb(pReset,
bottom_width_0_height_0_subtile_0__pin_cout_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] Test_en;
input [0:0] scan_enable;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I0_0_;
//----- INPUT PORTS -----
@ -211,9 +211,9 @@ output [0:0] ccff_tail;
// ----- END Local output short connections -----
logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 (
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.scan_enable(scan_enable),
.clb_I0({top_width_0_height_0_subtile_0__pin_I0_0_, top_width_0_height_0_subtile_0__pin_I0_1_}),
.clb_I0i({top_width_0_height_0_subtile_0__pin_I0i_0_, top_width_0_height_0_subtile_0__pin_I0i_1_}),
.clb_I1({top_width_0_height_0_subtile_0__pin_I1_0_, top_width_0_height_0_subtile_0__pin_I1_1_}),

60
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_bottom_bottom.v
View File

@ -12,12 +12,12 @@
`default_nettype none
// ----- Verilog module for grid_io_bottom_bottom -----
module grid_io_bottom_bottom(IO_ISOL_N,
pReset,
module grid_io_bottom_bottom(isol_n,
prog_reset,
prog_clk,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_io_soc_in,
gfpga_pad_io_soc_out,
gfpga_pad_io_soc_dir,
top_width_0_height_0_subtile_0__pin_outpad_0_,
top_width_0_height_0_subtile_1__pin_outpad_0_,
top_width_0_height_0_subtile_2__pin_outpad_0_,
@ -29,17 +29,17 @@ module grid_io_bottom_bottom(IO_ISOL_N,
top_width_0_height_0_subtile_3__pin_inpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] IO_ISOL_N;
input [0:0] isol_n;
//----- GLOBAL PORTS -----
input [0:0] pReset;
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIN PORTS -----
input [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
input [0:3] gfpga_pad_io_soc_in;
//----- GPOUT PORTS -----
output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [0:3] gfpga_pad_io_soc_out;
//----- GPOUT PORTS -----
output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
output [0:3] gfpga_pad_io_soc_dir;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_outpad_0_;
//----- INPUT PORTS -----
@ -79,48 +79,48 @@ wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
// ----- END Local output short connections -----
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
.io_outpad(top_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(top_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
.io_outpad(top_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_1__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
.io_outpad(top_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_2__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
.io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_),

60
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_left_left.v
View File

@ -12,12 +12,12 @@
`default_nettype none
// ----- Verilog module for grid_io_left_left -----
module grid_io_left_left(IO_ISOL_N,
pReset,
module grid_io_left_left(isol_n,
prog_reset,
prog_clk,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_io_soc_in,
gfpga_pad_io_soc_out,
gfpga_pad_io_soc_dir,
right_width_0_height_0_subtile_0__pin_outpad_0_,
right_width_0_height_0_subtile_1__pin_outpad_0_,
right_width_0_height_0_subtile_2__pin_outpad_0_,
@ -29,17 +29,17 @@ module grid_io_left_left(IO_ISOL_N,
right_width_0_height_0_subtile_3__pin_inpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] IO_ISOL_N;
input [0:0] isol_n;
//----- GLOBAL PORTS -----
input [0:0] pReset;
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIN PORTS -----
input [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
input [0:3] gfpga_pad_io_soc_in;
//----- GPOUT PORTS -----
output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [0:3] gfpga_pad_io_soc_out;
//----- GPOUT PORTS -----
output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
output [0:3] gfpga_pad_io_soc_dir;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_outpad_0_;
//----- INPUT PORTS -----
@ -79,48 +79,48 @@ wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
// ----- END Local output short connections -----
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
.io_outpad(right_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(right_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
.io_outpad(right_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_1__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
.io_outpad(right_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_2__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
.io_outpad(right_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_3__pin_inpad_0_),

60
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_right_right.v
View File

@ -12,12 +12,12 @@
`default_nettype none
// ----- Verilog module for grid_io_right_right -----
module grid_io_right_right(IO_ISOL_N,
pReset,
module grid_io_right_right(isol_n,
prog_reset,
prog_clk,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_io_soc_in,
gfpga_pad_io_soc_out,
gfpga_pad_io_soc_dir,
left_width_0_height_0_subtile_0__pin_outpad_0_,
left_width_0_height_0_subtile_1__pin_outpad_0_,
left_width_0_height_0_subtile_2__pin_outpad_0_,
@ -29,17 +29,17 @@ module grid_io_right_right(IO_ISOL_N,
left_width_0_height_0_subtile_3__pin_inpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] IO_ISOL_N;
input [0:0] isol_n;
//----- GLOBAL PORTS -----
input [0:0] pReset;
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIN PORTS -----
input [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
input [0:3] gfpga_pad_io_soc_in;
//----- GPOUT PORTS -----
output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [0:3] gfpga_pad_io_soc_out;
//----- GPOUT PORTS -----
output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
output [0:3] gfpga_pad_io_soc_dir;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_0__pin_outpad_0_;
//----- INPUT PORTS -----
@ -79,48 +79,48 @@ wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
// ----- END Local output short connections -----
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
.io_outpad(left_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(left_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
.io_outpad(left_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_1__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
.io_outpad(left_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_2__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
.io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_),

60
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_top_top.v
View File

@ -12,12 +12,12 @@
`default_nettype none
// ----- Verilog module for grid_io_top_top -----
module grid_io_top_top(IO_ISOL_N,
pReset,
module grid_io_top_top(isol_n,
prog_reset,
prog_clk,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
gfpga_pad_io_soc_in,
gfpga_pad_io_soc_out,
gfpga_pad_io_soc_dir,
bottom_width_0_height_0_subtile_0__pin_outpad_0_,
bottom_width_0_height_0_subtile_1__pin_outpad_0_,
bottom_width_0_height_0_subtile_2__pin_outpad_0_,
@ -29,17 +29,17 @@ module grid_io_top_top(IO_ISOL_N,
bottom_width_0_height_0_subtile_3__pin_inpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] IO_ISOL_N;
input [0:0] isol_n;
//----- GLOBAL PORTS -----
input [0:0] pReset;
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIN PORTS -----
input [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
input [0:3] gfpga_pad_io_soc_in;
//----- GPOUT PORTS -----
output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [0:3] gfpga_pad_io_soc_out;
//----- GPOUT PORTS -----
output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
output [0:3] gfpga_pad_io_soc_dir;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_0__pin_outpad_0_;
//----- INPUT PORTS -----
@ -79,48 +79,48 @@ wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
// ----- END Local output short connections -----
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
.io_outpad(bottom_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
.io_outpad(bottom_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
.io_outpad(bottom_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_2__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
.IO_ISOL_N(IO_ISOL_N),
.pReset(pReset),
.isol_n(isol_n),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
.io_outpad(bottom_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_3__pin_inpad_0_),

40
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_clb_.v
View File

@ -12,9 +12,9 @@
`default_nettype none
// ----- Verilog module for logical_tile_clb_mode_clb_ -----
module logical_tile_clb_mode_clb_(pReset,
module logical_tile_clb_mode_clb_(prog_reset,
prog_clk,
Test_en,
scan_enable,
clb_I0,
clb_I0i,
clb_I1,
@ -43,11 +43,11 @@ module logical_tile_clb_mode_clb_(pReset,
clb_cout,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] Test_en;
input [0:0] scan_enable;
//----- INPUT PORTS -----
input [0:1] clb_I0;
//----- INPUT PORTS -----
@ -254,9 +254,9 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
// ----- END Local output short connections -----
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0 (
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.scan_enable(scan_enable),
.fle_in({direct_interc_19_out, direct_interc_20_out, direct_interc_21_out, direct_interc_22_out}),
.fle_reg_in(direct_interc_23_out),
.fle_sc_in(direct_interc_24_out),
@ -271,9 +271,9 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 (
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.scan_enable(scan_enable),
.fle_in({direct_interc_28_out, direct_interc_29_out, direct_interc_30_out, direct_interc_31_out}),
.fle_reg_in(direct_interc_32_out),
.fle_sc_in(direct_interc_33_out),
@ -288,9 +288,9 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 (
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.scan_enable(scan_enable),
.fle_in({direct_interc_37_out, direct_interc_38_out, direct_interc_39_out, direct_interc_40_out}),
.fle_reg_in(direct_interc_41_out),
.fle_sc_in(direct_interc_42_out),
@ -305,9 +305,9 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 (
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.scan_enable(scan_enable),
.fle_in({direct_interc_46_out, direct_interc_47_out, direct_interc_48_out, direct_interc_49_out}),
.fle_reg_in(direct_interc_50_out),
.fle_sc_in(direct_interc_51_out),
@ -322,9 +322,9 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4 (
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.scan_enable(scan_enable),
.fle_in({direct_interc_55_out, direct_interc_56_out, direct_interc_57_out, direct_interc_58_out}),
.fle_reg_in(direct_interc_59_out),
.fle_sc_in(direct_interc_60_out),
@ -339,9 +339,9 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.ccff_tail(logical_tile_clb_mode_default__fle_4_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5 (
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.scan_enable(scan_enable),
.fle_in({direct_interc_64_out, direct_interc_65_out, direct_interc_66_out, direct_interc_67_out}),
.fle_reg_in(direct_interc_68_out),
.fle_sc_in(direct_interc_69_out),
@ -356,9 +356,9 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.ccff_tail(logical_tile_clb_mode_default__fle_5_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6 (
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.scan_enable(scan_enable),
.fle_in({direct_interc_73_out, direct_interc_74_out, direct_interc_75_out, direct_interc_76_out}),
.fle_reg_in(direct_interc_77_out),
.fle_sc_in(direct_interc_78_out),
@ -373,9 +373,9 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
.ccff_tail(logical_tile_clb_mode_default__fle_6_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 (
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.scan_enable(scan_enable),
.fle_in({direct_interc_82_out, direct_interc_83_out, direct_interc_84_out, direct_interc_85_out}),
.fle_reg_in(direct_interc_86_out),
.fle_sc_in(direct_interc_87_out),

12
SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle.v
View File

@ -12,9 +12,9 @@
`default_nettype none
// ----- Verilog module for logical_tile_clb_mode_default__fle -----
module logical_tile_clb_mode_default__fle(pReset,
module logical_tile_clb_mode_default__fle(prog_reset,
prog_clk,
Test_en,
scan_enable,
fle_in,
fle_reg_in,
fle_sc_in,
@ -28,11 +28,11 @@ module logical_tile_clb_mode_default__fle(pReset,
fle_cout,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
input [0:0] prog_reset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] Test_en;
input [0:0] scan_enable;
//----- INPUT PORTS -----
input [0:3] fle_in;
//----- INPUT PORTS -----
@ -96,9 +96,9 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_
// ----- END Local output short connections -----
logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
.pReset(pReset),
.prog_reset(prog_reset),
.prog_clk(prog_clk),
.Test_en(Test_en),
.scan_enable(scan_enable),
.fabric_in({direct_interc_5_out, direct_interc_6_out, direct_interc_7_out, direct_interc_8_out}),
.fabric_reg_in(direct_interc_9_out),
.fabric_sc_in(direct_interc_10_out),

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