diff --git a/SOFA_A/CommonFiles/restructure_fabric_sofa_a.py b/SOFA_A/CommonFiles/restructure_fabric_sofa_a.py
index ccc1cce..4172e4a 100644
--- a/SOFA_A/CommonFiles/restructure_fabric_sofa_a.py
+++ b/SOFA_A/CommonFiles/restructure_fabric_sofa_a.py
@@ -218,6 +218,15 @@ def main():
             shapes[module]["PLACEMENT"][1] += 1
 
     fpga.create_placement()
+    # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+    # Feedthrough generation
+    # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+    instance_map = [[0 for _ in range(FPGA_HEIGHT + 1)]
+                    for _ in range(FPGA_WIDTH + 1)]
+    for inst in fpga.top_module.get_instances():
+        _, x, _, y, _ = inst.name.rsplit("_", 4)
+        instance_map[int(x)][int(y)] = inst.name
+    # create_global_feedthrough(fpga, "reset", instance_map)
 
     filename = SVG_DIR + f"{PROJ_NAME}_pre_tile_floorplan.svg"
     save_tiling_floorplan(fpga, filename, STYLE_SHEET=STYLE_SHEET)
@@ -234,6 +243,34 @@ def main():
     logger.info("Saved floorplan in %s", filename)
     # save_netlist_outline(fpga)
 
+
+def create_global_feedthrough(
+    fpga: OpenFPGA, signal, instance_map, down_port=None, top_cable=None
+):
+    """
+    This creates global feedthroughs
+    """
+    logger.debug("create_global_feedthrough [%s]", signal)
+    with open(PICKLE_DIR + f"{signal}_pattern.pickle", "rb") as fp:
+        sig_conn_patt: ConnectPointList = pickle.load(fp)
+    sig_conn_patt.get_top_instance_name = lambda x, y: instance_map[x][y]
+    signal_cable = next(fpga.top_module.get_cables(signal), None)
+    if not signal_cable:
+        signal_cable = fpga.top_module.create_cable(signal, wires=1)
+    else:
+        for pin in list(signal_cable.wires[0].pins):
+            if isinstance(pin, sdn.OuterPin):
+                signal_cable.wires[0].disconnect_pin(pin)
+    sig_conn_patt.create_ft_ports(fpga.netlist, signal, signal_cable)
+    sig_conn_patt.create_ft_connection(
+        fpga.netlist,
+        signal_cable,
+        down_port=down_port,
+        top_cable=top_cable or signal_cable,
+    )
+    rpt_file = f"{RELEASE_DIR}/rpts/pre_pnr/{signal}_ports.txt"
+    sig_conn_patt.print_port_stat(fpga.netlist, filename=rpt_file)
+
 def save_tiling_floorplan(fpga: OpenFPGA, filename: str, STYLE_SHEET=None):
     """
     Save currnt tiling strategy to SVG file
diff --git a/SOFA_A/FPGA88_SOFA_A/.spydrnet b/SOFA_A/FPGA88_SOFA_A/.spydrnet
index ee64190..ff14fc5 100644
--- a/SOFA_A/FPGA88_SOFA_A/.spydrnet
+++ b/SOFA_A/FPGA88_SOFA_A/.spydrnet
@@ -1 +1 @@
-spydrnet_physical
+spydrnet_physical
\ No newline at end of file
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/arch/openfpga_arch.xml b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/arch/openfpga_arch.xml
index aa409a0..6e273ea 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/arch/openfpga_arch.xml
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/arch/openfpga_arch.xml
@@ -154,7 +154,7 @@
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <port type="input" prefix="D" size="1"/>
       <port type="input" prefix="DI" lib_name="SCD" size="1"/>
-      <port type="input" prefix="Test_en" lib_name="SCE" size="1" is_global="true" default_val="0"/>
+      <port type="input" prefix="scan_enable" lib_name="SCE" size="1" is_global="true" default_val="0"/>
       <port type="input" prefix="reset" lib_name="RESET_B" size="1" default_val="1"/>
       <port type="output" prefix="Q" size="1"/>
       <port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="false" default_val="0" />
@@ -182,16 +182,16 @@
       <port type="input" prefix="D" size="1"/>
       <port type="output" prefix="Q" size="1"/>
       <port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
-      <port type="input" prefix="pReset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_prog="true" is_reset="true"/>
+      <port type="input" prefix="prog_reset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_prog="true" is_reset="true"/>
     </circuit_model>
-    <circuit_model type="iopad" name="EMBEDDED_IO_HD" prefix="EMBEDDED_IO_HD" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v">
+    <circuit_model type="iopad" name="io" prefix="io" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
       <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
-      <port type="input" prefix="SOC_IN" lib_name="SOC_IN" size="1" is_global="true" is_io="true" is_data_io="true"/>
-      <port type="output" prefix="SOC_OUT" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/>
-      <port type="output" prefix="SOC_DIR" lib_name="SOC_DIR" size="1" is_global="true" is_io="true"/>
-      <port type="input" prefix="IO_ISOL_N" lib_name="IO_ISOL_N" size="1" is_global="true" default_val="1"/>
+      <port type="input" prefix="soc_in" lib_name="SOC_IN" size="1" is_global="true" is_io="true" is_data_io="true"/>
+      <port type="output" prefix="soc_out" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/>
+      <port type="output" prefix="soc_dir" lib_name="SOC_DIR" size="1" is_global="true" is_io="true"/>
+      <port type="input" prefix="isol_n" lib_name="IO_ISOL_N" size="1" is_global="true" default_val="1"/>
       <port type="output" prefix="inpad" lib_name="FPGA_IN" size="1"/>
       <port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
       <port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfrtp_1" default_val="1"/>
@@ -232,7 +232,7 @@
       <global_port name="clk" is_clock="true" default_val="0">
           <tile name="clb" port="clk" x="-1" y="-1"/>
       </global_port>
-      <global_port name="Reset" is_reset="true" default_val="1">
+      <global_port name="reset" is_reset="true" default_val="1">
           <tile name="clb" port="reset" x="-1" y="-1"/>
       </global_port>
   </tile_annotations>
@@ -240,7 +240,7 @@
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
     <!-- IMPORTANT: must set unused I/Os to operating in INPUT mode !!! -->
-    <pb_type name="io[physical].iopad" circuit_model_name="EMBEDDED_IO_HD" mode_bits="1"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="io" mode_bits="1"/>
     <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
     <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
     <!-- End physical pb_type binding in complex block IO -->
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fabric_netlists.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fabric_netlists.v
index 8ed58ab..969d686 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fabric_netlists.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fabric_netlists.v
@@ -1,6 +1,4 @@
 `include "./SRC/fpga_top.v"
-`include "./SRC/submodules/EMBEDDED_IO_HD.v"
-`include "./SRC/submodules/EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.v"
 `include "./SRC/submodules/cbx_1__0_.v"
 `include "./SRC/submodules/cbx_1__0__old.v"
 `include "./SRC/submodules/cbx_1__1_.v"
@@ -22,6 +20,7 @@
 `include "./SRC/submodules/grid_io_left_left.v"
 `include "./SRC/submodules/grid_io_right_right.v"
 `include "./SRC/submodules/grid_io_top_top.v"
+`include "./SRC/submodules/io_sky130_fd_sc_hd__dfrtp_1_mem.v"
 `include "./SRC/submodules/logical_tile_clb_mode_clb_.v"
 `include "./SRC/submodules/logical_tile_clb_mode_default__fle.v"
 `include "./SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric.v"
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fpga_top.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fpga_top.v
index f79db83..db6e0a4 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fpga_top.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/fpga_top.v
@@ -2,34 +2,31 @@
 //netlist name: FPGA88_SOFA_A
 module fpga_top
 (
-    IO_ISOL_N,
-    Reset,
-    Test_en,
     ccff_head,
     clk,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    pReset,
+    gfpga_pad_io_soc_in,
+    isol_n,
     prog_clk,
+    prog_reset,
+    reset,
+    scan_enable,
     ccff_tail,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT
+    gfpga_pad_io_soc_dir,
+    gfpga_pad_io_soc_out
 );
 
-    input IO_ISOL_N;
-    input Reset;
-    input Test_en;
     input ccff_head;
     input clk;
-    input [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    input pReset;
+    input [0:127]gfpga_pad_io_soc_in;
+    input isol_n;
     input prog_clk;
+    input prog_reset;
+    input reset;
+    input scan_enable;
     output ccff_tail;
-    output [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    output [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output [0:127]gfpga_pad_io_soc_dir;
+    output [0:127]gfpga_pad_io_soc_out;
 
-    wire IO_ISOL_N;
-    wire Reset;
-    wire Test_en;
     wire cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;
     wire cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_;
     wire cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -2816,9 +2813,9 @@ module fpga_top
     wire direct_interc_98_out;
     wire direct_interc_99_out;
     wire direct_interc_9_out;
-    wire [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    wire [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    wire [0:127]gfpga_pad_io_soc_dir;
+    wire [0:127]gfpga_pad_io_soc_in;
+    wire [0:127]gfpga_pad_io_soc_out;
     wire grid_clb_0_bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
     wire grid_clb_0_ccff_tail;
     wire grid_clb_0_right_width_0_height_0_subtile_0__pin_O_10_;
@@ -4275,8 +4272,10 @@ module fpga_top
     wire grid_io_top_top_7_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
     wire grid_io_top_top_7_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
     wire grid_io_top_top_7_ccff_tail;
-    wire pReset;
+    wire isol_n;
     wire prog_clk;
+    wire prog_reset;
+    wire reset;
     wire sb_0__0__0_ccff_tail;
     wire [0:29]sb_0__0__0_chanx_right_out;
     wire [0:29]sb_0__0__0_chany_top_out;
@@ -4646,14 +4645,15 @@ module fpga_top
     wire sb_8__8__0_ccff_tail;
     wire [0:29]sb_8__8__0_chanx_left_out;
     wire [0:29]sb_8__8__0_chany_bottom_out;
+    wire scan_enable;
 
     bottom_left_tile tile_1__1_
     (
         .ccff_head(grid_io_left_left_1_ccff_tail),
         .chanx_right_in(cbx_1__0__0_chanx_left_out),
         .chany_top_in(cby_0__1__0_chany_bottom_out),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_0__pin_inpad_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -4668,15 +4668,15 @@ module fpga_top
     );
     left_tile tile_1__2_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(grid_io_left_left_2_ccff_tail),
         .ccff_head_0(sb_0__0__0_ccff_tail),
         .chanx_right_in(cbx_1__1__0_chanx_left_out),
         .chany_bottom_in(sb_0__0__0_chany_top_out),
         .chany_top_in_0(cby_0__1__1_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96:99]),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[96:99]),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -4694,8 +4694,8 @@ module fpga_top
         .chanx_right_out(sb_0__1__0_chanx_right_out),
         .chany_bottom_out(cby_0__1__0_chany_bottom_out),
         .chany_top_out_0(sb_0__1__0_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96:99]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96:99]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[96:99]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[96:99]),
         .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_),
         .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -4703,15 +4703,15 @@ module fpga_top
     );
     left_tile tile_1__3_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(grid_io_left_left_3_ccff_tail),
         .ccff_head_0(sb_0__1__0_ccff_tail),
         .chanx_right_in(cbx_1__1__1_chanx_left_out),
         .chany_bottom_in(sb_0__1__0_chany_top_out),
         .chany_top_in_0(cby_0__1__2_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100:103]),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[100:103]),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -4729,8 +4729,8 @@ module fpga_top
         .chanx_right_out(sb_0__1__1_chanx_right_out),
         .chany_bottom_out(cby_0__1__1_chany_bottom_out),
         .chany_top_out_0(sb_0__1__1_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[100:103]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100:103]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[100:103]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[100:103]),
         .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_),
         .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -4738,15 +4738,15 @@ module fpga_top
     );
     left_tile tile_1__4_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(grid_io_left_left_4_ccff_tail),
         .ccff_head_0(sb_0__1__1_ccff_tail),
         .chanx_right_in(cbx_1__1__2_chanx_left_out),
         .chany_bottom_in(sb_0__1__1_chany_top_out),
         .chany_top_in_0(cby_0__1__3_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104:107]),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[104:107]),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -4764,8 +4764,8 @@ module fpga_top
         .chanx_right_out(sb_0__1__2_chanx_right_out),
         .chany_bottom_out(cby_0__1__2_chany_bottom_out),
         .chany_top_out_0(sb_0__1__2_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[104:107]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104:107]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[104:107]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[104:107]),
         .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_),
         .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -4773,15 +4773,15 @@ module fpga_top
     );
     left_tile tile_1__5_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(grid_io_left_left_5_ccff_tail),
         .ccff_head_0(sb_0__1__2_ccff_tail),
         .chanx_right_in(cbx_1__1__3_chanx_left_out),
         .chany_bottom_in(sb_0__1__2_chany_top_out),
         .chany_top_in_0(cby_0__1__4_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108:111]),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[108:111]),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -4799,8 +4799,8 @@ module fpga_top
         .chanx_right_out(sb_0__1__3_chanx_right_out),
         .chany_bottom_out(cby_0__1__3_chany_bottom_out),
         .chany_top_out_0(sb_0__1__3_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[108:111]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108:111]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[108:111]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[108:111]),
         .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_),
         .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -4808,15 +4808,15 @@ module fpga_top
     );
     left_tile tile_1__6_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(grid_io_left_left_6_ccff_tail),
         .ccff_head_0(sb_0__1__3_ccff_tail),
         .chanx_right_in(cbx_1__1__4_chanx_left_out),
         .chany_bottom_in(sb_0__1__3_chany_top_out),
         .chany_top_in_0(cby_0__1__5_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112:115]),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[112:115]),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -4834,8 +4834,8 @@ module fpga_top
         .chanx_right_out(sb_0__1__4_chanx_right_out),
         .chany_bottom_out(cby_0__1__4_chany_bottom_out),
         .chany_top_out_0(sb_0__1__4_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[112:115]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112:115]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[112:115]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[112:115]),
         .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_),
         .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -4843,15 +4843,15 @@ module fpga_top
     );
     left_tile tile_1__7_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(grid_io_left_left_7_ccff_tail),
         .ccff_head_0(sb_0__1__4_ccff_tail),
         .chanx_right_in(cbx_1__1__5_chanx_left_out),
         .chany_bottom_in(sb_0__1__4_chany_top_out),
         .chany_top_in_0(cby_0__1__6_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116:119]),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[116:119]),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -4869,8 +4869,8 @@ module fpga_top
         .chanx_right_out(sb_0__1__5_chanx_right_out),
         .chany_bottom_out(cby_0__1__5_chany_bottom_out),
         .chany_top_out_0(sb_0__1__5_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[116:119]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116:119]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[116:119]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[116:119]),
         .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_),
         .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -4878,15 +4878,15 @@ module fpga_top
     );
     left_tile tile_1__8_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(sb_0__8__0_ccff_tail),
         .ccff_head_0(sb_0__1__5_ccff_tail),
         .chanx_right_in(cbx_1__1__6_chanx_left_out),
         .chany_bottom_in(sb_0__1__5_chany_top_out),
         .chany_top_in_0(cby_0__1__7_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120:123]),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[120:123]),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -4904,8 +4904,8 @@ module fpga_top
         .chanx_right_out(sb_0__1__6_chanx_right_out),
         .chany_bottom_out(cby_0__1__6_chany_bottom_out),
         .chany_top_out_0(sb_0__1__6_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[120:123]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120:123]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[120:123]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[120:123]),
         .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_),
         .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -4913,14 +4913,14 @@ module fpga_top
     );
     top_left_tile tile_1__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(grid_io_top_top_0_ccff_tail),
         .ccff_head_0(sb_0__1__6_ccff_tail),
         .chanx_right_in(cbx_1__8__0_chanx_left_out),
         .chany_bottom_in_0(sb_0__1__6_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124:127]),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[124:127]),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -4937,8 +4937,8 @@ module fpga_top
         .ccff_tail_0(grid_io_left_left_7_ccff_tail),
         .chanx_right_out(sb_0__8__0_chanx_right_out),
         .chany_bottom_out_0(cby_0__1__7_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[124:127]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124:127]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[124:127]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[124:127]),
         .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_),
         .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -4946,15 +4946,15 @@ module fpga_top
     );
     bottom_tile tile_2__1_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(ccff_head),
         .ccff_head_1(grid_io_left_left_0_ccff_tail),
         .chanx_left_in(sb_0__0__0_chanx_right_out),
         .chanx_right_in_0(cbx_1__0__1_chanx_left_out),
         .chany_top_in(cby_1__1__0_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92:95]),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[92:95]),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_0__pin_inpad_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -4972,8 +4972,8 @@ module fpga_top
         .chanx_left_out(cbx_1__0__0_chanx_left_out),
         .chanx_right_out_0(sb_1__0__0_chanx_right_out),
         .chany_top_out(sb_1__0__0_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[92:95]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92:95]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[92:95]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[92:95]),
         .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_0__pin_inpad_0_),
         .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_1__pin_inpad_0_),
         .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_7_top_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -4981,7 +4981,6 @@ module fpga_top
     );
     tile tile_2__2_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__0__0_ccff_tail),
         .ccff_head_2(grid_clb_9_ccff_tail),
         .chanx_left_in(sb_0__1__0_chanx_right_out),
@@ -4989,9 +4988,9 @@ module fpga_top
         .chany_bottom_in(sb_1__0__0_chany_top_out),
         .chany_top_in_0(cby_1__1__1_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -5000,6 +4999,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -5039,7 +5039,6 @@ module fpga_top
     );
     tile tile_2__3_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__0_ccff_tail),
         .ccff_head_2(grid_clb_1_ccff_tail),
         .chanx_left_in(sb_0__1__1_chanx_right_out),
@@ -5047,9 +5046,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__0_chany_top_out),
         .chany_top_in_0(cby_1__1__2_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -5058,6 +5057,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -5097,7 +5097,6 @@ module fpga_top
     );
     tile tile_2__4_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__1_ccff_tail),
         .ccff_head_2(grid_clb_11_ccff_tail),
         .chanx_left_in(sb_0__1__2_chanx_right_out),
@@ -5105,9 +5104,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__1_chany_top_out),
         .chany_top_in_0(cby_1__1__3_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -5116,6 +5115,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -5155,7 +5155,6 @@ module fpga_top
     );
     tile tile_2__5_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__2_ccff_tail),
         .ccff_head_2(grid_clb_3_ccff_tail),
         .chanx_left_in(sb_0__1__3_chanx_right_out),
@@ -5163,9 +5162,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__2_chany_top_out),
         .chany_top_in_0(cby_1__1__4_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -5174,6 +5173,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -5213,7 +5213,6 @@ module fpga_top
     );
     tile tile_2__6_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__3_ccff_tail),
         .ccff_head_2(grid_clb_13_ccff_tail),
         .chanx_left_in(sb_0__1__4_chanx_right_out),
@@ -5221,9 +5220,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__3_chany_top_out),
         .chany_top_in_0(cby_1__1__5_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -5232,6 +5231,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -5271,7 +5271,6 @@ module fpga_top
     );
     tile tile_2__7_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__4_ccff_tail),
         .ccff_head_2(grid_clb_5_ccff_tail),
         .chanx_left_in(sb_0__1__5_chanx_right_out),
@@ -5279,9 +5278,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__4_chany_top_out),
         .chany_top_in_0(cby_1__1__6_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -5290,6 +5289,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -5329,7 +5329,6 @@ module fpga_top
     );
     tile tile_2__8_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__5_ccff_tail),
         .ccff_head_2(grid_clb_15_ccff_tail),
         .chanx_left_in(sb_0__1__6_chanx_right_out),
@@ -5337,9 +5336,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__5_chany_top_out),
         .chany_top_in_0(cby_1__1__7_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -5348,6 +5347,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -5387,18 +5387,17 @@ module fpga_top
     );
     top_tile tile_2__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__6_ccff_tail),
         .ccff_head_2(grid_io_top_top_1_ccff_tail),
         .chanx_left_in(sb_0__8__0_chanx_right_out),
         .chanx_right_in_0(cbx_1__8__1_chanx_left_out),
         .chany_bottom_in(sb_1__1__6_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:3]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0:3]),
+        .isol_n(isol_n),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -5411,6 +5410,7 @@ module fpga_top
         .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
         .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_),
         .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_),
         .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_1__8__undriven_top_width_0_height_0_subtile_0__pin_sc_in_0_),
@@ -5426,8 +5426,8 @@ module fpga_top
         .chanx_left_out(cbx_1__8__0_chanx_left_out),
         .chanx_right_out_0(sb_1__8__0_chanx_right_out),
         .chany_bottom_out(cby_1__1__7_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:3]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0:3]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0:3]),
         .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_10_),
         .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_11_),
         .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -5447,15 +5447,15 @@ module fpga_top
     );
     bottom_tile tile_3__1_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(grid_io_bottom_bottom_7_ccff_tail),
         .ccff_head_1(grid_clb_0_ccff_tail),
         .chanx_left_in(sb_1__0__0_chanx_right_out),
         .chanx_right_in_0(cbx_1__0__2_chanx_left_out),
         .chany_top_in(cby_1__1__8_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88:91]),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[88:91]),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_0__pin_inpad_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -5473,8 +5473,8 @@ module fpga_top
         .chanx_left_out(cbx_1__0__1_chanx_left_out),
         .chanx_right_out_0(sb_1__0__1_chanx_right_out),
         .chany_top_out(sb_1__0__1_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[88:91]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88:91]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[88:91]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[88:91]),
         .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_0__pin_inpad_0_),
         .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_1__pin_inpad_0_),
         .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_6_top_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -5482,7 +5482,6 @@ module fpga_top
     );
     tile tile_3__2_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__0__1_ccff_tail),
         .ccff_head_2(grid_clb_17_ccff_tail),
         .chanx_left_in(sb_1__1__0_chanx_right_out),
@@ -5490,9 +5489,9 @@ module fpga_top
         .chany_bottom_in(sb_1__0__1_chany_top_out),
         .chany_top_in_0(cby_1__1__9_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -5501,6 +5500,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -5540,7 +5540,6 @@ module fpga_top
     );
     tile tile_3__3_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__7_ccff_tail),
         .ccff_head_2(grid_clb_2_ccff_tail),
         .chanx_left_in(sb_1__1__1_chanx_right_out),
@@ -5548,9 +5547,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__7_chany_top_out),
         .chany_top_in_0(cby_1__1__10_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -5559,6 +5558,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -5598,7 +5598,6 @@ module fpga_top
     );
     tile tile_3__4_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__8_ccff_tail),
         .ccff_head_2(grid_clb_19_ccff_tail),
         .chanx_left_in(sb_1__1__2_chanx_right_out),
@@ -5606,9 +5605,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__8_chany_top_out),
         .chany_top_in_0(cby_1__1__11_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -5617,6 +5616,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -5656,7 +5656,6 @@ module fpga_top
     );
     tile tile_3__5_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__9_ccff_tail),
         .ccff_head_2(grid_clb_4_ccff_tail),
         .chanx_left_in(sb_1__1__3_chanx_right_out),
@@ -5664,9 +5663,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__9_chany_top_out),
         .chany_top_in_0(cby_1__1__12_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -5675,6 +5674,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -5714,7 +5714,6 @@ module fpga_top
     );
     tile tile_3__6_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__10_ccff_tail),
         .ccff_head_2(grid_clb_21_ccff_tail),
         .chanx_left_in(sb_1__1__4_chanx_right_out),
@@ -5722,9 +5721,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__10_chany_top_out),
         .chany_top_in_0(cby_1__1__13_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -5733,6 +5732,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -5772,7 +5772,6 @@ module fpga_top
     );
     tile tile_3__7_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__11_ccff_tail),
         .ccff_head_2(grid_clb_6_ccff_tail),
         .chanx_left_in(sb_1__1__5_chanx_right_out),
@@ -5780,9 +5779,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__11_chany_top_out),
         .chany_top_in_0(cby_1__1__14_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -5791,6 +5790,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -5830,7 +5830,6 @@ module fpga_top
     );
     tile tile_3__8_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__12_ccff_tail),
         .ccff_head_2(grid_clb_23_ccff_tail),
         .chanx_left_in(sb_1__1__6_chanx_right_out),
@@ -5838,9 +5837,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__12_chany_top_out),
         .chany_top_in_0(cby_1__1__15_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -5849,6 +5848,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -5888,18 +5888,17 @@ module fpga_top
     );
     top_tile tile_3__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__13_ccff_tail),
         .ccff_head_2(grid_io_top_top_2_ccff_tail),
         .chanx_left_in(sb_1__8__0_chanx_right_out),
         .chanx_right_in_0(cbx_1__8__2_chanx_left_out),
         .chany_bottom_in(sb_1__1__13_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4:7]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[4:7]),
+        .isol_n(isol_n),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -5912,6 +5911,7 @@ module fpga_top
         .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
         .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_2__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_),
         .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_2__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_),
         .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_sc_out_0_),
@@ -5927,8 +5927,8 @@ module fpga_top
         .chanx_left_out(cbx_1__8__1_chanx_left_out),
         .chanx_right_out_0(sb_1__8__1_chanx_right_out),
         .chany_bottom_out(cby_1__1__15_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4:7]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4:7]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[4:7]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[4:7]),
         .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_10_),
         .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_11_),
         .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -5948,15 +5948,15 @@ module fpga_top
     );
     bottom_tile tile_4__1_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(grid_io_bottom_bottom_6_ccff_tail),
         .ccff_head_1(grid_clb_8_ccff_tail),
         .chanx_left_in(sb_1__0__1_chanx_right_out),
         .chanx_right_in_0(cbx_1__0__3_chanx_left_out),
         .chany_top_in(cby_1__1__16_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84:87]),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[84:87]),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_0__pin_inpad_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -5974,8 +5974,8 @@ module fpga_top
         .chanx_left_out(cbx_1__0__2_chanx_left_out),
         .chanx_right_out_0(sb_1__0__2_chanx_right_out),
         .chany_top_out(sb_1__0__2_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[84:87]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84:87]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[84:87]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[84:87]),
         .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_0__pin_inpad_0_),
         .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_1__pin_inpad_0_),
         .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_5_top_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -5983,7 +5983,6 @@ module fpga_top
     );
     tile tile_4__2_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__0__2_ccff_tail),
         .ccff_head_2(grid_clb_25_ccff_tail),
         .chanx_left_in(sb_1__1__7_chanx_right_out),
@@ -5991,9 +5990,9 @@ module fpga_top
         .chany_bottom_in(sb_1__0__2_chany_top_out),
         .chany_top_in_0(cby_1__1__17_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -6002,6 +6001,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -6041,7 +6041,6 @@ module fpga_top
     );
     tile tile_4__3_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__14_ccff_tail),
         .ccff_head_2(grid_clb_10_ccff_tail),
         .chanx_left_in(sb_1__1__8_chanx_right_out),
@@ -6049,9 +6048,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__14_chany_top_out),
         .chany_top_in_0(cby_1__1__18_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -6060,6 +6059,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -6099,7 +6099,6 @@ module fpga_top
     );
     tile tile_4__4_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__15_ccff_tail),
         .ccff_head_2(grid_clb_27_ccff_tail),
         .chanx_left_in(sb_1__1__9_chanx_right_out),
@@ -6107,9 +6106,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__15_chany_top_out),
         .chany_top_in_0(cby_1__1__19_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -6118,6 +6117,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -6157,7 +6157,6 @@ module fpga_top
     );
     tile tile_4__5_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__16_ccff_tail),
         .ccff_head_2(grid_clb_12_ccff_tail),
         .chanx_left_in(sb_1__1__10_chanx_right_out),
@@ -6165,9 +6164,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__16_chany_top_out),
         .chany_top_in_0(cby_1__1__20_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -6176,6 +6175,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -6215,7 +6215,6 @@ module fpga_top
     );
     tile tile_4__6_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__17_ccff_tail),
         .ccff_head_2(grid_clb_29_ccff_tail),
         .chanx_left_in(sb_1__1__11_chanx_right_out),
@@ -6223,9 +6222,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__17_chany_top_out),
         .chany_top_in_0(cby_1__1__21_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -6234,6 +6233,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -6273,7 +6273,6 @@ module fpga_top
     );
     tile tile_4__7_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__18_ccff_tail),
         .ccff_head_2(grid_clb_14_ccff_tail),
         .chanx_left_in(sb_1__1__12_chanx_right_out),
@@ -6281,9 +6280,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__18_chany_top_out),
         .chany_top_in_0(cby_1__1__22_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -6292,6 +6291,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -6331,7 +6331,6 @@ module fpga_top
     );
     tile tile_4__8_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__19_ccff_tail),
         .ccff_head_2(grid_clb_31_ccff_tail),
         .chanx_left_in(sb_1__1__13_chanx_right_out),
@@ -6339,9 +6338,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__19_chany_top_out),
         .chany_top_in_0(cby_1__1__23_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -6350,6 +6349,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -6389,18 +6389,17 @@ module fpga_top
     );
     top_tile tile_4__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__20_ccff_tail),
         .ccff_head_2(grid_io_top_top_3_ccff_tail),
         .chanx_left_in(sb_1__8__1_chanx_right_out),
         .chanx_right_in_0(cbx_1__8__3_chanx_left_out),
         .chany_bottom_in(sb_1__1__20_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8:11]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[8:11]),
+        .isol_n(isol_n),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -6413,6 +6412,7 @@ module fpga_top
         .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
         .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_3__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_),
         .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_3__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_),
         .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_8_bottom_width_0_height_0_subtile_0__pin_sc_out_0_),
@@ -6428,8 +6428,8 @@ module fpga_top
         .chanx_left_out(cbx_1__8__2_chanx_left_out),
         .chanx_right_out_0(sb_1__8__2_chanx_right_out),
         .chany_bottom_out(cby_1__1__23_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8:11]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8:11]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[8:11]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[8:11]),
         .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_10_),
         .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_11_),
         .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -6449,15 +6449,15 @@ module fpga_top
     );
     bottom_tile tile_5__1_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(grid_io_bottom_bottom_5_ccff_tail),
         .ccff_head_1(grid_clb_16_ccff_tail),
         .chanx_left_in(sb_1__0__2_chanx_right_out),
         .chanx_right_in_0(cbx_1__0__4_chanx_left_out),
         .chany_top_in(cby_1__1__24_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80:83]),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[80:83]),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -6475,8 +6475,8 @@ module fpga_top
         .chanx_left_out(cbx_1__0__3_chanx_left_out),
         .chanx_right_out_0(sb_1__0__3_chanx_right_out),
         .chany_top_out(sb_1__0__3_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[80:83]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80:83]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[80:83]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[80:83]),
         .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_0__pin_inpad_0_),
         .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_1__pin_inpad_0_),
         .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_4_top_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -6484,7 +6484,6 @@ module fpga_top
     );
     tile tile_5__2_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__0__3_ccff_tail),
         .ccff_head_2(grid_clb_33_ccff_tail),
         .chanx_left_in(sb_1__1__14_chanx_right_out),
@@ -6492,9 +6491,9 @@ module fpga_top
         .chany_bottom_in(sb_1__0__3_chany_top_out),
         .chany_top_in_0(cby_1__1__25_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -6503,6 +6502,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -6542,7 +6542,6 @@ module fpga_top
     );
     tile tile_5__3_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__21_ccff_tail),
         .ccff_head_2(grid_clb_18_ccff_tail),
         .chanx_left_in(sb_1__1__15_chanx_right_out),
@@ -6550,9 +6549,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__21_chany_top_out),
         .chany_top_in_0(cby_1__1__26_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -6561,6 +6560,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -6600,7 +6600,6 @@ module fpga_top
     );
     tile tile_5__4_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__22_ccff_tail),
         .ccff_head_2(grid_clb_35_ccff_tail),
         .chanx_left_in(sb_1__1__16_chanx_right_out),
@@ -6608,9 +6607,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__22_chany_top_out),
         .chany_top_in_0(cby_1__1__27_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -6619,6 +6618,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -6658,7 +6658,6 @@ module fpga_top
     );
     tile tile_5__5_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__23_ccff_tail),
         .ccff_head_2(grid_clb_20_ccff_tail),
         .chanx_left_in(sb_1__1__17_chanx_right_out),
@@ -6666,9 +6665,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__23_chany_top_out),
         .chany_top_in_0(cby_1__1__28_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -6677,6 +6676,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -6716,7 +6716,6 @@ module fpga_top
     );
     tile tile_5__6_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__24_ccff_tail),
         .ccff_head_2(grid_clb_37_ccff_tail),
         .chanx_left_in(sb_1__1__18_chanx_right_out),
@@ -6724,9 +6723,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__24_chany_top_out),
         .chany_top_in_0(cby_1__1__29_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -6735,6 +6734,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -6774,7 +6774,6 @@ module fpga_top
     );
     tile tile_5__7_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__25_ccff_tail),
         .ccff_head_2(grid_clb_22_ccff_tail),
         .chanx_left_in(sb_1__1__19_chanx_right_out),
@@ -6782,9 +6781,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__25_chany_top_out),
         .chany_top_in_0(cby_1__1__30_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -6793,6 +6792,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -6832,7 +6832,6 @@ module fpga_top
     );
     tile tile_5__8_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__26_ccff_tail),
         .ccff_head_2(grid_clb_39_ccff_tail),
         .chanx_left_in(sb_1__1__20_chanx_right_out),
@@ -6840,9 +6839,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__26_chany_top_out),
         .chany_top_in_0(cby_1__1__31_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -6851,6 +6850,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -6890,18 +6890,17 @@ module fpga_top
     );
     top_tile tile_5__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__27_ccff_tail),
         .ccff_head_2(grid_io_top_top_4_ccff_tail),
         .chanx_left_in(sb_1__8__2_chanx_right_out),
         .chanx_right_in_0(cbx_1__8__4_chanx_left_out),
         .chany_bottom_in(sb_1__1__27_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12:15]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[12:15]),
+        .isol_n(isol_n),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -6914,6 +6913,7 @@ module fpga_top
         .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
         .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_4__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_),
         .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_4__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_),
         .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_16_bottom_width_0_height_0_subtile_0__pin_sc_out_0_),
@@ -6929,8 +6929,8 @@ module fpga_top
         .chanx_left_out(cbx_1__8__3_chanx_left_out),
         .chanx_right_out_0(sb_1__8__3_chanx_right_out),
         .chany_bottom_out(cby_1__1__31_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12:15]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12:15]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[12:15]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[12:15]),
         .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_10_),
         .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_11_),
         .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -6950,15 +6950,15 @@ module fpga_top
     );
     bottom_tile tile_6__1_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(grid_io_bottom_bottom_4_ccff_tail),
         .ccff_head_1(grid_clb_24_ccff_tail),
         .chanx_left_in(sb_1__0__3_chanx_right_out),
         .chanx_right_in_0(cbx_1__0__5_chanx_left_out),
         .chany_top_in(cby_1__1__32_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76:79]),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[76:79]),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -6976,8 +6976,8 @@ module fpga_top
         .chanx_left_out(cbx_1__0__4_chanx_left_out),
         .chanx_right_out_0(sb_1__0__4_chanx_right_out),
         .chany_top_out(sb_1__0__4_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[76:79]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76:79]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[76:79]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[76:79]),
         .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_),
         .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_),
         .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -6985,7 +6985,6 @@ module fpga_top
     );
     tile tile_6__2_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__0__4_ccff_tail),
         .ccff_head_2(grid_clb_41_ccff_tail),
         .chanx_left_in(sb_1__1__21_chanx_right_out),
@@ -6993,9 +6992,9 @@ module fpga_top
         .chany_bottom_in(sb_1__0__4_chany_top_out),
         .chany_top_in_0(cby_1__1__33_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -7004,6 +7003,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -7043,7 +7043,6 @@ module fpga_top
     );
     tile tile_6__3_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__28_ccff_tail),
         .ccff_head_2(grid_clb_26_ccff_tail),
         .chanx_left_in(sb_1__1__22_chanx_right_out),
@@ -7051,9 +7050,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__28_chany_top_out),
         .chany_top_in_0(cby_1__1__34_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -7062,6 +7061,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -7101,7 +7101,6 @@ module fpga_top
     );
     tile tile_6__4_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__29_ccff_tail),
         .ccff_head_2(grid_clb_43_ccff_tail),
         .chanx_left_in(sb_1__1__23_chanx_right_out),
@@ -7109,9 +7108,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__29_chany_top_out),
         .chany_top_in_0(cby_1__1__35_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -7120,6 +7119,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -7159,7 +7159,6 @@ module fpga_top
     );
     tile tile_6__5_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__30_ccff_tail),
         .ccff_head_2(grid_clb_28_ccff_tail),
         .chanx_left_in(sb_1__1__24_chanx_right_out),
@@ -7167,9 +7166,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__30_chany_top_out),
         .chany_top_in_0(cby_1__1__36_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -7178,6 +7177,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -7217,7 +7217,6 @@ module fpga_top
     );
     tile tile_6__6_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__31_ccff_tail),
         .ccff_head_2(grid_clb_45_ccff_tail),
         .chanx_left_in(sb_1__1__25_chanx_right_out),
@@ -7225,9 +7224,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__31_chany_top_out),
         .chany_top_in_0(cby_1__1__37_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -7236,6 +7235,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -7275,7 +7275,6 @@ module fpga_top
     );
     tile tile_6__7_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__32_ccff_tail),
         .ccff_head_2(grid_clb_30_ccff_tail),
         .chanx_left_in(sb_1__1__26_chanx_right_out),
@@ -7283,9 +7282,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__32_chany_top_out),
         .chany_top_in_0(cby_1__1__38_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -7294,6 +7293,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -7333,7 +7333,6 @@ module fpga_top
     );
     tile tile_6__8_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__33_ccff_tail),
         .ccff_head_2(grid_clb_47_ccff_tail),
         .chanx_left_in(sb_1__1__27_chanx_right_out),
@@ -7341,9 +7340,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__33_chany_top_out),
         .chany_top_in_0(cby_1__1__39_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -7352,6 +7351,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -7391,18 +7391,17 @@ module fpga_top
     );
     top_tile tile_6__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__34_ccff_tail),
         .ccff_head_2(grid_io_top_top_5_ccff_tail),
         .chanx_left_in(sb_1__8__3_chanx_right_out),
         .chanx_right_in_0(cbx_1__8__5_chanx_left_out),
         .chany_bottom_in(sb_1__1__34_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16:19]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[16:19]),
+        .isol_n(isol_n),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -7415,6 +7414,7 @@ module fpga_top
         .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
         .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_5__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_),
         .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_5__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_),
         .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_24_bottom_width_0_height_0_subtile_0__pin_sc_out_0_),
@@ -7430,8 +7430,8 @@ module fpga_top
         .chanx_left_out(cbx_1__8__4_chanx_left_out),
         .chanx_right_out_0(sb_1__8__4_chanx_right_out),
         .chany_bottom_out(cby_1__1__39_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16:19]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16:19]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[16:19]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[16:19]),
         .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_10_),
         .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_11_),
         .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -7451,15 +7451,15 @@ module fpga_top
     );
     bottom_tile tile_7__1_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(grid_io_bottom_bottom_3_ccff_tail),
         .ccff_head_1(grid_clb_32_ccff_tail),
         .chanx_left_in(sb_1__0__4_chanx_right_out),
         .chanx_right_in_0(cbx_1__0__6_chanx_left_out),
         .chany_top_in(cby_1__1__40_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72:75]),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[72:75]),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -7477,8 +7477,8 @@ module fpga_top
         .chanx_left_out(cbx_1__0__5_chanx_left_out),
         .chanx_right_out_0(sb_1__0__5_chanx_right_out),
         .chany_top_out(sb_1__0__5_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[72:75]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72:75]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[72:75]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[72:75]),
         .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_),
         .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_),
         .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -7486,7 +7486,6 @@ module fpga_top
     );
     tile tile_7__2_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__0__5_ccff_tail),
         .ccff_head_2(grid_clb_49_ccff_tail),
         .chanx_left_in(sb_1__1__28_chanx_right_out),
@@ -7494,9 +7493,9 @@ module fpga_top
         .chany_bottom_in(sb_1__0__5_chany_top_out),
         .chany_top_in_0(cby_1__1__41_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -7505,6 +7504,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -7544,7 +7544,6 @@ module fpga_top
     );
     tile tile_7__3_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__35_ccff_tail),
         .ccff_head_2(grid_clb_34_ccff_tail),
         .chanx_left_in(sb_1__1__29_chanx_right_out),
@@ -7552,9 +7551,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__35_chany_top_out),
         .chany_top_in_0(cby_1__1__42_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -7563,6 +7562,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -7602,7 +7602,6 @@ module fpga_top
     );
     tile tile_7__4_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__36_ccff_tail),
         .ccff_head_2(grid_clb_51_ccff_tail),
         .chanx_left_in(sb_1__1__30_chanx_right_out),
@@ -7610,9 +7609,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__36_chany_top_out),
         .chany_top_in_0(cby_1__1__43_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -7621,6 +7620,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -7660,7 +7660,6 @@ module fpga_top
     );
     tile tile_7__5_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__37_ccff_tail),
         .ccff_head_2(grid_clb_36_ccff_tail),
         .chanx_left_in(sb_1__1__31_chanx_right_out),
@@ -7668,9 +7667,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__37_chany_top_out),
         .chany_top_in_0(cby_1__1__44_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -7679,6 +7678,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -7718,7 +7718,6 @@ module fpga_top
     );
     tile tile_7__6_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__38_ccff_tail),
         .ccff_head_2(grid_clb_53_ccff_tail),
         .chanx_left_in(sb_1__1__32_chanx_right_out),
@@ -7726,9 +7725,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__38_chany_top_out),
         .chany_top_in_0(cby_1__1__45_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -7737,6 +7736,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -7776,7 +7776,6 @@ module fpga_top
     );
     tile tile_7__7_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__39_ccff_tail),
         .ccff_head_2(grid_clb_38_ccff_tail),
         .chanx_left_in(sb_1__1__33_chanx_right_out),
@@ -7784,9 +7783,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__39_chany_top_out),
         .chany_top_in_0(cby_1__1__46_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -7795,6 +7794,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -7834,7 +7834,6 @@ module fpga_top
     );
     tile tile_7__8_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__40_ccff_tail),
         .ccff_head_2(grid_clb_55_ccff_tail),
         .chanx_left_in(sb_1__1__34_chanx_right_out),
@@ -7842,9 +7841,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__40_chany_top_out),
         .chany_top_in_0(cby_1__1__47_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -7853,6 +7852,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -7892,18 +7892,17 @@ module fpga_top
     );
     top_tile tile_7__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__41_ccff_tail),
         .ccff_head_2(grid_io_top_top_6_ccff_tail),
         .chanx_left_in(sb_1__8__4_chanx_right_out),
         .chanx_right_in_0(cbx_1__8__6_chanx_left_out),
         .chany_bottom_in(sb_1__1__41_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20:23]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[20:23]),
+        .isol_n(isol_n),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -7916,6 +7915,7 @@ module fpga_top
         .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
         .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_6__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_),
         .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_6__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_),
         .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_32_bottom_width_0_height_0_subtile_0__pin_sc_out_0_),
@@ -7931,8 +7931,8 @@ module fpga_top
         .chanx_left_out(cbx_1__8__5_chanx_left_out),
         .chanx_right_out_0(sb_1__8__5_chanx_right_out),
         .chany_bottom_out(cby_1__1__47_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20:23]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20:23]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[20:23]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[20:23]),
         .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_10_),
         .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_11_),
         .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -7952,15 +7952,15 @@ module fpga_top
     );
     bottom_tile tile_8__1_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(grid_io_bottom_bottom_2_ccff_tail),
         .ccff_head_1(grid_clb_40_ccff_tail),
         .chanx_left_in(sb_1__0__5_chanx_right_out),
         .chanx_right_in_0(cbx_1__0__7_chanx_left_out),
         .chany_top_in(cby_1__1__48_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68:71]),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[68:71]),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -7978,8 +7978,8 @@ module fpga_top
         .chanx_left_out(cbx_1__0__6_chanx_left_out),
         .chanx_right_out_0(sb_1__0__6_chanx_right_out),
         .chany_top_out(sb_1__0__6_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[68:71]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68:71]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[68:71]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[68:71]),
         .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_),
         .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_),
         .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -7987,7 +7987,6 @@ module fpga_top
     );
     tile tile_8__2_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__0__6_ccff_tail),
         .ccff_head_2(grid_clb_57_ccff_tail),
         .chanx_left_in(sb_1__1__35_chanx_right_out),
@@ -7995,9 +7994,9 @@ module fpga_top
         .chany_bottom_in(sb_1__0__6_chany_top_out),
         .chany_top_in_0(cby_1__1__49_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -8006,6 +8005,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -8045,7 +8045,6 @@ module fpga_top
     );
     tile tile_8__3_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__42_ccff_tail),
         .ccff_head_2(grid_clb_42_ccff_tail),
         .chanx_left_in(sb_1__1__36_chanx_right_out),
@@ -8053,9 +8052,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__42_chany_top_out),
         .chany_top_in_0(cby_1__1__50_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -8064,6 +8063,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -8103,7 +8103,6 @@ module fpga_top
     );
     tile tile_8__4_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__43_ccff_tail),
         .ccff_head_2(grid_clb_59_ccff_tail),
         .chanx_left_in(sb_1__1__37_chanx_right_out),
@@ -8111,9 +8110,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__43_chany_top_out),
         .chany_top_in_0(cby_1__1__51_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -8122,6 +8121,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -8161,7 +8161,6 @@ module fpga_top
     );
     tile tile_8__5_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__44_ccff_tail),
         .ccff_head_2(grid_clb_44_ccff_tail),
         .chanx_left_in(sb_1__1__38_chanx_right_out),
@@ -8169,9 +8168,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__44_chany_top_out),
         .chany_top_in_0(cby_1__1__52_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -8180,6 +8179,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -8219,7 +8219,6 @@ module fpga_top
     );
     tile tile_8__6_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__45_ccff_tail),
         .ccff_head_2(grid_clb_61_ccff_tail),
         .chanx_left_in(sb_1__1__39_chanx_right_out),
@@ -8227,9 +8226,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__45_chany_top_out),
         .chany_top_in_0(cby_1__1__53_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -8238,6 +8237,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -8277,7 +8277,6 @@ module fpga_top
     );
     tile tile_8__7_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__46_ccff_tail),
         .ccff_head_2(grid_clb_46_ccff_tail),
         .chanx_left_in(sb_1__1__40_chanx_right_out),
@@ -8285,9 +8284,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__46_chany_top_out),
         .chany_top_in_0(cby_1__1__54_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -8296,6 +8295,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -8335,7 +8335,6 @@ module fpga_top
     );
     tile tile_8__8_
     (
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__47_ccff_tail),
         .ccff_head_2(grid_clb_63_ccff_tail),
         .chanx_left_in(sb_1__1__41_chanx_right_out),
@@ -8343,9 +8342,9 @@ module fpga_top
         .chany_bottom_in(sb_1__1__47_chany_top_out),
         .chany_top_in_0(cby_1__1__55_chany_bottom_out),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -8354,6 +8353,7 @@ module fpga_top
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_5_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_6_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_7_),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -8393,18 +8393,17 @@ module fpga_top
     );
     top_tile tile_8__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .Test_en(Test_en),
         .ccff_head_1(cbx_1__1__48_ccff_tail),
         .ccff_head_2(grid_io_top_top_7_ccff_tail),
         .chanx_left_in(sb_1__8__5_chanx_right_out),
         .chanx_right_in_0(cbx_1__8__7_chanx_left_out),
         .chany_bottom_in(sb_1__1__48_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24:27]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[24:27]),
+        .isol_n(isol_n),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_2_),
@@ -8417,6 +8416,7 @@ module fpga_top
         .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
         .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_7__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_),
         .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_7__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_),
         .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_40_bottom_width_0_height_0_subtile_0__pin_sc_out_0_),
@@ -8432,8 +8432,8 @@ module fpga_top
         .chanx_left_out(cbx_1__8__6_chanx_left_out),
         .chanx_right_out_0(sb_1__8__6_chanx_right_out),
         .chany_bottom_out(cby_1__1__55_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24:27]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24:27]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[24:27]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[24:27]),
         .right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_10_),
         .right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_11_),
         .right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -8453,14 +8453,14 @@ module fpga_top
     );
     bottom_right_tile tile_9__1_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(grid_io_bottom_bottom_1_ccff_tail),
         .ccff_head_1(grid_clb_48_ccff_tail),
         .chanx_left_in(sb_1__0__6_chanx_right_out),
         .chany_top_in(cby_8__1__0_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64:67]),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[64:67]),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -8477,8 +8477,8 @@ module fpga_top
         .ccff_tail_0(cbx_1__0__7_ccff_tail),
         .chanx_left_out(cbx_1__0__7_chanx_left_out),
         .chany_top_out(sb_8__0__0_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[64:67]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64:67]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[64:67]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[64:67]),
         .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
         .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
         .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -8486,19 +8486,19 @@ module fpga_top
     );
     right_tile tile_9__2_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .Test_en(Test_en),
         .ccff_head_0_0(cbx_1__0__7_ccff_tail),
         .ccff_head_1(grid_io_bottom_bottom_0_ccff_tail),
         .ccff_head_2(grid_clb_56_ccff_tail),
         .chanx_left_in(sb_1__1__42_chanx_right_out),
         .chany_bottom_in(sb_8__0__0_chany_top_out),
         .chany_top_in_0(cby_8__1__1_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60:63]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[60:63]),
+        .isol_n(isol_n),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -8523,8 +8523,8 @@ module fpga_top
         .chanx_left_out(cbx_1__1__49_chanx_left_out),
         .chany_bottom_out(cby_8__1__0_chany_bottom_out),
         .chany_top_out_0(sb_8__1__0_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60:63]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60:63]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[60:63]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[60:63]),
         .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_0__pin_inpad_0_),
         .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_1__pin_inpad_0_),
         .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_7_left_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -8548,19 +8548,19 @@ module fpga_top
     );
     right_tile tile_9__3_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .Test_en(Test_en),
         .ccff_head_0_0(cbx_1__1__49_ccff_tail),
         .ccff_head_1(grid_io_right_right_7_ccff_tail),
         .ccff_head_2(grid_clb_50_ccff_tail),
         .chanx_left_in(sb_1__1__43_chanx_right_out),
         .chany_bottom_in(sb_8__1__0_chany_top_out),
         .chany_top_in_0(cby_8__1__2_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56:59]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[56:59]),
+        .isol_n(isol_n),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -8585,8 +8585,8 @@ module fpga_top
         .chanx_left_out(cbx_1__1__50_chanx_left_out),
         .chany_bottom_out(cby_8__1__1_chany_bottom_out),
         .chany_top_out_0(sb_8__1__1_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[56:59]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56:59]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[56:59]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[56:59]),
         .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_0__pin_inpad_0_),
         .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_1__pin_inpad_0_),
         .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_6_left_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -8610,19 +8610,19 @@ module fpga_top
     );
     right_tile tile_9__4_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .Test_en(Test_en),
         .ccff_head_0_0(cbx_1__1__50_ccff_tail),
         .ccff_head_1(grid_io_right_right_6_ccff_tail),
         .ccff_head_2(grid_clb_58_ccff_tail),
         .chanx_left_in(sb_1__1__44_chanx_right_out),
         .chany_bottom_in(sb_8__1__1_chany_top_out),
         .chany_top_in_0(cby_8__1__3_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52:55]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[52:55]),
+        .isol_n(isol_n),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -8647,8 +8647,8 @@ module fpga_top
         .chanx_left_out(cbx_1__1__51_chanx_left_out),
         .chany_bottom_out(cby_8__1__2_chany_bottom_out),
         .chany_top_out_0(sb_8__1__2_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[52:55]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52:55]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[52:55]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[52:55]),
         .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_0__pin_inpad_0_),
         .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_1__pin_inpad_0_),
         .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_5_left_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -8672,19 +8672,19 @@ module fpga_top
     );
     right_tile tile_9__5_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .Test_en(Test_en),
         .ccff_head_0_0(cbx_1__1__51_ccff_tail),
         .ccff_head_1(grid_io_right_right_5_ccff_tail),
         .ccff_head_2(grid_clb_52_ccff_tail),
         .chanx_left_in(sb_1__1__45_chanx_right_out),
         .chany_bottom_in(sb_8__1__2_chany_top_out),
         .chany_top_in_0(cby_8__1__4_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48:51]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[48:51]),
+        .isol_n(isol_n),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -8709,8 +8709,8 @@ module fpga_top
         .chanx_left_out(cbx_1__1__52_chanx_left_out),
         .chany_bottom_out(cby_8__1__3_chany_bottom_out),
         .chany_top_out_0(sb_8__1__3_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[48:51]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48:51]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[48:51]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[48:51]),
         .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_0__pin_inpad_0_),
         .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_1__pin_inpad_0_),
         .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_4_left_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -8734,19 +8734,19 @@ module fpga_top
     );
     right_tile tile_9__6_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .Test_en(Test_en),
         .ccff_head_0_0(cbx_1__1__52_ccff_tail),
         .ccff_head_1(grid_io_right_right_4_ccff_tail),
         .ccff_head_2(grid_clb_60_ccff_tail),
         .chanx_left_in(sb_1__1__46_chanx_right_out),
         .chany_bottom_in(sb_8__1__3_chany_top_out),
         .chany_top_in_0(cby_8__1__5_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44:47]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[44:47]),
+        .isol_n(isol_n),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -8771,8 +8771,8 @@ module fpga_top
         .chanx_left_out(cbx_1__1__53_chanx_left_out),
         .chany_bottom_out(cby_8__1__4_chany_bottom_out),
         .chany_top_out_0(sb_8__1__4_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[44:47]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44:47]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[44:47]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[44:47]),
         .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_0__pin_inpad_0_),
         .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_1__pin_inpad_0_),
         .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_3_left_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -8796,19 +8796,19 @@ module fpga_top
     );
     right_tile tile_9__7_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .Test_en(Test_en),
         .ccff_head_0_0(cbx_1__1__53_ccff_tail),
         .ccff_head_1(grid_io_right_right_3_ccff_tail),
         .ccff_head_2(grid_clb_54_ccff_tail),
         .chanx_left_in(sb_1__1__47_chanx_right_out),
         .chany_bottom_in(sb_8__1__4_chany_top_out),
         .chany_top_in_0(cby_8__1__6_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40:43]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[40:43]),
+        .isol_n(isol_n),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -8833,8 +8833,8 @@ module fpga_top
         .chanx_left_out(cbx_1__1__54_chanx_left_out),
         .chany_bottom_out(cby_8__1__5_chany_bottom_out),
         .chany_top_out_0(sb_8__1__5_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[40:43]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40:43]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[40:43]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[40:43]),
         .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_0__pin_inpad_0_),
         .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_1__pin_inpad_0_),
         .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_2_left_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -8858,19 +8858,19 @@ module fpga_top
     );
     right_tile tile_9__8_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .Test_en(Test_en),
         .ccff_head_0_0(cbx_1__1__54_ccff_tail),
         .ccff_head_1(grid_io_right_right_2_ccff_tail),
         .ccff_head_2(grid_clb_62_ccff_tail),
         .chanx_left_in(sb_1__1__48_chanx_right_out),
         .chany_bottom_in(sb_8__1__5_chany_top_out),
         .chany_top_in_0(cby_8__1__7_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36:39]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[36:39]),
+        .isol_n(isol_n),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
+        .scan_enable(scan_enable),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_12_),
@@ -8895,8 +8895,8 @@ module fpga_top
         .chanx_left_out(cbx_1__1__55_chanx_left_out),
         .chany_bottom_out(cby_8__1__6_chany_bottom_out),
         .chany_top_out_0(sb_8__1__6_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[36:39]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36:39]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[36:39]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[36:39]),
         .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_0__pin_inpad_0_),
         .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_1__pin_inpad_0_),
         .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_1_left_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -8920,18 +8920,18 @@ module fpga_top
     );
     top_right_tile tile_9__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .Test_en(Test_en),
         .ccff_head_0_0(cbx_1__1__55_ccff_tail),
         .ccff_head_1(grid_io_right_right_1_ccff_tail),
         .chanx_left_in(sb_1__8__6_chanx_right_out),
         .chany_bottom_in(sb_8__1__6_chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28:31]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN_0(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32:35]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[28:31]),
+        .gfpga_pad_io_soc_in_0(gfpga_pad_io_soc_in[32:35]),
+        .isol_n(isol_n),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
-        .pReset(pReset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_cin_0_(grid_clb_8__8__undriven_top_width_0_height_0_subtile_0__pin_cin_0_),
         .top_width_0_height_0_subtile_0__pin_reg_in_0_(grid_clb_8__8__undriven_top_width_0_height_0_subtile_0__pin_reg_in_0_),
         .top_width_0_height_0_subtile_0__pin_sc_in_0_(grid_clb_48_bottom_width_0_height_0_subtile_0__pin_sc_out_0_),
@@ -8946,10 +8946,10 @@ module fpga_top
         .ccff_tail_0(grid_io_top_top_7_ccff_tail),
         .chanx_left_out(cbx_1__8__7_chanx_left_out),
         .chany_bottom_out(cby_8__1__7_chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[28:31]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR_0(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[32:35]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28:31]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_0(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32:35]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[28:31]),
+        .gfpga_pad_io_soc_dir_0(gfpga_pad_io_soc_dir[32:35]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[28:31]),
+        .gfpga_pad_io_soc_out_0(gfpga_pad_io_soc_out[32:35]),
         .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_),
         .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_),
         .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/EMBEDDED_IO_HD.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/EMBEDDED_IO_HD.v
deleted file mode 100644
index 4f903f1..0000000
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/EMBEDDED_IO_HD.v
+++ /dev/null
@@ -1,31 +0,0 @@
-//Generated from netlist by SpyDrNet
-//netlist name: FPGA88_SOFA_A
-module EMBEDDED_IO_HD
-(
-    FPGA_DIR,
-    FPGA_OUT,
-    IO_ISOL_N,
-    SOC_IN,
-    FPGA_IN,
-    SOC_DIR,
-    SOC_OUT
-);
-
-    input FPGA_DIR;
-    input FPGA_OUT;
-    input IO_ISOL_N;
-    input SOC_IN;
-    output FPGA_IN;
-    output SOC_DIR;
-    output SOC_OUT;
-
-    wire FPGA_DIR;
-    wire FPGA_IN;
-    wire FPGA_OUT;
-    wire IO_ISOL_N;
-    wire SOC_DIR;
-    wire SOC_IN;
-    wire SOC_OUT;
-
-endmodule
-
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__0_.v
index b5ea2fc..f8f6deb 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__0_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__0_.v
@@ -2,46 +2,45 @@
 //netlist name: FPGA88_SOFA_A
 module cbx_1__0_
 (
-    IO_ISOL_N,
     ccff_head,
     ccff_head_0,
     chanx_left_in,
     chanx_right_in,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    pReset,
+    gfpga_pad_io_soc_in,
+    isol_n,
     prog_clk,
+    prog_reset,
     ccff_tail,
     ccff_tail_0,
     chanx_left_out,
     chanx_right_out,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    gfpga_pad_io_soc_dir,
+    gfpga_pad_io_soc_out,
     top_width_0_height_0_subtile_0__pin_inpad_0_,
     top_width_0_height_0_subtile_1__pin_inpad_0_,
     top_width_0_height_0_subtile_2__pin_inpad_0_,
     top_width_0_height_0_subtile_3__pin_inpad_0_
 );
 
-    input IO_ISOL_N;
     input ccff_head;
     input ccff_head_0;
     input [29:0]chanx_left_in;
     input [29:0]chanx_right_in;
-    input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    input pReset;
+    input [3:0]gfpga_pad_io_soc_in;
+    input isol_n;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output ccff_tail_0;
     output [29:0]chanx_left_out;
     output [29:0]chanx_right_out;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output [3:0]gfpga_pad_io_soc_dir;
+    output [3:0]gfpga_pad_io_soc_out;
     output top_width_0_height_0_subtile_0__pin_inpad_0_;
     output top_width_0_height_0_subtile_1__pin_inpad_0_;
     output top_width_0_height_0_subtile_2__pin_inpad_0_;
     output top_width_0_height_0_subtile_3__pin_inpad_0_;
 
-    wire IO_ISOL_N;
     wire bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;
     wire bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_;
     wire bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -54,11 +53,12 @@ module cbx_1__0_
     wire [29:0]chanx_left_out;
     wire [29:0]chanx_right_in;
     wire [29:0]chanx_right_out;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    wire pReset;
+    wire [3:0]gfpga_pad_io_soc_dir;
+    wire [3:0]gfpga_pad_io_soc_in;
+    wire [3:0]gfpga_pad_io_soc_out;
+    wire isol_n;
     wire prog_clk;
+    wire prog_reset;
     wire top_width_0_height_0_subtile_0__pin_inpad_0_;
     wire top_width_0_height_0_subtile_1__pin_inpad_0_;
     wire top_width_0_height_0_subtile_2__pin_inpad_0_;
@@ -69,8 +69,8 @@ module cbx_1__0_
         .ccff_head(ccff_head_0),
         .chanx_left_in(chanx_left_in),
         .chanx_right_in(chanx_right_in),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
         .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
         .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -81,18 +81,18 @@ module cbx_1__0_
     );
     grid_io_bottom_bottom grid_io_bottom_bottom_8__0_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(ccff_head),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .top_width_0_height_0_subtile_0__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
         .top_width_0_height_0_subtile_1__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
         .top_width_0_height_0_subtile_2__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
         .top_width_0_height_0_subtile_3__pin_outpad_0_(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_),
         .ccff_tail(ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
         .top_width_0_height_0_subtile_0__pin_inpad_0_(top_width_0_height_0_subtile_0__pin_inpad_0_),
         .top_width_0_height_0_subtile_1__pin_inpad_0_(top_width_0_height_0_subtile_1__pin_inpad_0_),
         .top_width_0_height_0_subtile_2__pin_inpad_0_(top_width_0_height_0_subtile_2__pin_inpad_0_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__0__old.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__0__old.v
index 2d4c7cf..ad2b60f 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__0__old.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__0__old.v
@@ -5,8 +5,8 @@ module cbx_1__0__old
     ccff_head,
     chanx_left_in,
     chanx_right_in,
-    pReset,
     prog_clk,
+    prog_reset,
     bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_,
     bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_,
     bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_,
@@ -19,8 +19,8 @@ module cbx_1__0__old
     input ccff_head;
     input [0:29]chanx_left_in;
     input [0:29]chanx_right_in;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;
     output bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_;
     output bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -50,8 +50,8 @@ module cbx_1__0__old
     wire mux_tree_tapbuf_size12_mem_0_ccff_tail;
     wire mux_tree_tapbuf_size12_mem_1_ccff_tail;
     wire mux_tree_tapbuf_size12_mem_2_ccff_tail;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
 assign chanx_right_out[0] = chanx_left_in[0];
 assign chanx_right_out[1] = chanx_left_in[1];
@@ -116,32 +116,32 @@ assign chanx_right_out[9] = chanx_left_in[9];
     mux_tree_tapbuf_size12_mem mem_top_ipin_0
     (
         .ccff_head(ccff_head),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_0_sram)
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_1
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_1_sram)
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_2
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_2_sram)
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_3
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_3_sram)
     );
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__1_.v
index 6ad0f0a..c39436b 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__1_.v
@@ -5,8 +5,8 @@ module cbx_1__1_
     ccff_head,
     chanx_left_in,
     chanx_right_in,
-    pReset,
     prog_clk,
+    prog_reset,
     bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_,
     bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_,
     bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_,
@@ -31,8 +31,8 @@ module cbx_1__1_
     input ccff_head;
     input [0:29]chanx_left_in;
     input [0:29]chanx_right_in;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
     output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
     output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
@@ -122,8 +122,8 @@ module cbx_1__1_
     wire mux_tree_tapbuf_size12_mem_5_ccff_tail;
     wire mux_tree_tapbuf_size12_mem_6_ccff_tail;
     wire mux_tree_tapbuf_size12_mem_7_ccff_tail;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
 assign chanx_right_out[0] = chanx_left_in[0];
 assign chanx_right_out[1] = chanx_left_in[1];
@@ -188,128 +188,128 @@ assign chanx_right_out[9] = chanx_left_in[9];
     mux_tree_tapbuf_size12_mem mem_top_ipin_0
     (
         .ccff_head(ccff_head),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_0_sram)
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_1
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_0_sram)
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_10
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_5_sram)
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_11
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_5_sram)
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_12
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_6_sram)
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_13
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_6_sram)
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_14
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_7_sram)
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_15
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_7_sram)
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_2
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_1_sram)
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_3
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_1_sram)
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_4
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_2_sram)
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_5
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_2_sram)
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_6
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_3_sram)
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_7
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_3_sram)
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_8
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_4_sram)
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_9
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_4_sram)
     );
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__8_.v
index 5dc8033..a41e0c6 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__8_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__8_.v
@@ -2,13 +2,13 @@
 //netlist name: FPGA88_SOFA_A
 module cbx_1__8_
 (
-    IO_ISOL_N,
     ccff_head_0,
     chanx_left_in,
     chanx_right_in,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    pReset,
+    gfpga_pad_io_soc_in,
+    isol_n,
     prog_clk,
+    prog_reset,
     bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_,
     bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_,
     bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_,
@@ -32,17 +32,17 @@ module cbx_1__8_
     ccff_tail,
     chanx_left_out,
     chanx_right_out,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT
+    gfpga_pad_io_soc_dir,
+    gfpga_pad_io_soc_out
 );
 
-    input IO_ISOL_N;
     input ccff_head_0;
     input [29:0]chanx_left_in;
     input [29:0]chanx_right_in;
-    input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    input pReset;
+    input [3:0]gfpga_pad_io_soc_in;
+    input isol_n;
     input prog_clk;
+    input prog_reset;
     output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
     output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
     output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
@@ -66,10 +66,9 @@ module cbx_1__8_
     output ccff_tail;
     output [29:0]chanx_left_out;
     output [29:0]chanx_right_out;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output [3:0]gfpga_pad_io_soc_dir;
+    output [3:0]gfpga_pad_io_soc_out;
 
-    wire IO_ISOL_N;
     wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
     wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
     wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
@@ -97,11 +96,12 @@ module cbx_1__8_
     wire [29:0]chanx_left_out;
     wire [29:0]chanx_right_in;
     wire [29:0]chanx_right_out;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    wire pReset;
+    wire [3:0]gfpga_pad_io_soc_dir;
+    wire [3:0]gfpga_pad_io_soc_in;
+    wire [3:0]gfpga_pad_io_soc_out;
+    wire isol_n;
     wire prog_clk;
+    wire prog_reset;
     wire top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_;
     wire top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_;
     wire top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -112,8 +112,8 @@ module cbx_1__8_
         .ccff_head(ccff_head_0),
         .chanx_left_in(chanx_left_in),
         .chanx_right_in(chanx_right_in),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -140,22 +140,22 @@ module cbx_1__8_
     );
     grid_io_top_top grid_io_top_top_1__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .bottom_width_0_height_0_subtile_0__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_1__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_2__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_3__pin_outpad_0_(top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_),
         .ccff_head(ccff_tail_0),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .bottom_width_0_height_0_subtile_0__pin_inpad_0_(bottom_width_0_height_0_subtile_0__pin_inpad_0_),
         .bottom_width_0_height_0_subtile_1__pin_inpad_0_(bottom_width_0_height_0_subtile_1__pin_inpad_0_),
         .bottom_width_0_height_0_subtile_2__pin_inpad_0_(bottom_width_0_height_0_subtile_2__pin_inpad_0_),
         .bottom_width_0_height_0_subtile_3__pin_inpad_0_(bottom_width_0_height_0_subtile_3__pin_inpad_0_),
         .ccff_tail(ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT)
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out)
     );
 endmodule
 
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__8__old.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__8__old.v
index b31d489..ee604ce 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__8__old.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cbx_1__8__old.v
@@ -5,8 +5,8 @@ module cbx_1__8__old
     ccff_head,
     chanx_left_in,
     chanx_right_in,
-    pReset,
     prog_clk,
+    prog_reset,
     bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_,
     bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_,
     bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_,
@@ -35,8 +35,8 @@ module cbx_1__8__old
     input ccff_head;
     input [0:29]chanx_left_in;
     input [0:29]chanx_right_in;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
     output bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
     output bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
@@ -142,8 +142,8 @@ module cbx_1__8__old
     wire mux_tree_tapbuf_size12_mem_7_ccff_tail;
     wire mux_tree_tapbuf_size12_mem_8_ccff_tail;
     wire mux_tree_tapbuf_size12_mem_9_ccff_tail;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
     wire top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_;
     wire top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_;
     wire top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -212,160 +212,160 @@ assign chanx_right_out[9] = chanx_left_in[9];
     mux_tree_tapbuf_size12_mem mem_bottom_ipin_0
     (
         .ccff_head(ccff_head),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_0_sram)
     );
     mux_tree_tapbuf_size12_mem mem_bottom_ipin_1
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_1_sram)
     );
     mux_tree_tapbuf_size12_mem mem_bottom_ipin_2
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_2_sram)
     );
     mux_tree_tapbuf_size12_mem mem_bottom_ipin_3
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_3_sram)
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_0
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_4_sram)
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_1
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_0_sram)
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_10
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_9_sram)
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_11
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_5_sram)
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_12
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_10_sram)
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_13
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_6_sram)
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_14
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_11_sram)
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_15
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_7_sram)
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_2
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_5_sram)
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_3
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_1_sram)
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_4
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_6_sram)
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_5
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_2_sram)
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_6
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_7_sram)
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_7
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_3_sram)
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_8
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_8_sram)
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_9
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_4_sram)
     );
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_0__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_0__1_.v
index 69c1735..6a48986 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_0__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_0__1_.v
@@ -2,42 +2,41 @@
 //netlist name: FPGA88_SOFA_A
 module cby_0__1_
 (
-    IO_ISOL_N,
     ccff_head_0,
     chany_bottom_in,
     chany_top_in,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    pReset,
+    gfpga_pad_io_soc_in,
+    isol_n,
     prog_clk,
+    prog_reset,
     ccff_tail,
     chany_bottom_out,
     chany_top_out,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    gfpga_pad_io_soc_dir,
+    gfpga_pad_io_soc_out,
     right_width_0_height_0_subtile_0__pin_inpad_0_,
     right_width_0_height_0_subtile_1__pin_inpad_0_,
     right_width_0_height_0_subtile_2__pin_inpad_0_,
     right_width_0_height_0_subtile_3__pin_inpad_0_
 );
 
-    input IO_ISOL_N;
     input ccff_head_0;
     input [29:0]chany_bottom_in;
     input [29:0]chany_top_in;
-    input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    input pReset;
+    input [3:0]gfpga_pad_io_soc_in;
+    input isol_n;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output [29:0]chany_bottom_out;
     output [29:0]chany_top_out;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output [3:0]gfpga_pad_io_soc_dir;
+    output [3:0]gfpga_pad_io_soc_out;
     output right_width_0_height_0_subtile_0__pin_inpad_0_;
     output right_width_0_height_0_subtile_1__pin_inpad_0_;
     output right_width_0_height_0_subtile_2__pin_inpad_0_;
     output right_width_0_height_0_subtile_3__pin_inpad_0_;
 
-    wire IO_ISOL_N;
     wire ccff_head_0;
     wire ccff_tail;
     wire ccff_tail_0;
@@ -45,15 +44,16 @@ module cby_0__1_
     wire [29:0]chany_bottom_out;
     wire [29:0]chany_top_in;
     wire [29:0]chany_top_out;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    wire [3:0]gfpga_pad_io_soc_dir;
+    wire [3:0]gfpga_pad_io_soc_in;
+    wire [3:0]gfpga_pad_io_soc_out;
+    wire isol_n;
     wire left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_;
     wire left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_;
     wire left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_;
     wire left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
     wire right_width_0_height_0_subtile_0__pin_inpad_0_;
     wire right_width_0_height_0_subtile_1__pin_inpad_0_;
     wire right_width_0_height_0_subtile_2__pin_inpad_0_;
@@ -64,8 +64,8 @@ module cby_0__1_
         .ccff_head(ccff_head_0),
         .chany_bottom_in(chany_bottom_in),
         .chany_top_in(chany_top_in),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail_0),
         .chany_bottom_out(chany_bottom_out),
         .chany_top_out(chany_top_out),
@@ -76,18 +76,18 @@ module cby_0__1_
     );
     grid_io_left_left grid_io_left_left_0__1_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(ccff_tail_0),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_width_0_height_0_subtile_0__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
         .right_width_0_height_0_subtile_1__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
         .right_width_0_height_0_subtile_2__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
         .right_width_0_height_0_subtile_3__pin_outpad_0_(left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_),
         .ccff_tail(ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
         .right_width_0_height_0_subtile_0__pin_inpad_0_(right_width_0_height_0_subtile_0__pin_inpad_0_),
         .right_width_0_height_0_subtile_1__pin_inpad_0_(right_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_width_0_height_0_subtile_2__pin_inpad_0_(right_width_0_height_0_subtile_2__pin_inpad_0_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_0__1__old.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_0__1__old.v
index 798e545..7ea82b4 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_0__1__old.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_0__1__old.v
@@ -5,8 +5,8 @@ module cby_0__1__old
     ccff_head,
     chany_bottom_in,
     chany_top_in,
-    pReset,
     prog_clk,
+    prog_reset,
     ccff_tail,
     chany_bottom_out,
     chany_top_out,
@@ -19,8 +19,8 @@ module cby_0__1__old
     input ccff_head;
     input [0:29]chany_bottom_in;
     input [0:29]chany_top_in;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output [0:29]chany_bottom_out;
     output [0:29]chany_top_out;
@@ -50,8 +50,8 @@ module cby_0__1__old
     wire mux_tree_tapbuf_size12_mem_0_ccff_tail;
     wire mux_tree_tapbuf_size12_mem_1_ccff_tail;
     wire mux_tree_tapbuf_size12_mem_2_ccff_tail;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
 assign chany_top_out[0] = chany_bottom_in[0];
 assign chany_top_out[1] = chany_bottom_in[1];
@@ -116,32 +116,32 @@ assign chany_top_out[9] = chany_bottom_in[9];
     mux_tree_tapbuf_size12_mem mem_right_ipin_0
     (
         .ccff_head(ccff_head),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_0_sram)
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_1
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_1_sram)
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_2
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_2_sram)
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_3
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_3_sram)
     );
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_1__1_.v
index 8e4f9ae..2162b52 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_1__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_1__1_.v
@@ -5,8 +5,8 @@ module cby_1__1_
     ccff_head,
     chany_bottom_in,
     chany_top_in,
-    pReset,
     prog_clk,
+    prog_reset,
     ccff_tail,
     chany_bottom_out,
     chany_top_out,
@@ -31,8 +31,8 @@ module cby_1__1_
     input ccff_head;
     input [0:29]chany_bottom_in;
     input [0:29]chany_top_in;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output [0:29]chany_bottom_out;
     output [0:29]chany_top_out;
@@ -122,8 +122,8 @@ module cby_1__1_
     wire mux_tree_tapbuf_size12_mem_5_ccff_tail;
     wire mux_tree_tapbuf_size12_mem_6_ccff_tail;
     wire mux_tree_tapbuf_size12_mem_7_ccff_tail;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
 assign chany_top_out[0] = chany_bottom_in[0];
 assign chany_top_out[1] = chany_bottom_in[1];
@@ -188,128 +188,128 @@ assign chany_top_out[9] = chany_bottom_in[9];
     mux_tree_tapbuf_size12_mem mem_right_ipin_0
     (
         .ccff_head(ccff_head),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_0_sram)
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_1
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_0_sram)
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_10
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_5_sram)
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_11
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_5_sram)
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_12
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_6_sram)
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_13
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_6_sram)
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_14
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_7_sram)
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_15
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_7_sram)
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_2
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_1_sram)
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_3
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_1_sram)
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_4
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_2_sram)
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_5
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_2_sram)
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_6
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_3_sram)
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_7
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_3_sram)
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_8
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_4_sram)
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_9
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_4_sram)
     );
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_8__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_8__1_.v
index 37055fd..b799d0f 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_8__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_8__1_.v
@@ -2,20 +2,20 @@
 //netlist name: FPGA88_SOFA_A
 module cby_8__1_
 (
-    IO_ISOL_N,
     ccff_head,
     ccff_head_0,
     chany_bottom_in,
     chany_top_in,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    pReset,
+    gfpga_pad_io_soc_in,
+    isol_n,
     prog_clk,
+    prog_reset,
     ccff_tail,
     ccff_tail_0,
     chany_bottom_out,
     chany_top_out,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    gfpga_pad_io_soc_dir,
+    gfpga_pad_io_soc_out,
     left_grid_right_width_0_height_0_subtile_0__pin_I4_0_,
     left_grid_right_width_0_height_0_subtile_0__pin_I4_1_,
     left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_,
@@ -38,20 +38,20 @@ module cby_8__1_
     left_width_0_height_0_subtile_3__pin_inpad_0_
 );
 
-    input IO_ISOL_N;
     input ccff_head;
     input ccff_head_0;
     input [29:0]chany_bottom_in;
     input [29:0]chany_top_in;
-    input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    input pReset;
+    input [3:0]gfpga_pad_io_soc_in;
+    input isol_n;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output ccff_tail_0;
     output [29:0]chany_bottom_out;
     output [29:0]chany_top_out;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output [3:0]gfpga_pad_io_soc_dir;
+    output [3:0]gfpga_pad_io_soc_out;
     output left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
     output left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
     output left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
@@ -73,7 +73,6 @@ module cby_8__1_
     output left_width_0_height_0_subtile_2__pin_inpad_0_;
     output left_width_0_height_0_subtile_3__pin_inpad_0_;
 
-    wire IO_ISOL_N;
     wire ccff_head;
     wire ccff_head_0;
     wire ccff_tail;
@@ -82,9 +81,10 @@ module cby_8__1_
     wire [29:0]chany_bottom_out;
     wire [29:0]chany_top_in;
     wire [29:0]chany_top_out;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    wire [3:0]gfpga_pad_io_soc_dir;
+    wire [3:0]gfpga_pad_io_soc_in;
+    wire [3:0]gfpga_pad_io_soc_out;
+    wire isol_n;
     wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
     wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
     wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
@@ -105,8 +105,8 @@ module cby_8__1_
     wire left_width_0_height_0_subtile_1__pin_inpad_0_;
     wire left_width_0_height_0_subtile_2__pin_inpad_0_;
     wire left_width_0_height_0_subtile_3__pin_inpad_0_;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
     wire right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_;
     wire right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_;
     wire right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -117,8 +117,8 @@ module cby_8__1_
         .ccff_head(ccff_head_0),
         .chany_bottom_in(chany_bottom_in),
         .chany_top_in(chany_top_in),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail_0),
         .chany_bottom_out(chany_bottom_out),
         .chany_top_out(chany_top_out),
@@ -145,18 +145,18 @@ module cby_8__1_
     );
     grid_io_right_right grid_io_right_right_9__8_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(ccff_head),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
+        .isol_n(isol_n),
         .left_width_0_height_0_subtile_0__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
         .left_width_0_height_0_subtile_1__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
         .left_width_0_height_0_subtile_2__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
         .left_width_0_height_0_subtile_3__pin_outpad_0_(right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
         .left_width_0_height_0_subtile_0__pin_inpad_0_(left_width_0_height_0_subtile_0__pin_inpad_0_),
         .left_width_0_height_0_subtile_1__pin_inpad_0_(left_width_0_height_0_subtile_1__pin_inpad_0_),
         .left_width_0_height_0_subtile_2__pin_inpad_0_(left_width_0_height_0_subtile_2__pin_inpad_0_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_8__1__old.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_8__1__old.v
index 0b60510..f19f035 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_8__1__old.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/cby_8__1__old.v
@@ -5,8 +5,8 @@ module cby_8__1__old
     ccff_head,
     chany_bottom_in,
     chany_top_in,
-    pReset,
     prog_clk,
+    prog_reset,
     ccff_tail,
     chany_bottom_out,
     chany_top_out,
@@ -35,8 +35,8 @@ module cby_8__1__old
     input ccff_head;
     input [0:29]chany_bottom_in;
     input [0:29]chany_top_in;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output [0:29]chany_bottom_out;
     output [0:29]chany_top_out;
@@ -142,8 +142,8 @@ module cby_8__1__old
     wire mux_tree_tapbuf_size12_mem_7_ccff_tail;
     wire mux_tree_tapbuf_size12_mem_8_ccff_tail;
     wire mux_tree_tapbuf_size12_mem_9_ccff_tail;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
     wire right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_;
     wire right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_;
     wire right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -212,160 +212,160 @@ assign chany_top_out[9] = chany_bottom_in[9];
     mux_tree_tapbuf_size12_mem mem_left_ipin_0
     (
         .ccff_head(ccff_head),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_0_sram)
     );
     mux_tree_tapbuf_size12_mem mem_left_ipin_1
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_1_sram)
     );
     mux_tree_tapbuf_size12_mem mem_left_ipin_2
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_2_sram)
     );
     mux_tree_tapbuf_size12_mem mem_left_ipin_3
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_3_sram)
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_0
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_4_sram)
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_1
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_0_sram)
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_10
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_9_sram)
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_11
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_5_sram)
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_12
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_10_sram)
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_13
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_6_sram)
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_14
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_11_sram)
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_15
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_7_sram)
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_2
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_5_sram)
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_3
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_1_sram)
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_4
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_6_sram)
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_5
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_2_sram)
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_6
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_7_sram)
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_7
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_3_sram)
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_8
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_8_sram)
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_9
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_4_sram)
     );
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.v
index f971dfb..15394ec 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem.v
@@ -3,142 +3,142 @@
 module frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem
 (
     ccff_head,
-    pReset,
     prog_clk,
+    prog_reset,
     ccff_tail,
     mem_out
 );
 
     input ccff_head;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output [0:16]mem_out;
 
     wire ccff_head;
     wire ccff_tail;
     wire [0:16]mem_out;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
 assign ccff_tail = mem_out[16];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
         .CLK(prog_clk),
         .D(ccff_head),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_
     (
         .CLK(prog_clk),
         .D(mem_out[9]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[10])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_
     (
         .CLK(prog_clk),
         .D(mem_out[10]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[11])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_
     (
         .CLK(prog_clk),
         .D(mem_out[11]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[12])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_
     (
         .CLK(prog_clk),
         .D(mem_out[12]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[13])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_
     (
         .CLK(prog_clk),
         .D(mem_out[13]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[14])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_
     (
         .CLK(prog_clk),
         .D(mem_out[14]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[15])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_
     (
         .CLK(prog_clk),
         .D(mem_out[15]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[16])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
         .CLK(prog_clk),
         .D(mem_out[0]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
         .CLK(prog_clk),
         .D(mem_out[1]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[2])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
     (
         .CLK(prog_clk),
         .D(mem_out[2]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[3])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_
     (
         .CLK(prog_clk),
         .D(mem_out[3]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[4])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_
     (
         .CLK(prog_clk),
         .D(mem_out[4]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[5])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_
     (
         .CLK(prog_clk),
         .D(mem_out[5]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[6])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_
     (
         .CLK(prog_clk),
         .D(mem_out[6]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[7])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_
     (
         .CLK(prog_clk),
         .D(mem_out[7]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[8])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_
     (
         .CLK(prog_clk),
         .D(mem_out[8]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[9])
     );
 endmodule
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_clb.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_clb.v
index 07ea2e7..f6c393b 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_clb.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_clb.v
@@ -2,12 +2,11 @@
 //netlist name: FPGA88_SOFA_A
 module grid_clb
 (
-    Test_en,
     ccff_head,
     left_width_0_height_0_subtile_0__pin_clk_0_,
     left_width_0_height_0_subtile_0__pin_reset_0_,
-    pReset,
     prog_clk,
+    prog_reset,
     right_width_0_height_0_subtile_0__pin_I4_0_,
     right_width_0_height_0_subtile_0__pin_I4_1_,
     right_width_0_height_0_subtile_0__pin_I4i_0_,
@@ -24,6 +23,7 @@ module grid_clb
     right_width_0_height_0_subtile_0__pin_I7_1_,
     right_width_0_height_0_subtile_0__pin_I7i_0_,
     right_width_0_height_0_subtile_0__pin_I7i_1_,
+    scan_enable,
     top_width_0_height_0_subtile_0__pin_I0_0_,
     top_width_0_height_0_subtile_0__pin_I0_1_,
     top_width_0_height_0_subtile_0__pin_I0i_0_,
@@ -65,12 +65,11 @@ module grid_clb
     top_width_0_height_0_subtile_0__pin_O_7_
 );
 
-    input Test_en;
     input ccff_head;
     input left_width_0_height_0_subtile_0__pin_clk_0_;
     input left_width_0_height_0_subtile_0__pin_reset_0_;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     input right_width_0_height_0_subtile_0__pin_I4_0_;
     input right_width_0_height_0_subtile_0__pin_I4_1_;
     input right_width_0_height_0_subtile_0__pin_I4i_0_;
@@ -87,6 +86,7 @@ module grid_clb
     input right_width_0_height_0_subtile_0__pin_I7_1_;
     input right_width_0_height_0_subtile_0__pin_I7i_0_;
     input right_width_0_height_0_subtile_0__pin_I7i_1_;
+    input scan_enable;
     input top_width_0_height_0_subtile_0__pin_I0_0_;
     input top_width_0_height_0_subtile_0__pin_I0_1_;
     input top_width_0_height_0_subtile_0__pin_I0i_0_;
@@ -127,7 +127,6 @@ module grid_clb
     output top_width_0_height_0_subtile_0__pin_O_6_;
     output top_width_0_height_0_subtile_0__pin_O_7_;
 
-    wire Test_en;
     wire bottom_width_0_height_0_subtile_0__pin_cout_0_;
     wire bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
     wire bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
@@ -135,8 +134,8 @@ module grid_clb
     wire ccff_tail;
     wire left_width_0_height_0_subtile_0__pin_clk_0_;
     wire left_width_0_height_0_subtile_0__pin_reset_0_;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
     wire right_width_0_height_0_subtile_0__pin_I4_0_;
     wire right_width_0_height_0_subtile_0__pin_I4_1_;
     wire right_width_0_height_0_subtile_0__pin_I4i_0_;
@@ -161,6 +160,7 @@ module grid_clb
     wire right_width_0_height_0_subtile_0__pin_O_15_;
     wire right_width_0_height_0_subtile_0__pin_O_8_;
     wire right_width_0_height_0_subtile_0__pin_O_9_;
+    wire scan_enable;
     wire top_width_0_height_0_subtile_0__pin_I0_0_;
     wire top_width_0_height_0_subtile_0__pin_I0_1_;
     wire top_width_0_height_0_subtile_0__pin_I0i_0_;
@@ -191,7 +191,6 @@ module grid_clb
 
     logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0
     (
-        .Test_en(Test_en),
         .ccff_head(ccff_head),
         .clb_I0({top_width_0_height_0_subtile_0__pin_I0_0_, top_width_0_height_0_subtile_0__pin_I0_1_}),
         .clb_I0i({top_width_0_height_0_subtile_0__pin_I0i_0_, top_width_0_height_0_subtile_0__pin_I0i_1_}),
@@ -214,8 +213,9 @@ module grid_clb
         .clb_reg_in(top_width_0_height_0_subtile_0__pin_reg_in_0_),
         .clb_reset(left_width_0_height_0_subtile_0__pin_reset_0_),
         .clb_sc_in(top_width_0_height_0_subtile_0__pin_sc_in_0_),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
+        .scan_enable(scan_enable),
         .ccff_tail(ccff_tail),
         .clb_O({top_width_0_height_0_subtile_0__pin_O_0_, top_width_0_height_0_subtile_0__pin_O_1_, top_width_0_height_0_subtile_0__pin_O_2_, top_width_0_height_0_subtile_0__pin_O_3_, top_width_0_height_0_subtile_0__pin_O_4_, top_width_0_height_0_subtile_0__pin_O_5_, top_width_0_height_0_subtile_0__pin_O_6_, top_width_0_height_0_subtile_0__pin_O_7_, right_width_0_height_0_subtile_0__pin_O_8_, right_width_0_height_0_subtile_0__pin_O_9_, right_width_0_height_0_subtile_0__pin_O_10_, right_width_0_height_0_subtile_0__pin_O_11_, right_width_0_height_0_subtile_0__pin_O_12_, right_width_0_height_0_subtile_0__pin_O_13_, right_width_0_height_0_subtile_0__pin_O_14_, right_width_0_height_0_subtile_0__pin_O_15_}),
         .clb_cout(bottom_width_0_height_0_subtile_0__pin_cout_0_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_bottom_bottom.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_bottom_bottom.v
index 896916d..a54d788 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_bottom_bottom.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_bottom_bottom.v
@@ -2,52 +2,52 @@
 //netlist name: FPGA88_SOFA_A
 module grid_io_bottom_bottom
 (
-    IO_ISOL_N,
     ccff_head,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    pReset,
+    gfpga_pad_io_soc_in,
+    isol_n,
     prog_clk,
+    prog_reset,
     top_width_0_height_0_subtile_0__pin_outpad_0_,
     top_width_0_height_0_subtile_1__pin_outpad_0_,
     top_width_0_height_0_subtile_2__pin_outpad_0_,
     top_width_0_height_0_subtile_3__pin_outpad_0_,
     ccff_tail,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    gfpga_pad_io_soc_dir,
+    gfpga_pad_io_soc_out,
     top_width_0_height_0_subtile_0__pin_inpad_0_,
     top_width_0_height_0_subtile_1__pin_inpad_0_,
     top_width_0_height_0_subtile_2__pin_inpad_0_,
     top_width_0_height_0_subtile_3__pin_inpad_0_
 );
 
-    input IO_ISOL_N;
     input ccff_head;
-    input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    input pReset;
+    input [0:3]gfpga_pad_io_soc_in;
+    input isol_n;
     input prog_clk;
+    input prog_reset;
     input top_width_0_height_0_subtile_0__pin_outpad_0_;
     input top_width_0_height_0_subtile_1__pin_outpad_0_;
     input top_width_0_height_0_subtile_2__pin_outpad_0_;
     input top_width_0_height_0_subtile_3__pin_outpad_0_;
     output ccff_tail;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output [0:3]gfpga_pad_io_soc_dir;
+    output [0:3]gfpga_pad_io_soc_out;
     output top_width_0_height_0_subtile_0__pin_inpad_0_;
     output top_width_0_height_0_subtile_1__pin_inpad_0_;
     output top_width_0_height_0_subtile_2__pin_inpad_0_;
     output top_width_0_height_0_subtile_3__pin_inpad_0_;
 
-    wire IO_ISOL_N;
     wire ccff_head;
     wire ccff_tail;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    wire [0:3]gfpga_pad_io_soc_dir;
+    wire [0:3]gfpga_pad_io_soc_in;
+    wire [0:3]gfpga_pad_io_soc_out;
+    wire isol_n;
     wire logical_tile_io_mode_io__0_ccff_tail;
     wire logical_tile_io_mode_io__1_ccff_tail;
     wire logical_tile_io_mode_io__2_ccff_tail;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
     wire top_width_0_height_0_subtile_0__pin_inpad_0_;
     wire top_width_0_height_0_subtile_0__pin_outpad_0_;
     wire top_width_0_height_0_subtile_1__pin_inpad_0_;
@@ -59,54 +59,54 @@ module grid_io_bottom_bottom
 
     logical_tile_io_mode_io_ logical_tile_io_mode_io__0
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(ccff_head),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
         .io_outpad(top_width_0_height_0_subtile_0__pin_outpad_0_),
-        .pReset(pReset),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(logical_tile_io_mode_io__0_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
         .io_inpad(top_width_0_height_0_subtile_0__pin_inpad_0_)
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__1
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(logical_tile_io_mode_io__0_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
         .io_outpad(top_width_0_height_0_subtile_1__pin_outpad_0_),
-        .pReset(pReset),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(logical_tile_io_mode_io__1_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
         .io_inpad(top_width_0_height_0_subtile_1__pin_inpad_0_)
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__2
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(logical_tile_io_mode_io__1_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
         .io_outpad(top_width_0_height_0_subtile_2__pin_outpad_0_),
-        .pReset(pReset),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(logical_tile_io_mode_io__2_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
         .io_inpad(top_width_0_height_0_subtile_2__pin_inpad_0_)
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__3
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(logical_tile_io_mode_io__2_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
         .io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_),
-        .pReset(pReset),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
         .io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_)
     );
 endmodule
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_left_left.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_left_left.v
index 9883717..ccb9322 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_left_left.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_left_left.v
@@ -2,52 +2,52 @@
 //netlist name: FPGA88_SOFA_A
 module grid_io_left_left
 (
-    IO_ISOL_N,
     ccff_head,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    pReset,
+    gfpga_pad_io_soc_in,
+    isol_n,
     prog_clk,
+    prog_reset,
     right_width_0_height_0_subtile_0__pin_outpad_0_,
     right_width_0_height_0_subtile_1__pin_outpad_0_,
     right_width_0_height_0_subtile_2__pin_outpad_0_,
     right_width_0_height_0_subtile_3__pin_outpad_0_,
     ccff_tail,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    gfpga_pad_io_soc_dir,
+    gfpga_pad_io_soc_out,
     right_width_0_height_0_subtile_0__pin_inpad_0_,
     right_width_0_height_0_subtile_1__pin_inpad_0_,
     right_width_0_height_0_subtile_2__pin_inpad_0_,
     right_width_0_height_0_subtile_3__pin_inpad_0_
 );
 
-    input IO_ISOL_N;
     input ccff_head;
-    input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    input pReset;
+    input [0:3]gfpga_pad_io_soc_in;
+    input isol_n;
     input prog_clk;
+    input prog_reset;
     input right_width_0_height_0_subtile_0__pin_outpad_0_;
     input right_width_0_height_0_subtile_1__pin_outpad_0_;
     input right_width_0_height_0_subtile_2__pin_outpad_0_;
     input right_width_0_height_0_subtile_3__pin_outpad_0_;
     output ccff_tail;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output [0:3]gfpga_pad_io_soc_dir;
+    output [0:3]gfpga_pad_io_soc_out;
     output right_width_0_height_0_subtile_0__pin_inpad_0_;
     output right_width_0_height_0_subtile_1__pin_inpad_0_;
     output right_width_0_height_0_subtile_2__pin_inpad_0_;
     output right_width_0_height_0_subtile_3__pin_inpad_0_;
 
-    wire IO_ISOL_N;
     wire ccff_head;
     wire ccff_tail;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    wire [0:3]gfpga_pad_io_soc_dir;
+    wire [0:3]gfpga_pad_io_soc_in;
+    wire [0:3]gfpga_pad_io_soc_out;
+    wire isol_n;
     wire logical_tile_io_mode_io__0_ccff_tail;
     wire logical_tile_io_mode_io__1_ccff_tail;
     wire logical_tile_io_mode_io__2_ccff_tail;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
     wire right_width_0_height_0_subtile_0__pin_inpad_0_;
     wire right_width_0_height_0_subtile_0__pin_outpad_0_;
     wire right_width_0_height_0_subtile_1__pin_inpad_0_;
@@ -59,54 +59,54 @@ module grid_io_left_left
 
     logical_tile_io_mode_io_ logical_tile_io_mode_io__0
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(ccff_head),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
         .io_outpad(right_width_0_height_0_subtile_0__pin_outpad_0_),
-        .pReset(pReset),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(logical_tile_io_mode_io__0_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
         .io_inpad(right_width_0_height_0_subtile_0__pin_inpad_0_)
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__1
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(logical_tile_io_mode_io__0_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
         .io_outpad(right_width_0_height_0_subtile_1__pin_outpad_0_),
-        .pReset(pReset),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(logical_tile_io_mode_io__1_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
         .io_inpad(right_width_0_height_0_subtile_1__pin_inpad_0_)
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__2
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(logical_tile_io_mode_io__1_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
         .io_outpad(right_width_0_height_0_subtile_2__pin_outpad_0_),
-        .pReset(pReset),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(logical_tile_io_mode_io__2_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
         .io_inpad(right_width_0_height_0_subtile_2__pin_inpad_0_)
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__3
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(logical_tile_io_mode_io__2_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
         .io_outpad(right_width_0_height_0_subtile_3__pin_outpad_0_),
-        .pReset(pReset),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
         .io_inpad(right_width_0_height_0_subtile_3__pin_inpad_0_)
     );
 endmodule
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_right_right.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_right_right.v
index 726a666..b1ede87 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_right_right.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_right_right.v
@@ -2,47 +2,47 @@
 //netlist name: FPGA88_SOFA_A
 module grid_io_right_right
 (
-    IO_ISOL_N,
     ccff_head,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
+    gfpga_pad_io_soc_in,
+    isol_n,
     left_width_0_height_0_subtile_0__pin_outpad_0_,
     left_width_0_height_0_subtile_1__pin_outpad_0_,
     left_width_0_height_0_subtile_2__pin_outpad_0_,
     left_width_0_height_0_subtile_3__pin_outpad_0_,
-    pReset,
     prog_clk,
+    prog_reset,
     ccff_tail,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    gfpga_pad_io_soc_dir,
+    gfpga_pad_io_soc_out,
     left_width_0_height_0_subtile_0__pin_inpad_0_,
     left_width_0_height_0_subtile_1__pin_inpad_0_,
     left_width_0_height_0_subtile_2__pin_inpad_0_,
     left_width_0_height_0_subtile_3__pin_inpad_0_
 );
 
-    input IO_ISOL_N;
     input ccff_head;
-    input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    input [0:3]gfpga_pad_io_soc_in;
+    input isol_n;
     input left_width_0_height_0_subtile_0__pin_outpad_0_;
     input left_width_0_height_0_subtile_1__pin_outpad_0_;
     input left_width_0_height_0_subtile_2__pin_outpad_0_;
     input left_width_0_height_0_subtile_3__pin_outpad_0_;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output [0:3]gfpga_pad_io_soc_dir;
+    output [0:3]gfpga_pad_io_soc_out;
     output left_width_0_height_0_subtile_0__pin_inpad_0_;
     output left_width_0_height_0_subtile_1__pin_inpad_0_;
     output left_width_0_height_0_subtile_2__pin_inpad_0_;
     output left_width_0_height_0_subtile_3__pin_inpad_0_;
 
-    wire IO_ISOL_N;
     wire ccff_head;
     wire ccff_tail;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    wire [0:3]gfpga_pad_io_soc_dir;
+    wire [0:3]gfpga_pad_io_soc_in;
+    wire [0:3]gfpga_pad_io_soc_out;
+    wire isol_n;
     wire left_width_0_height_0_subtile_0__pin_inpad_0_;
     wire left_width_0_height_0_subtile_0__pin_outpad_0_;
     wire left_width_0_height_0_subtile_1__pin_inpad_0_;
@@ -54,59 +54,59 @@ module grid_io_right_right
     wire logical_tile_io_mode_io__0_ccff_tail;
     wire logical_tile_io_mode_io__1_ccff_tail;
     wire logical_tile_io_mode_io__2_ccff_tail;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
     logical_tile_io_mode_io_ logical_tile_io_mode_io__0
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(ccff_head),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
         .io_outpad(left_width_0_height_0_subtile_0__pin_outpad_0_),
-        .pReset(pReset),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(logical_tile_io_mode_io__0_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
         .io_inpad(left_width_0_height_0_subtile_0__pin_inpad_0_)
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__1
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(logical_tile_io_mode_io__0_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
         .io_outpad(left_width_0_height_0_subtile_1__pin_outpad_0_),
-        .pReset(pReset),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(logical_tile_io_mode_io__1_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
         .io_inpad(left_width_0_height_0_subtile_1__pin_inpad_0_)
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__2
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(logical_tile_io_mode_io__1_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
         .io_outpad(left_width_0_height_0_subtile_2__pin_outpad_0_),
-        .pReset(pReset),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(logical_tile_io_mode_io__2_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
         .io_inpad(left_width_0_height_0_subtile_2__pin_inpad_0_)
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__3
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(logical_tile_io_mode_io__2_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
         .io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_),
-        .pReset(pReset),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
         .io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_)
     );
 endmodule
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_top_top.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_top_top.v
index 51b2e73..6b21f81 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_top_top.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/grid_io_top_top.v
@@ -2,42 +2,41 @@
 //netlist name: FPGA88_SOFA_A
 module grid_io_top_top
 (
-    IO_ISOL_N,
     bottom_width_0_height_0_subtile_0__pin_outpad_0_,
     bottom_width_0_height_0_subtile_1__pin_outpad_0_,
     bottom_width_0_height_0_subtile_2__pin_outpad_0_,
     bottom_width_0_height_0_subtile_3__pin_outpad_0_,
     ccff_head,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    pReset,
+    gfpga_pad_io_soc_in,
+    isol_n,
     prog_clk,
+    prog_reset,
     bottom_width_0_height_0_subtile_0__pin_inpad_0_,
     bottom_width_0_height_0_subtile_1__pin_inpad_0_,
     bottom_width_0_height_0_subtile_2__pin_inpad_0_,
     bottom_width_0_height_0_subtile_3__pin_inpad_0_,
     ccff_tail,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT
+    gfpga_pad_io_soc_dir,
+    gfpga_pad_io_soc_out
 );
 
-    input IO_ISOL_N;
     input bottom_width_0_height_0_subtile_0__pin_outpad_0_;
     input bottom_width_0_height_0_subtile_1__pin_outpad_0_;
     input bottom_width_0_height_0_subtile_2__pin_outpad_0_;
     input bottom_width_0_height_0_subtile_3__pin_outpad_0_;
     input ccff_head;
-    input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    input pReset;
+    input [0:3]gfpga_pad_io_soc_in;
+    input isol_n;
     input prog_clk;
+    input prog_reset;
     output bottom_width_0_height_0_subtile_0__pin_inpad_0_;
     output bottom_width_0_height_0_subtile_1__pin_inpad_0_;
     output bottom_width_0_height_0_subtile_2__pin_inpad_0_;
     output bottom_width_0_height_0_subtile_3__pin_inpad_0_;
     output ccff_tail;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output [0:3]gfpga_pad_io_soc_dir;
+    output [0:3]gfpga_pad_io_soc_out;
 
-    wire IO_ISOL_N;
     wire bottom_width_0_height_0_subtile_0__pin_inpad_0_;
     wire bottom_width_0_height_0_subtile_0__pin_outpad_0_;
     wire bottom_width_0_height_0_subtile_1__pin_inpad_0_;
@@ -48,65 +47,66 @@ module grid_io_top_top
     wire bottom_width_0_height_0_subtile_3__pin_outpad_0_;
     wire ccff_head;
     wire ccff_tail;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    wire [0:3]gfpga_pad_io_soc_dir;
+    wire [0:3]gfpga_pad_io_soc_in;
+    wire [0:3]gfpga_pad_io_soc_out;
+    wire isol_n;
     wire logical_tile_io_mode_io__0_ccff_tail;
     wire logical_tile_io_mode_io__1_ccff_tail;
     wire logical_tile_io_mode_io__2_ccff_tail;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
     logical_tile_io_mode_io_ logical_tile_io_mode_io__0
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(ccff_head),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
         .io_outpad(bottom_width_0_height_0_subtile_0__pin_outpad_0_),
-        .pReset(pReset),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(logical_tile_io_mode_io__0_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
         .io_inpad(bottom_width_0_height_0_subtile_0__pin_inpad_0_)
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__1
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(logical_tile_io_mode_io__0_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
         .io_outpad(bottom_width_0_height_0_subtile_1__pin_outpad_0_),
-        .pReset(pReset),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(logical_tile_io_mode_io__1_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
         .io_inpad(bottom_width_0_height_0_subtile_1__pin_inpad_0_)
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__2
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(logical_tile_io_mode_io__1_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
         .io_outpad(bottom_width_0_height_0_subtile_2__pin_outpad_0_),
-        .pReset(pReset),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(logical_tile_io_mode_io__2_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
         .io_inpad(bottom_width_0_height_0_subtile_2__pin_inpad_0_)
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__3
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(logical_tile_io_mode_io__2_ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
         .io_outpad(bottom_width_0_height_0_subtile_3__pin_outpad_0_),
-        .pReset(pReset),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
         .io_inpad(bottom_width_0_height_0_subtile_3__pin_inpad_0_)
     );
 endmodule
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/io_sky130_fd_sc_hd__dfrtp_1_mem.v
similarity index 78%
rename from SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.v
rename to SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/io_sky130_fd_sc_hd__dfrtp_1_mem.v
index 4757823..0de068b 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/io_sky130_fd_sc_hd__dfrtp_1_mem.v
@@ -1,32 +1,32 @@
 //Generated from netlist by SpyDrNet
 //netlist name: FPGA88_SOFA_A
-module EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem
+module io_sky130_fd_sc_hd__dfrtp_1_mem
 (
     ccff_head,
-    pReset,
     prog_clk,
+    prog_reset,
     ccff_tail,
     mem_out
 );
 
     input ccff_head;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output mem_out;
 
     wire ccff_head;
     wire ccff_tail;
     wire mem_out;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
 assign ccff_tail = mem_out;
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
         .CLK(prog_clk),
         .D(ccff_head),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out)
     );
 endmodule
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_clb_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_clb_.v
index 3249ee0..17b7108 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_clb_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_clb_.v
@@ -2,7 +2,6 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_clb_mode_clb_
 (
-    Test_en,
     ccff_head,
     clb_I0,
     clb_I0i,
@@ -25,8 +24,9 @@ module logical_tile_clb_mode_clb_
     clb_reg_in,
     clb_reset,
     clb_sc_in,
-    pReset,
     prog_clk,
+    prog_reset,
+    scan_enable,
     ccff_tail,
     clb_O,
     clb_cout,
@@ -34,7 +34,6 @@ module logical_tile_clb_mode_clb_
     clb_sc_out
 );
 
-    input Test_en;
     input ccff_head;
     input [0:1]clb_I0;
     input [0:1]clb_I0i;
@@ -57,15 +56,15 @@ module logical_tile_clb_mode_clb_
     input clb_reg_in;
     input clb_reset;
     input clb_sc_in;
-    input pReset;
     input prog_clk;
+    input prog_reset;
+    input scan_enable;
     output ccff_tail;
     output [0:15]clb_O;
     output clb_cout;
     output clb_reg_out;
     output clb_sc_out;
 
-    wire Test_en;
     wire ccff_head;
     wire ccff_tail;
     wire [0:1]clb_I0;
@@ -204,8 +203,9 @@ module logical_tile_clb_mode_clb_
     wire [0:1]logical_tile_clb_mode_default__fle_7_fle_out;
     wire logical_tile_clb_mode_default__fle_7_fle_reg_out;
     wire logical_tile_clb_mode_default__fle_7_fle_sc_out;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
+    wire scan_enable;
 
     direct_interc direct_interc_0_
     (
@@ -664,7 +664,6 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0
     (
-        .Test_en(Test_en),
         .ccff_head(ccff_head),
         .fle_cin(direct_interc_25_out),
         .fle_clk(direct_interc_27_out),
@@ -672,8 +671,9 @@ module logical_tile_clb_mode_clb_
         .fle_reg_in(direct_interc_23_out),
         .fle_reset(direct_interc_26_out),
         .fle_sc_in(direct_interc_24_out),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
+        .scan_enable(scan_enable),
         .ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail),
         .fle_cout(logical_tile_clb_mode_default__fle_0_fle_cout),
         .fle_out(logical_tile_clb_mode_default__fle_0_fle_out),
@@ -682,7 +682,6 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1
     (
-        .Test_en(Test_en),
         .ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail),
         .fle_cin(direct_interc_34_out),
         .fle_clk(direct_interc_36_out),
@@ -690,8 +689,9 @@ module logical_tile_clb_mode_clb_
         .fle_reg_in(direct_interc_32_out),
         .fle_reset(direct_interc_35_out),
         .fle_sc_in(direct_interc_33_out),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
+        .scan_enable(scan_enable),
         .ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail),
         .fle_cout(logical_tile_clb_mode_default__fle_1_fle_cout),
         .fle_out(logical_tile_clb_mode_default__fle_1_fle_out),
@@ -700,7 +700,6 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2
     (
-        .Test_en(Test_en),
         .ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail),
         .fle_cin(direct_interc_43_out),
         .fle_clk(direct_interc_45_out),
@@ -708,8 +707,9 @@ module logical_tile_clb_mode_clb_
         .fle_reg_in(direct_interc_41_out),
         .fle_reset(direct_interc_44_out),
         .fle_sc_in(direct_interc_42_out),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
+        .scan_enable(scan_enable),
         .ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail),
         .fle_cout(logical_tile_clb_mode_default__fle_2_fle_cout),
         .fle_out(logical_tile_clb_mode_default__fle_2_fle_out),
@@ -718,7 +718,6 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3
     (
-        .Test_en(Test_en),
         .ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail),
         .fle_cin(direct_interc_52_out),
         .fle_clk(direct_interc_54_out),
@@ -726,8 +725,9 @@ module logical_tile_clb_mode_clb_
         .fle_reg_in(direct_interc_50_out),
         .fle_reset(direct_interc_53_out),
         .fle_sc_in(direct_interc_51_out),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
+        .scan_enable(scan_enable),
         .ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail),
         .fle_cout(logical_tile_clb_mode_default__fle_3_fle_cout),
         .fle_out(logical_tile_clb_mode_default__fle_3_fle_out),
@@ -736,7 +736,6 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4
     (
-        .Test_en(Test_en),
         .ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail),
         .fle_cin(direct_interc_61_out),
         .fle_clk(direct_interc_63_out),
@@ -744,8 +743,9 @@ module logical_tile_clb_mode_clb_
         .fle_reg_in(direct_interc_59_out),
         .fle_reset(direct_interc_62_out),
         .fle_sc_in(direct_interc_60_out),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
+        .scan_enable(scan_enable),
         .ccff_tail(logical_tile_clb_mode_default__fle_4_ccff_tail),
         .fle_cout(logical_tile_clb_mode_default__fle_4_fle_cout),
         .fle_out(logical_tile_clb_mode_default__fle_4_fle_out),
@@ -754,7 +754,6 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5
     (
-        .Test_en(Test_en),
         .ccff_head(logical_tile_clb_mode_default__fle_4_ccff_tail),
         .fle_cin(direct_interc_70_out),
         .fle_clk(direct_interc_72_out),
@@ -762,8 +761,9 @@ module logical_tile_clb_mode_clb_
         .fle_reg_in(direct_interc_68_out),
         .fle_reset(direct_interc_71_out),
         .fle_sc_in(direct_interc_69_out),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
+        .scan_enable(scan_enable),
         .ccff_tail(logical_tile_clb_mode_default__fle_5_ccff_tail),
         .fle_cout(logical_tile_clb_mode_default__fle_5_fle_cout),
         .fle_out(logical_tile_clb_mode_default__fle_5_fle_out),
@@ -772,7 +772,6 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6
     (
-        .Test_en(Test_en),
         .ccff_head(logical_tile_clb_mode_default__fle_5_ccff_tail),
         .fle_cin(direct_interc_79_out),
         .fle_clk(direct_interc_81_out),
@@ -780,8 +779,9 @@ module logical_tile_clb_mode_clb_
         .fle_reg_in(direct_interc_77_out),
         .fle_reset(direct_interc_80_out),
         .fle_sc_in(direct_interc_78_out),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
+        .scan_enable(scan_enable),
         .ccff_tail(logical_tile_clb_mode_default__fle_6_ccff_tail),
         .fle_cout(logical_tile_clb_mode_default__fle_6_fle_cout),
         .fle_out(logical_tile_clb_mode_default__fle_6_fle_out),
@@ -790,7 +790,6 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7
     (
-        .Test_en(Test_en),
         .ccff_head(logical_tile_clb_mode_default__fle_6_ccff_tail),
         .fle_cin(direct_interc_88_out),
         .fle_clk(direct_interc_90_out),
@@ -798,8 +797,9 @@ module logical_tile_clb_mode_clb_
         .fle_reg_in(direct_interc_86_out),
         .fle_reset(direct_interc_89_out),
         .fle_sc_in(direct_interc_87_out),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
+        .scan_enable(scan_enable),
         .ccff_tail(ccff_tail),
         .fle_cout(logical_tile_clb_mode_default__fle_7_fle_cout),
         .fle_out(logical_tile_clb_mode_default__fle_7_fle_out),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle.v
index 8c042cc..f94ab4b 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle.v
@@ -2,7 +2,6 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_clb_mode_default__fle
 (
-    Test_en,
     ccff_head,
     fle_cin,
     fle_clk,
@@ -10,8 +9,9 @@ module logical_tile_clb_mode_default__fle
     fle_reg_in,
     fle_reset,
     fle_sc_in,
-    pReset,
     prog_clk,
+    prog_reset,
+    scan_enable,
     ccff_tail,
     fle_cout,
     fle_out,
@@ -19,7 +19,6 @@ module logical_tile_clb_mode_default__fle
     fle_sc_out
 );
 
-    input Test_en;
     input ccff_head;
     input fle_cin;
     input fle_clk;
@@ -27,15 +26,15 @@ module logical_tile_clb_mode_default__fle
     input fle_reg_in;
     input fle_reset;
     input fle_sc_in;
-    input pReset;
     input prog_clk;
+    input prog_reset;
+    input scan_enable;
     output ccff_tail;
     output fle_cout;
     output [0:1]fle_out;
     output fle_reg_out;
     output fle_sc_out;
 
-    wire Test_en;
     wire ccff_head;
     wire ccff_tail;
     wire direct_interc_10_out;
@@ -61,8 +60,9 @@ module logical_tile_clb_mode_default__fle
     wire [0:1]logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out;
     wire logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out;
     wire logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
+    wire scan_enable;
 
     direct_interc direct_interc_0_
     (
@@ -136,7 +136,6 @@ module logical_tile_clb_mode_default__fle
     );
     logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0
     (
-        .Test_en(Test_en),
         .ccff_head(ccff_head),
         .fabric_cin(direct_interc_11_out),
         .fabric_clk(direct_interc_13_out),
@@ -144,8 +143,9 @@ module logical_tile_clb_mode_default__fle
         .fabric_reg_in(direct_interc_9_out),
         .fabric_reset(direct_interc_12_out),
         .fabric_sc_in(direct_interc_10_out),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
+        .scan_enable(scan_enable),
         .ccff_tail(ccff_tail),
         .fabric_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout),
         .fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
index 3328140..7e3e609 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
@@ -2,7 +2,6 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_clb_mode_default__fle_mode_physical__fabric
 (
-    Test_en,
     ccff_head,
     fabric_cin,
     fabric_clk,
@@ -10,8 +9,9 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     fabric_reg_in,
     fabric_reset,
     fabric_sc_in,
-    pReset,
     prog_clk,
+    prog_reset,
+    scan_enable,
     ccff_tail,
     fabric_cout,
     fabric_out,
@@ -19,7 +19,6 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     fabric_sc_out
 );
 
-    input Test_en;
     input ccff_head;
     input fabric_cin;
     input fabric_clk;
@@ -27,15 +26,15 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     input fabric_reg_in;
     input fabric_reset;
     input fabric_sc_in;
-    input pReset;
     input prog_clk;
+    input prog_reset;
+    input scan_enable;
     output ccff_tail;
     output fabric_cout;
     output [0:1]fabric_out;
     output fabric_reg_out;
     output fabric_sc_out;
 
-    wire Test_en;
     wire ccff_head;
     wire ccff_tail;
     wire direct_interc_10_out;
@@ -77,8 +76,9 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     wire mux_tree_size2_mem_0_ccff_tail;
     wire mux_tree_size2_mem_1_ccff_tail;
     wire mux_tree_size2_mem_2_ccff_tail;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
+    wire scan_enable;
 
     direct_interc direct_interc_0_
     (
@@ -152,20 +152,20 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     );
     logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0
     (
-        .Test_en(Test_en),
         .ff_D(mux_tree_size2_2_out),
         .ff_DI(direct_interc_8_out),
         .ff_clk(direct_interc_10_out),
         .ff_reset(direct_interc_9_out),
+        .scan_enable(scan_enable),
         .ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q)
     );
     logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1
     (
-        .Test_en(Test_en),
         .ff_D(mux_tree_size2_3_out),
         .ff_DI(direct_interc_11_out),
         .ff_clk(direct_interc_13_out),
         .ff_reset(direct_interc_12_out),
+        .scan_enable(scan_enable),
         .ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q)
     );
     logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0
@@ -173,8 +173,8 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
         .ccff_head(ccff_head),
         .frac_logic_cin(direct_interc_7_out),
         .frac_logic_in({direct_interc_3_out, direct_interc_4_out, direct_interc_5_out, direct_interc_6_out}),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail),
         .frac_logic_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout),
         .frac_logic_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out)
@@ -182,32 +182,32 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     mux_tree_size2_mem mem_fabric_out_0
     (
         .ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_size2_mem_0_ccff_tail),
         .mem_out(mux_tree_size2_0_sram)
     );
     mux_tree_size2_mem mem_fabric_out_1
     (
         .ccff_head(mux_tree_size2_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_size2_mem_1_ccff_tail),
         .mem_out(mux_tree_size2_1_sram)
     );
     mux_tree_size2_mem mem_ff_0_D_0
     (
         .ccff_head(mux_tree_size2_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_size2_mem_2_ccff_tail),
         .mem_out(mux_tree_size2_2_sram)
     );
     mux_tree_size2_mem mem_ff_1_D_0
     (
         .ccff_head(mux_tree_size2_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
         .mem_out(mux_tree_size2_3_sram)
     );
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v
index 7bb0f9e..a801740 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v
@@ -2,27 +2,27 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
 (
-    Test_en,
     ff_D,
     ff_DI,
     ff_clk,
     ff_reset,
+    scan_enable,
     ff_Q
 );
 
-    input Test_en;
     input ff_D;
     input ff_DI;
     input ff_clk;
     input ff_reset;
+    input scan_enable;
     output ff_Q;
 
-    wire Test_en;
     wire ff_D;
     wire ff_DI;
     wire ff_Q;
     wire ff_clk;
     wire ff_reset;
+    wire scan_enable;
 
     sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_
     (
@@ -30,7 +30,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
         .D(ff_D),
         .RESET_B(ff_reset),
         .SCD(ff_DI),
-        .SCE(Test_en),
+        .SCE(scan_enable),
         .Q(ff_Q)
     );
 endmodule
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v
index e01a31d..d8b50b1 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v
@@ -5,8 +5,8 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
     ccff_head,
     frac_logic_cin,
     frac_logic_in,
-    pReset,
     prog_clk,
+    prog_reset,
     ccff_tail,
     frac_logic_cout,
     frac_logic_out
@@ -15,8 +15,8 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
     input ccff_head;
     input frac_logic_cin;
     input [0:3]frac_logic_in;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output frac_logic_cout;
     output [0:1]frac_logic_out;
@@ -44,8 +44,8 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
     wire mux_tree_size2_1_out;
     wire [0:1]mux_tree_size2_1_sram;
     wire mux_tree_size2_mem_0_ccff_tail;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
     direct_interc direct_interc_0_
     (
@@ -98,8 +98,8 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
     (
         .ccff_head(ccff_head),
         .frac_lut4_in({direct_interc_2_out, direct_interc_3_out, mux_tree_size2_1_out, direct_interc_4_out}),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail),
         .frac_lut4_lut2_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out),
         .frac_lut4_lut3_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out),
@@ -108,16 +108,16 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
     mux_tree_size2_mem mem_frac_logic_out_0
     (
         .ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_size2_mem_0_ccff_tail),
         .mem_out(mux_tree_size2_0_sram)
     );
     mux_tree_size2_mem mem_frac_lut4_0_in_2
     (
         .ccff_head(mux_tree_size2_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
         .mem_out(mux_tree_size2_1_sram)
     );
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v
index 3d49b1f..8cbbdce 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v
@@ -4,8 +4,8 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
 (
     ccff_head,
     frac_lut4_in,
-    pReset,
     prog_clk,
+    prog_reset,
     ccff_tail,
     frac_lut4_lut2_out,
     frac_lut4_lut3_out,
@@ -14,8 +14,8 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
 
     input ccff_head;
     input [0:3]frac_lut4_in;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output [0:1]frac_lut4_lut2_out;
     output [0:1]frac_lut4_lut3_out;
@@ -31,8 +31,8 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
     wire [0:1]frac_lut4_lut2_out;
     wire [0:1]frac_lut4_lut3_out;
     wire frac_lut4_lut4_out;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
     frac_lut4 frac_lut4_0_
     (
@@ -48,8 +48,8 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
     frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem
     (
         .ccff_head(ccff_head),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
         .mem_out({frac_lut4_0_sram[0], frac_lut4_0_sram[1], frac_lut4_0_sram[2], frac_lut4_0_sram[3], frac_lut4_0_sram[4], frac_lut4_0_sram[5], frac_lut4_0_sram[6], frac_lut4_0_sram[7], frac_lut4_0_sram[8], frac_lut4_0_sram[9], frac_lut4_0_sram[10], frac_lut4_0_sram[11], frac_lut4_0_sram[12], frac_lut4_0_sram[13], frac_lut4_0_sram[14], frac_lut4_0_sram[15], frac_lut4_0_mode})
     );
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_io_mode_io_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_io_mode_io_.v
index 8f186ab..b92a16b 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_io_mode_io_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_io_mode_io_.v
@@ -2,41 +2,41 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_io_mode_io_
 (
-    IO_ISOL_N,
     ccff_head,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
+    gfpga_pad_io_soc_in,
     io_outpad,
-    pReset,
+    isol_n,
     prog_clk,
+    prog_reset,
     ccff_tail,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    gfpga_pad_io_soc_dir,
+    gfpga_pad_io_soc_out,
     io_inpad
 );
 
-    input IO_ISOL_N;
     input ccff_head;
-    input gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    input gfpga_pad_io_soc_in;
     input io_outpad;
-    input pReset;
+    input isol_n;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
-    output gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    output gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output gfpga_pad_io_soc_dir;
+    output gfpga_pad_io_soc_out;
     output io_inpad;
 
-    wire IO_ISOL_N;
     wire ccff_head;
     wire ccff_tail;
     wire direct_interc_1_out;
-    wire gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    wire gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    wire gfpga_pad_io_soc_dir;
+    wire gfpga_pad_io_soc_in;
+    wire gfpga_pad_io_soc_out;
     wire io_inpad;
     wire io_outpad;
+    wire isol_n;
     wire logical_tile_io_mode_physical__iopad_0_iopad_inpad;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
     direct_interc direct_interc_0_
     (
@@ -50,15 +50,15 @@ module logical_tile_io_mode_io_
     );
     logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(ccff_head),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
         .iopad_outpad(direct_interc_1_out),
-        .pReset(pReset),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
         .iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad)
     );
 endmodule
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_io_mode_physical__iopad.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_io_mode_physical__iopad.v
index d73ea95..4295937 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_io_mode_physical__iopad.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/logical_tile_io_mode_physical__iopad.v
@@ -2,58 +2,58 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_io_mode_physical__iopad
 (
-    IO_ISOL_N,
     ccff_head,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
+    gfpga_pad_io_soc_in,
     iopad_outpad,
-    pReset,
+    isol_n,
     prog_clk,
+    prog_reset,
     ccff_tail,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    gfpga_pad_io_soc_dir,
+    gfpga_pad_io_soc_out,
     iopad_inpad
 );
 
-    input IO_ISOL_N;
     input ccff_head;
-    input gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    input gfpga_pad_io_soc_in;
     input iopad_outpad;
-    input pReset;
+    input isol_n;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
-    output gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    output gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output gfpga_pad_io_soc_dir;
+    output gfpga_pad_io_soc_out;
     output iopad_inpad;
 
-    wire EMBEDDED_IO_HD_0_en;
-    wire IO_ISOL_N;
     wire ccff_head;
     wire ccff_tail;
-    wire gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    wire gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    wire gfpga_pad_io_soc_dir;
+    wire gfpga_pad_io_soc_in;
+    wire gfpga_pad_io_soc_out;
+    wire io_0_en;
     wire iopad_inpad;
     wire iopad_outpad;
-    wire pReset;
+    wire isol_n;
     wire prog_clk;
+    wire prog_reset;
 
-    EMBEDDED_IO_HD EMBEDDED_IO_HD_0_
+    io io_0_
     (
-        .FPGA_DIR(EMBEDDED_IO_HD_0_en),
+        .FPGA_DIR(io_0_en),
         .FPGA_OUT(iopad_outpad),
-        .IO_ISOL_N(IO_ISOL_N),
-        .SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
+        .IO_ISOL_N(isol_n),
+        .SOC_IN(gfpga_pad_io_soc_in),
         .FPGA_IN(iopad_inpad),
-        .SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
-        .SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT)
+        .SOC_DIR(gfpga_pad_io_soc_dir),
+        .SOC_OUT(gfpga_pad_io_soc_out)
     );
-    EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem
+    io_sky130_fd_sc_hd__dfrtp_1_mem io_sky130_fd_sc_hd__dfrtp_1_mem
     (
         .ccff_head(ccff_head),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
-        .mem_out(EMBEDDED_IO_HD_0_en)
+        .mem_out(io_0_en)
     );
 endmodule
 
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_size2_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_size2_mem.v
index d5ba29e..d319b14 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_size2_mem.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_size2_mem.v
@@ -3,37 +3,37 @@
 module mux_tree_size2_mem
 (
     ccff_head,
-    pReset,
     prog_clk,
+    prog_reset,
     ccff_tail,
     mem_out
 );
 
     input ccff_head;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output [0:1]mem_out;
 
     wire ccff_head;
     wire ccff_tail;
     wire [0:1]mem_out;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
 assign ccff_tail = mem_out[1];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
         .CLK(prog_clk),
         .D(ccff_head),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
         .CLK(prog_clk),
         .D(mem_out[0]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[1])
     );
 endmodule
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size10_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size10_mem.v
index 1cae90e..7de9ca6 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size10_mem.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size10_mem.v
@@ -3,51 +3,51 @@
 module mux_tree_tapbuf_size10_mem
 (
     ccff_head,
-    pReset,
     prog_clk,
+    prog_reset,
     ccff_tail,
     mem_out
 );
 
     input ccff_head;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output [0:3]mem_out;
 
     wire ccff_head;
     wire ccff_tail;
     wire [0:3]mem_out;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
 assign ccff_tail = mem_out[3];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
         .CLK(prog_clk),
         .D(ccff_head),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
         .CLK(prog_clk),
         .D(mem_out[0]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
         .CLK(prog_clk),
         .D(mem_out[1]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[2])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
     (
         .CLK(prog_clk),
         .D(mem_out[2]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[3])
     );
 endmodule
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size11_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size11_mem.v
index 43bcce1..548911d 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size11_mem.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size11_mem.v
@@ -3,51 +3,51 @@
 module mux_tree_tapbuf_size11_mem
 (
     ccff_head,
-    pReset,
     prog_clk,
+    prog_reset,
     ccff_tail,
     mem_out
 );
 
     input ccff_head;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output [0:3]mem_out;
 
     wire ccff_head;
     wire ccff_tail;
     wire [0:3]mem_out;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
 assign ccff_tail = mem_out[3];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
         .CLK(prog_clk),
         .D(ccff_head),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
         .CLK(prog_clk),
         .D(mem_out[0]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
         .CLK(prog_clk),
         .D(mem_out[1]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[2])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
     (
         .CLK(prog_clk),
         .D(mem_out[2]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[3])
     );
 endmodule
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size12_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size12_mem.v
index 5a0fdc8..9895a37 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size12_mem.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size12_mem.v
@@ -3,51 +3,51 @@
 module mux_tree_tapbuf_size12_mem
 (
     ccff_head,
-    pReset,
     prog_clk,
+    prog_reset,
     ccff_tail,
     mem_out
 );
 
     input ccff_head;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output [0:3]mem_out;
 
     wire ccff_head;
     wire ccff_tail;
     wire [0:3]mem_out;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
 assign ccff_tail = mem_out[3];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
         .CLK(prog_clk),
         .D(ccff_head),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
         .CLK(prog_clk),
         .D(mem_out[0]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
         .CLK(prog_clk),
         .D(mem_out[1]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[2])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
     (
         .CLK(prog_clk),
         .D(mem_out[2]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[3])
     );
 endmodule
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size2_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size2_mem.v
index 447f320..db55292 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size2_mem.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size2_mem.v
@@ -3,37 +3,37 @@
 module mux_tree_tapbuf_size2_mem
 (
     ccff_head,
-    pReset,
     prog_clk,
+    prog_reset,
     ccff_tail,
     mem_out
 );
 
     input ccff_head;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output [0:1]mem_out;
 
     wire ccff_head;
     wire ccff_tail;
     wire [0:1]mem_out;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
 assign ccff_tail = mem_out[1];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
         .CLK(prog_clk),
         .D(ccff_head),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
         .CLK(prog_clk),
         .D(mem_out[0]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[1])
     );
 endmodule
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size3_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size3_mem.v
index 9e955a2..e557f11 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size3_mem.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size3_mem.v
@@ -3,37 +3,37 @@
 module mux_tree_tapbuf_size3_mem
 (
     ccff_head,
-    pReset,
     prog_clk,
+    prog_reset,
     ccff_tail,
     mem_out
 );
 
     input ccff_head;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output [0:1]mem_out;
 
     wire ccff_head;
     wire ccff_tail;
     wire [0:1]mem_out;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
 assign ccff_tail = mem_out[1];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
         .CLK(prog_clk),
         .D(ccff_head),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
         .CLK(prog_clk),
         .D(mem_out[0]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[1])
     );
 endmodule
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size4_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size4_mem.v
index 28fb4f3..01fc7cc 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size4_mem.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size4_mem.v
@@ -3,44 +3,44 @@
 module mux_tree_tapbuf_size4_mem
 (
     ccff_head,
-    pReset,
     prog_clk,
+    prog_reset,
     ccff_tail,
     mem_out
 );
 
     input ccff_head;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output [0:2]mem_out;
 
     wire ccff_head;
     wire ccff_tail;
     wire [0:2]mem_out;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
 assign ccff_tail = mem_out[2];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
         .CLK(prog_clk),
         .D(ccff_head),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
         .CLK(prog_clk),
         .D(mem_out[0]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
         .CLK(prog_clk),
         .D(mem_out[1]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[2])
     );
 endmodule
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size5_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size5_mem.v
index 285b187..8952743 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size5_mem.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size5_mem.v
@@ -3,44 +3,44 @@
 module mux_tree_tapbuf_size5_mem
 (
     ccff_head,
-    pReset,
     prog_clk,
+    prog_reset,
     ccff_tail,
     mem_out
 );
 
     input ccff_head;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output [0:2]mem_out;
 
     wire ccff_head;
     wire ccff_tail;
     wire [0:2]mem_out;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
 assign ccff_tail = mem_out[2];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
         .CLK(prog_clk),
         .D(ccff_head),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
         .CLK(prog_clk),
         .D(mem_out[0]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
         .CLK(prog_clk),
         .D(mem_out[1]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[2])
     );
 endmodule
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size6_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size6_mem.v
index 248ae26..e61e42e 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size6_mem.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size6_mem.v
@@ -3,44 +3,44 @@
 module mux_tree_tapbuf_size6_mem
 (
     ccff_head,
-    pReset,
     prog_clk,
+    prog_reset,
     ccff_tail,
     mem_out
 );
 
     input ccff_head;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output [0:2]mem_out;
 
     wire ccff_head;
     wire ccff_tail;
     wire [0:2]mem_out;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
 assign ccff_tail = mem_out[2];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
         .CLK(prog_clk),
         .D(ccff_head),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
         .CLK(prog_clk),
         .D(mem_out[0]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
         .CLK(prog_clk),
         .D(mem_out[1]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[2])
     );
 endmodule
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size7_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size7_mem.v
index dabe18a..eb000a4 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size7_mem.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size7_mem.v
@@ -3,44 +3,44 @@
 module mux_tree_tapbuf_size7_mem
 (
     ccff_head,
-    pReset,
     prog_clk,
+    prog_reset,
     ccff_tail,
     mem_out
 );
 
     input ccff_head;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output [0:2]mem_out;
 
     wire ccff_head;
     wire ccff_tail;
     wire [0:2]mem_out;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
 assign ccff_tail = mem_out[2];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
         .CLK(prog_clk),
         .D(ccff_head),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
         .CLK(prog_clk),
         .D(mem_out[0]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
         .CLK(prog_clk),
         .D(mem_out[1]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[2])
     );
 endmodule
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size8_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size8_mem.v
index 83a9937..b6159f7 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size8_mem.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size8_mem.v
@@ -3,51 +3,51 @@
 module mux_tree_tapbuf_size8_mem
 (
     ccff_head,
-    pReset,
     prog_clk,
+    prog_reset,
     ccff_tail,
     mem_out
 );
 
     input ccff_head;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output [0:3]mem_out;
 
     wire ccff_head;
     wire ccff_tail;
     wire [0:3]mem_out;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
 assign ccff_tail = mem_out[3];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
         .CLK(prog_clk),
         .D(ccff_head),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
         .CLK(prog_clk),
         .D(mem_out[0]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
         .CLK(prog_clk),
         .D(mem_out[1]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[2])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
     (
         .CLK(prog_clk),
         .D(mem_out[2]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[3])
     );
 endmodule
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size9_mem.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size9_mem.v
index 9e4aa9a..7c03d51 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size9_mem.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/mux_tree_tapbuf_size9_mem.v
@@ -3,51 +3,51 @@
 module mux_tree_tapbuf_size9_mem
 (
     ccff_head,
-    pReset,
     prog_clk,
+    prog_reset,
     ccff_tail,
     mem_out
 );
 
     input ccff_head;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output [0:3]mem_out;
 
     wire ccff_head;
     wire ccff_tail;
     wire [0:3]mem_out;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
 assign ccff_tail = mem_out[3];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
         .CLK(prog_clk),
         .D(ccff_head),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
         .CLK(prog_clk),
         .D(mem_out[0]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
         .CLK(prog_clk),
         .D(mem_out[1]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[2])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
     (
         .CLK(prog_clk),
         .D(mem_out[2]),
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .Q(mem_out[3])
     );
 endmodule
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__0_.v
index 4643af3..550dc3e 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__0_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__0_.v
@@ -5,8 +5,8 @@ module sb_0__0_
     ccff_head,
     chanx_right_in,
     chany_top_in,
-    pReset,
     prog_clk,
+    prog_reset,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
     right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
     right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
@@ -23,8 +23,8 @@ module sb_0__0_
     input ccff_head;
     input [0:29]chanx_right_in;
     input [0:29]chany_top_in;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
     input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
     input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
@@ -150,8 +150,8 @@ module sb_0__0_
     wire mux_tree_tapbuf_size3_mem_1_ccff_tail;
     wire mux_tree_tapbuf_size3_mem_2_ccff_tail;
     wire mux_tree_tapbuf_size3_mem_3_ccff_tail;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
     wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
     wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
@@ -188,288 +188,288 @@ assign chanx_right_out[27] = chany_top_in[26];
     mux_tree_tapbuf_size3_mem mem_right_track_0
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_2_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_10
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_19_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_12
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_20_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_14
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_21_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_16
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_22_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_18
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_23_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_2
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_16_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_28
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_24_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_30
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_25_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_32
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_26_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_34
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_27_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_4
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_17_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_44
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_28_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_28_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_46
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_28_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_29_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_29_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_48
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_29_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_30_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_30_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_50
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_30_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_31_sram)
     );
     mux_tree_tapbuf_size3_mem mem_right_track_6
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_3_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_8
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_18_sram)
     );
     mux_tree_tapbuf_size3_mem mem_top_track_0
     (
         .ccff_head(ccff_head),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_0_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_10
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_3_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_12
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_4_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_14
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_5_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_16
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_6_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_18
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_7_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_2
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_0_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_28
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_8_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_30
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_9_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_32
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_10_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_34
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_11_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_4
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_1_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_44
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_12_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_46
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_13_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_48
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_14_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_50
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_15_sram)
     );
     mux_tree_tapbuf_size3_mem mem_top_track_6
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_1_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_8
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_2_sram)
     );
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__1_.v
index ac1ec14..e47d266 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__1_.v
@@ -10,8 +10,8 @@ module sb_0__1_
     chanx_right_in,
     chany_bottom_in,
     chany_top_in,
-    pReset,
     prog_clk,
+    prog_reset,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
@@ -38,8 +38,8 @@ module sb_0__1_
     input [0:29]chanx_right_in;
     input [0:29]chany_bottom_in;
     input [0:29]chany_top_in;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@@ -218,8 +218,8 @@ module sb_0__1_
     wire mux_tree_tapbuf_size7_mem_2_ccff_tail;
     wire mux_tree_tapbuf_size7_mem_3_ccff_tail;
     wire mux_tree_tapbuf_size7_mem_4_ccff_tail;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@@ -275,400 +275,400 @@ assign chany_bottom_out[17] = chany_top_in[16];
     mux_tree_tapbuf_size6_mem mem_bottom_track_1
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_7_sram)
     );
     mux_tree_tapbuf_size7_mem mem_bottom_track_11
     (
         .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size7_4_sram)
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_13
     (
         .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_9_sram)
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_21
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_10_sram)
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_29
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_11_sram)
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_3
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_4_sram)
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_37
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_5_sram)
     );
     mux_tree_tapbuf_size4_mem mem_bottom_track_45
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_9_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_9_sram)
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_5
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_8_sram)
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_53
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_9_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_8_sram)
     );
     mux_tree_tapbuf_size7_mem mem_bottom_track_7
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size7_3_sram)
     );
     mux_tree_tapbuf_size5_mem mem_right_track_0
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_1_sram)
     );
     mux_tree_tapbuf_size5_mem mem_right_track_10
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_3_sram)
     );
     mux_tree_tapbuf_size4_mem mem_right_track_12
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_2_sram)
     );
     mux_tree_tapbuf_size4_mem mem_right_track_14
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_3_sram)
     );
     mux_tree_tapbuf_size4_mem mem_right_track_16
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_4_sram)
     );
     mux_tree_tapbuf_size4_mem mem_right_track_18
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_5_sram)
     );
     mux_tree_tapbuf_size6_mem mem_right_track_2
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_4_sram)
     );
     mux_tree_tapbuf_size4_mem mem_right_track_20
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_6_sram)
     );
     mux_tree_tapbuf_size4_mem mem_right_track_22
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_7_sram)
     );
     mux_tree_tapbuf_size3_mem mem_right_track_24
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_1_sram)
     );
     mux_tree_tapbuf_size3_mem mem_right_track_26
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_2_sram)
     );
     mux_tree_tapbuf_size3_mem mem_right_track_28
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_3_sram)
     );
     mux_tree_tapbuf_size3_mem mem_right_track_30
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_4_sram)
     );
     mux_tree_tapbuf_size3_mem mem_right_track_32
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_5_sram)
     );
     mux_tree_tapbuf_size3_mem mem_right_track_34
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_6_sram)
     );
     mux_tree_tapbuf_size4_mem mem_right_track_36
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_8_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_8_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_38
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_8_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_0_sram)
     );
     mux_tree_tapbuf_size5_mem mem_right_track_4
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_2_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_40
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_1_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_44
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_2_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_46
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_3_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_48
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_4_sram)
     );
     mux_tree_tapbuf_size3_mem mem_right_track_50
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_7_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_52
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_5_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_54
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_6_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_56
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_7_sram)
     );
     mux_tree_tapbuf_size6_mem mem_right_track_6
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_5_sram)
     );
     mux_tree_tapbuf_size6_mem mem_right_track_8
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_6_sram)
     );
     mux_tree_tapbuf_size7_mem mem_top_track_0
     (
         .ccff_head(ccff_head),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size7_0_sram)
     );
     mux_tree_tapbuf_size7_mem mem_top_track_10
     (
         .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size7_2_sram)
     );
     mux_tree_tapbuf_size6_mem mem_top_track_12
     (
         .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_2_sram)
     );
     mux_tree_tapbuf_size6_mem mem_top_track_2
     (
         .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_0_sram)
     );
     mux_tree_tapbuf_size6_mem mem_top_track_20
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_3_sram)
     );
     mux_tree_tapbuf_size5_mem mem_top_track_28
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_0_sram)
     );
     mux_tree_tapbuf_size4_mem mem_top_track_36
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_0_sram)
     );
     mux_tree_tapbuf_size6_mem mem_top_track_4
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_1_sram)
     );
     mux_tree_tapbuf_size3_mem mem_top_track_44
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_0_sram)
     );
     mux_tree_tapbuf_size4_mem mem_top_track_52
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_1_sram)
     );
     mux_tree_tapbuf_size7_mem mem_top_track_6
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size7_1_sram)
     );
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__8_.v
index 413e5de..61c0988 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__8_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_0__8_.v
@@ -9,8 +9,8 @@ module sb_0__8_
     ccff_head,
     chanx_right_in,
     chany_bottom_in,
-    pReset,
     prog_clk,
+    prog_reset,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
@@ -35,8 +35,8 @@ module sb_0__8_
     input ccff_head;
     input [0:29]chanx_right_in;
     input [0:29]chany_bottom_in;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@@ -206,8 +206,8 @@ module sb_0__8_
     wire mux_tree_tapbuf_size5_mem_3_ccff_tail;
     wire mux_tree_tapbuf_size5_mem_4_ccff_tail;
     wire mux_tree_tapbuf_size5_mem_5_ccff_tail;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@@ -236,384 +236,384 @@ assign chany_bottom_out[11] = chanx_right_in[17];
     mux_tree_tapbuf_size3_mem mem_bottom_track_1
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_11_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_11
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_16_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_13
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_17_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_15
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_18_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_17
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_19_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_19
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_20_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_29
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_21_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_3
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_13_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_31
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_22_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_33
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_23_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_35
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_24_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_45
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_25_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_47
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_26_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_49
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_27_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_5
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_14_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_51
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_28_sram)
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_7
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_12_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_9
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_15_sram)
     );
     mux_tree_tapbuf_size5_mem mem_right_track_0
     (
         .ccff_head(ccff_head),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_0_sram)
     );
     mux_tree_tapbuf_size5_mem mem_right_track_10
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_5_sram)
     );
     mux_tree_tapbuf_size3_mem mem_right_track_12
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_0_sram)
     );
     mux_tree_tapbuf_size3_mem mem_right_track_14
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_1_sram)
     );
     mux_tree_tapbuf_size3_mem mem_right_track_16
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_2_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_18
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_0_sram)
     );
     mux_tree_tapbuf_size5_mem mem_right_track_2
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_1_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_20
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_1_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_22
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_2_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_24
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_3_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_26
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_4_sram)
     );
     mux_tree_tapbuf_size3_mem mem_right_track_28
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_3_sram)
     );
     mux_tree_tapbuf_size3_mem mem_right_track_30
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_4_sram)
     );
     mux_tree_tapbuf_size3_mem mem_right_track_32
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_5_sram)
     );
     mux_tree_tapbuf_size3_mem mem_right_track_34
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_6_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_36
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_5_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_38
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_6_sram)
     );
     mux_tree_tapbuf_size5_mem mem_right_track_4
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_2_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_40
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_7_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_42
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_8_sram)
     );
     mux_tree_tapbuf_size3_mem mem_right_track_44
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_7_sram)
     );
     mux_tree_tapbuf_size3_mem mem_right_track_46
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_8_sram)
     );
     mux_tree_tapbuf_size3_mem mem_right_track_48
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_9_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_50
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_9_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_52
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_10_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_54
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_11_sram)
     );
     mux_tree_tapbuf_size2_mem mem_right_track_56
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_12_sram)
     );
     mux_tree_tapbuf_size3_mem mem_right_track_58
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_10_sram)
     );
     mux_tree_tapbuf_size5_mem mem_right_track_6
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_3_sram)
     );
     mux_tree_tapbuf_size5_mem mem_right_track_8
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_4_sram)
     );
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__0_.v
index 1636d61..78c28db 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__0_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__0_.v
@@ -10,8 +10,8 @@ module sb_1__0_
     left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
     left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
     left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
-    pReset,
     prog_clk,
+    prog_reset,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
     right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
     right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
@@ -38,8 +38,8 @@ module sb_1__0_
     input left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
     input left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
     input left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
     input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
     input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
@@ -212,8 +212,8 @@ module sb_1__0_
     wire mux_tree_tapbuf_size7_mem_2_ccff_tail;
     wire mux_tree_tapbuf_size7_mem_3_ccff_tail;
     wire mux_tree_tapbuf_size7_mem_4_ccff_tail;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
     wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
     wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
@@ -272,384 +272,384 @@ assign chanx_left_out[16] = chanx_right_in[15];
     mux_tree_tapbuf_size7_mem mem_left_track_1
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size7_3_sram)
     );
     mux_tree_tapbuf_size7_mem mem_left_track_11
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size7_4_sram)
     );
     mux_tree_tapbuf_size6_mem mem_left_track_13
     (
         .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_10_sram)
     );
     mux_tree_tapbuf_size6_mem mem_left_track_21
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_11_sram)
     );
     mux_tree_tapbuf_size6_mem mem_left_track_29
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_12_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_12_sram)
     );
     mux_tree_tapbuf_size5_mem mem_left_track_3
     (
         .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_3_sram)
     );
     mux_tree_tapbuf_size5_mem mem_left_track_37
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_12_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_5_sram)
     );
     mux_tree_tapbuf_size4_mem mem_left_track_45
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_4_sram)
     );
     mux_tree_tapbuf_size5_mem mem_left_track_5
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_4_sram)
     );
     mux_tree_tapbuf_size4_mem mem_left_track_53
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_5_sram)
     );
     mux_tree_tapbuf_size6_mem mem_left_track_7
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_9_sram)
     );
     mux_tree_tapbuf_size6_mem mem_right_track_0
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_3_sram)
     );
     mux_tree_tapbuf_size7_mem mem_right_track_10
     (
         .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size7_2_sram)
     );
     mux_tree_tapbuf_size6_mem mem_right_track_12
     (
         .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_6_sram)
     );
     mux_tree_tapbuf_size6_mem mem_right_track_2
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_4_sram)
     );
     mux_tree_tapbuf_size6_mem mem_right_track_20
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_7_sram)
     );
     mux_tree_tapbuf_size6_mem mem_right_track_28
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_8_sram)
     );
     mux_tree_tapbuf_size5_mem mem_right_track_36
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_2_sram)
     );
     mux_tree_tapbuf_size6_mem mem_right_track_4
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_5_sram)
     );
     mux_tree_tapbuf_size3_mem mem_right_track_44
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_5_sram)
     );
     mux_tree_tapbuf_size3_mem mem_right_track_52
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_6_sram)
     );
     mux_tree_tapbuf_size7_mem mem_right_track_6
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size7_1_sram)
     );
     mux_tree_tapbuf_size7_mem mem_top_track_0
     (
         .ccff_head(ccff_head),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size7_0_sram)
     );
     mux_tree_tapbuf_size5_mem mem_top_track_10
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_1_sram)
     );
     mux_tree_tapbuf_size4_mem mem_top_track_12
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_0_sram)
     );
     mux_tree_tapbuf_size4_mem mem_top_track_14
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_1_sram)
     );
     mux_tree_tapbuf_size4_mem mem_top_track_16
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_2_sram)
     );
     mux_tree_tapbuf_size4_mem mem_top_track_18
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_3_sram)
     );
     mux_tree_tapbuf_size6_mem mem_top_track_2
     (
         .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_0_sram)
     );
     mux_tree_tapbuf_size3_mem mem_top_track_20
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_0_sram)
     );
     mux_tree_tapbuf_size3_mem mem_top_track_22
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_1_sram)
     );
     mux_tree_tapbuf_size3_mem mem_top_track_24
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_2_sram)
     );
     mux_tree_tapbuf_size3_mem mem_top_track_26
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_3_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_28
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_0_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_30
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_1_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_32
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_2_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_34
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_3_sram)
     );
     mux_tree_tapbuf_size3_mem mem_top_track_36
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_4_sram)
     );
     mux_tree_tapbuf_size5_mem mem_top_track_4
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_0_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_40
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_4_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_42
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_5_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_44
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_6_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_46
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_7_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_48
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_8_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_50
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_9_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_58
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_10_sram)
     );
     mux_tree_tapbuf_size6_mem mem_top_track_6
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_1_sram)
     );
     mux_tree_tapbuf_size6_mem mem_top_track_8
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_2_sram)
     );
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__1_.v
index 0092db3..501d7a1 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__1_.v
@@ -23,8 +23,8 @@ module sb_1__1_
     left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_,
     left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_,
     left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_,
-    pReset,
     prog_clk,
+    prog_reset,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
@@ -69,8 +69,8 @@ module sb_1__1_
     input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_;
     input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_;
     input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@@ -250,8 +250,8 @@ module sb_1__1_
     wire mux_tree_tapbuf_size9_mem_1_ccff_tail;
     wire mux_tree_tapbuf_size9_mem_2_ccff_tail;
     wire mux_tree_tapbuf_size9_mem_3_ccff_tail;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@@ -348,352 +348,352 @@ assign chany_bottom_out[17] = chany_top_in[16];
     mux_tree_tapbuf_size11_mem mem_bottom_track_1
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size11_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size11_4_sram)
     );
     mux_tree_tapbuf_size12_mem mem_bottom_track_11
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_5_sram)
     );
     mux_tree_tapbuf_size10_mem mem_bottom_track_13
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_7_sram)
     );
     mux_tree_tapbuf_size10_mem mem_bottom_track_21
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_8_sram)
     );
     mux_tree_tapbuf_size9_mem mem_bottom_track_29
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size9_2_sram)
     );
     mux_tree_tapbuf_size11_mem mem_bottom_track_3
     (
         .ccff_head(mux_tree_tapbuf_size11_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size11_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size11_5_sram)
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_37
     (
         .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_6_sram)
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_45
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_7_sram)
     );
     mux_tree_tapbuf_size10_mem mem_bottom_track_5
     (
         .ccff_head(mux_tree_tapbuf_size11_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_6_sram)
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_53
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_8_sram)
     );
     mux_tree_tapbuf_size12_mem mem_bottom_track_7
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_4_sram)
     );
     mux_tree_tapbuf_size11_mem mem_left_track_1
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size11_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size11_6_sram)
     );
     mux_tree_tapbuf_size12_mem mem_left_track_11
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_7_sram)
     );
     mux_tree_tapbuf_size10_mem mem_left_track_13
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_10_sram)
     );
     mux_tree_tapbuf_size10_mem mem_left_track_21
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_11_sram)
     );
     mux_tree_tapbuf_size9_mem mem_left_track_29
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size9_3_sram)
     );
     mux_tree_tapbuf_size11_mem mem_left_track_3
     (
         .ccff_head(mux_tree_tapbuf_size11_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size11_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size11_7_sram)
     );
     mux_tree_tapbuf_size6_mem mem_left_track_37
     (
         .ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_9_sram)
     );
     mux_tree_tapbuf_size6_mem mem_left_track_45
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_10_sram)
     );
     mux_tree_tapbuf_size10_mem mem_left_track_5
     (
         .ccff_head(mux_tree_tapbuf_size11_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_9_sram)
     );
     mux_tree_tapbuf_size6_mem mem_left_track_53
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_11_sram)
     );
     mux_tree_tapbuf_size12_mem mem_left_track_7
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_6_sram)
     );
     mux_tree_tapbuf_size11_mem mem_right_track_0
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size11_2_sram)
     );
     mux_tree_tapbuf_size12_mem mem_right_track_10
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_3_sram)
     );
     mux_tree_tapbuf_size10_mem mem_right_track_12
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_4_sram)
     );
     mux_tree_tapbuf_size11_mem mem_right_track_2
     (
         .ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size11_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size11_3_sram)
     );
     mux_tree_tapbuf_size10_mem mem_right_track_20
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_5_sram)
     );
     mux_tree_tapbuf_size9_mem mem_right_track_28
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size9_1_sram)
     );
     mux_tree_tapbuf_size6_mem mem_right_track_36
     (
         .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_3_sram)
     );
     mux_tree_tapbuf_size10_mem mem_right_track_4
     (
         .ccff_head(mux_tree_tapbuf_size11_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_3_sram)
     );
     mux_tree_tapbuf_size6_mem mem_right_track_44
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_4_sram)
     );
     mux_tree_tapbuf_size6_mem mem_right_track_52
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_5_sram)
     );
     mux_tree_tapbuf_size12_mem mem_right_track_6
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_2_sram)
     );
     mux_tree_tapbuf_size11_mem mem_top_track_0
     (
         .ccff_head(ccff_head),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size11_0_sram)
     );
     mux_tree_tapbuf_size12_mem mem_top_track_10
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_1_sram)
     );
     mux_tree_tapbuf_size10_mem mem_top_track_12
     (
         .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_1_sram)
     );
     mux_tree_tapbuf_size11_mem mem_top_track_2
     (
         .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size11_1_sram)
     );
     mux_tree_tapbuf_size10_mem mem_top_track_20
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_2_sram)
     );
     mux_tree_tapbuf_size9_mem mem_top_track_28
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size9_0_sram)
     );
     mux_tree_tapbuf_size6_mem mem_top_track_36
     (
         .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_0_sram)
     );
     mux_tree_tapbuf_size10_mem mem_top_track_4
     (
         .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_0_sram)
     );
     mux_tree_tapbuf_size6_mem mem_top_track_44
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_1_sram)
     );
     mux_tree_tapbuf_size6_mem mem_top_track_52
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_2_sram)
     );
     mux_tree_tapbuf_size12_mem mem_top_track_6
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size12_0_sram)
     );
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__8_.v
index 1826c3c..e065b0e 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__8_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_1__8_.v
@@ -26,8 +26,8 @@ module sb_1__8_
     left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
     left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
     left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
-    pReset,
     prog_clk,
+    prog_reset,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
@@ -70,8 +70,8 @@ module sb_1__8_
     input left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
     input left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
     input left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@@ -260,8 +260,8 @@ module sb_1__8_
     wire mux_tree_tapbuf_size9_mem_0_ccff_tail;
     wire mux_tree_tapbuf_size9_mem_1_ccff_tail;
     wire mux_tree_tapbuf_size9_mem_2_ccff_tail;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@@ -320,384 +320,384 @@ assign chanx_left_out[13] = chanx_right_in[12];
     mux_tree_tapbuf_size6_mem mem_bottom_track_1
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_2_sram)
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_11
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_2_sram)
     );
     mux_tree_tapbuf_size4_mem mem_bottom_track_13
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_0_sram)
     );
     mux_tree_tapbuf_size4_mem mem_bottom_track_15
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_1_sram)
     );
     mux_tree_tapbuf_size4_mem mem_bottom_track_17
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_2_sram)
     );
     mux_tree_tapbuf_size4_mem mem_bottom_track_19
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_3_sram)
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_21
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_0_sram)
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_23
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_1_sram)
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_25
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_2_sram)
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_27
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_3_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_29
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_0_sram)
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_3
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_3_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_31
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_1_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_33
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_2_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_35
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_3_sram)
     );
     mux_tree_tapbuf_size4_mem mem_bottom_track_37
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_4_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_39
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_4_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_41
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_5_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_43
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_6_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_45
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_7_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_47
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_8_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_49
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_9_sram)
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_5
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_1_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_51
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_10_sram)
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_7
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_4_sram)
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_9
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_5_sram)
     );
     mux_tree_tapbuf_size8_mem mem_left_track_1
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size8_2_sram)
     );
     mux_tree_tapbuf_size11_mem mem_left_track_11
     (
         .ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size11_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size11_3_sram)
     );
     mux_tree_tapbuf_size7_mem mem_left_track_13
     (
         .ccff_head(mux_tree_tapbuf_size11_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size7_3_sram)
     );
     mux_tree_tapbuf_size7_mem mem_left_track_21
     (
         .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size7_4_sram)
     );
     mux_tree_tapbuf_size7_mem mem_left_track_29
     (
         .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size7_5_sram)
     );
     mux_tree_tapbuf_size9_mem mem_left_track_3
     (
         .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size9_1_sram)
     );
     mux_tree_tapbuf_size6_mem mem_left_track_37
     (
         .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_6_sram)
     );
     mux_tree_tapbuf_size5_mem mem_left_track_45
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_3_sram)
     );
     mux_tree_tapbuf_size9_mem mem_left_track_5
     (
         .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size9_2_sram)
     );
     mux_tree_tapbuf_size5_mem mem_left_track_53
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_4_sram)
     );
     mux_tree_tapbuf_size11_mem mem_left_track_7
     (
         .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size11_2_sram)
     );
     mux_tree_tapbuf_size8_mem mem_right_track_0
     (
         .ccff_head(ccff_head),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size8_0_sram)
     );
     mux_tree_tapbuf_size11_mem mem_right_track_10
     (
         .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size11_1_sram)
     );
     mux_tree_tapbuf_size7_mem mem_right_track_12
     (
         .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size7_0_sram)
     );
     mux_tree_tapbuf_size8_mem mem_right_track_2
     (
         .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size8_1_sram)
     );
     mux_tree_tapbuf_size7_mem mem_right_track_20
     (
         .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size7_1_sram)
     );
     mux_tree_tapbuf_size7_mem mem_right_track_28
     (
         .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size7_2_sram)
     );
     mux_tree_tapbuf_size6_mem mem_right_track_36
     (
         .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_0_sram)
     );
     mux_tree_tapbuf_size9_mem mem_right_track_4
     (
         .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size9_0_sram)
     );
     mux_tree_tapbuf_size6_mem mem_right_track_44
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_1_sram)
     );
     mux_tree_tapbuf_size5_mem mem_right_track_52
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_0_sram)
     );
     mux_tree_tapbuf_size11_mem mem_right_track_6
     (
         .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size11_0_sram)
     );
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__0_.v
index 1ac66eb..a5c054f 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__0_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__0_.v
@@ -9,8 +9,8 @@ module sb_8__0_
     left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
     left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
     left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
-    pReset,
     prog_clk,
+    prog_reset,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
@@ -35,8 +35,8 @@ module sb_8__0_
     input left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
     input left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
     input left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@@ -194,8 +194,8 @@ module sb_8__0_
     wire mux_tree_tapbuf_size5_mem_3_ccff_tail;
     wire mux_tree_tapbuf_size5_mem_4_ccff_tail;
     wire mux_tree_tapbuf_size5_mem_5_ccff_tail;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@@ -228,352 +228,352 @@ assign chanx_left_out[12] = chany_top_in[18];
     mux_tree_tapbuf_size3_mem mem_left_track_1
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_8_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_11
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_15_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_13
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_16_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_15
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_17_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_17
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_18_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_19
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_19_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_29
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_20_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_3
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_12_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_31
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_21_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_33
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_22_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_35
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_23_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_45
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_24_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_47
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_25_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_49
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_26_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_5
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_13_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_51
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_27_sram)
     );
     mux_tree_tapbuf_size3_mem mem_left_track_7
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_9_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_9
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_14_sram)
     );
     mux_tree_tapbuf_size5_mem mem_top_track_0
     (
         .ccff_head(ccff_head),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_0_sram)
     );
     mux_tree_tapbuf_size5_mem mem_top_track_10
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_5_sram)
     );
     mux_tree_tapbuf_size3_mem mem_top_track_12
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_0_sram)
     );
     mux_tree_tapbuf_size3_mem mem_top_track_14
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_1_sram)
     );
     mux_tree_tapbuf_size3_mem mem_top_track_16
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_2_sram)
     );
     mux_tree_tapbuf_size3_mem mem_top_track_18
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_3_sram)
     );
     mux_tree_tapbuf_size5_mem mem_top_track_2
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_1_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_20
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_0_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_22
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_1_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_24
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_2_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_26
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_3_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_28
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_4_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_30
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_5_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_32
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_6_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_34
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_7_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_36
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_8_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_38
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_9_sram)
     );
     mux_tree_tapbuf_size5_mem mem_top_track_4
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_2_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_40
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_10_sram)
     );
     mux_tree_tapbuf_size2_mem mem_top_track_42
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_11_sram)
     );
     mux_tree_tapbuf_size3_mem mem_top_track_44
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_4_sram)
     );
     mux_tree_tapbuf_size3_mem mem_top_track_46
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_5_sram)
     );
     mux_tree_tapbuf_size3_mem mem_top_track_48
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_6_sram)
     );
     mux_tree_tapbuf_size3_mem mem_top_track_50
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_7_sram)
     );
     mux_tree_tapbuf_size5_mem mem_top_track_6
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_3_sram)
     );
     mux_tree_tapbuf_size5_mem mem_top_track_8
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_4_sram)
     );
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__1_.v
index 1350585..3eab785 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__1_.v
@@ -26,8 +26,8 @@ module sb_8__1_
     left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_,
     left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_,
     left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_,
-    pReset,
     prog_clk,
+    prog_reset,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
@@ -70,8 +70,8 @@ module sb_8__1_
     input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_;
     input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_;
     input left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@@ -263,8 +263,8 @@ module sb_8__1_
     wire mux_tree_tapbuf_size9_mem_1_ccff_tail;
     wire mux_tree_tapbuf_size9_mem_2_ccff_tail;
     wire mux_tree_tapbuf_size9_mem_3_ccff_tail;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@@ -322,392 +322,392 @@ assign chany_bottom_out[16] = chany_top_in[15];
     mux_tree_tapbuf_size9_mem mem_bottom_track_1
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size9_1_sram)
     );
     mux_tree_tapbuf_size11_mem mem_bottom_track_11
     (
         .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size11_2_sram)
     );
     mux_tree_tapbuf_size7_mem mem_bottom_track_13
     (
         .ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size7_3_sram)
     );
     mux_tree_tapbuf_size7_mem mem_bottom_track_21
     (
         .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size7_4_sram)
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_29
     (
         .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_3_sram)
     );
     mux_tree_tapbuf_size9_mem mem_bottom_track_3
     (
         .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size9_2_sram)
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_37
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_0_sram)
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_45
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_1_sram)
     );
     mux_tree_tapbuf_size9_mem mem_bottom_track_5
     (
         .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size9_3_sram)
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_53
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_4_sram)
     );
     mux_tree_tapbuf_size11_mem mem_bottom_track_7
     (
         .ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size11_1_sram)
     );
     mux_tree_tapbuf_size6_mem mem_left_track_1
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_5_sram)
     );
     mux_tree_tapbuf_size5_mem mem_left_track_11
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_3_sram)
     );
     mux_tree_tapbuf_size4_mem mem_left_track_13
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_0_sram)
     );
     mux_tree_tapbuf_size4_mem mem_left_track_15
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_1_sram)
     );
     mux_tree_tapbuf_size4_mem mem_left_track_17
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_2_sram)
     );
     mux_tree_tapbuf_size4_mem mem_left_track_19
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_3_sram)
     );
     mux_tree_tapbuf_size4_mem mem_left_track_21
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_4_sram)
     );
     mux_tree_tapbuf_size4_mem mem_left_track_23
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size4_5_sram)
     );
     mux_tree_tapbuf_size3_mem mem_left_track_25
     (
         .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_0_sram)
     );
     mux_tree_tapbuf_size3_mem mem_left_track_27
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_1_sram)
     );
     mux_tree_tapbuf_size3_mem mem_left_track_29
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_2_sram)
     );
     mux_tree_tapbuf_size6_mem mem_left_track_3
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_6_sram)
     );
     mux_tree_tapbuf_size3_mem mem_left_track_31
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_3_sram)
     );
     mux_tree_tapbuf_size3_mem mem_left_track_33
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_4_sram)
     );
     mux_tree_tapbuf_size3_mem mem_left_track_35
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_5_sram)
     );
     mux_tree_tapbuf_size3_mem mem_left_track_37
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_6_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_41
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_0_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_45
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_1_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_47
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_2_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_49
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_3_sram)
     );
     mux_tree_tapbuf_size5_mem mem_left_track_5
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_2_sram)
     );
     mux_tree_tapbuf_size3_mem mem_left_track_51
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_7_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_53
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_4_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_55
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_5_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_57
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_6_sram)
     );
     mux_tree_tapbuf_size6_mem mem_left_track_7
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_7_sram)
     );
     mux_tree_tapbuf_size6_mem mem_left_track_9
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_8_sram)
     );
     mux_tree_tapbuf_size9_mem mem_top_track_0
     (
         .ccff_head(ccff_head),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size9_0_sram)
     );
     mux_tree_tapbuf_size11_mem mem_top_track_10
     (
         .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size11_0_sram)
     );
     mux_tree_tapbuf_size7_mem mem_top_track_12
     (
         .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size7_0_sram)
     );
     mux_tree_tapbuf_size8_mem mem_top_track_2
     (
         .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size8_0_sram)
     );
     mux_tree_tapbuf_size7_mem mem_top_track_20
     (
         .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size7_1_sram)
     );
     mux_tree_tapbuf_size7_mem mem_top_track_28
     (
         .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size7_2_sram)
     );
     mux_tree_tapbuf_size6_mem mem_top_track_36
     (
         .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_0_sram)
     );
     mux_tree_tapbuf_size8_mem mem_top_track_4
     (
         .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size8_1_sram)
     );
     mux_tree_tapbuf_size6_mem mem_top_track_44
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_1_sram)
     );
     mux_tree_tapbuf_size6_mem mem_top_track_52
     (
         .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size6_2_sram)
     );
     mux_tree_tapbuf_size10_mem mem_top_track_6
     (
         .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size10_0_sram)
     );
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__8_.v
index 4d3b2cf..72a8021 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__8_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/submodules/sb_8__8_.v
@@ -29,8 +29,8 @@ module sb_8__8_
     left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
     left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
     left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
-    pReset,
     prog_clk,
+    prog_reset,
     ccff_tail,
     chanx_left_out,
     chany_bottom_out
@@ -63,8 +63,8 @@ module sb_8__8_
     input left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
     input left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
     input left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     output ccff_tail;
     output [0:29]chanx_left_out;
     output [0:29]chany_bottom_out;
@@ -266,8 +266,8 @@ module sb_8__8_
     wire mux_tree_tapbuf_size5_mem_7_ccff_tail;
     wire mux_tree_tapbuf_size5_mem_8_ccff_tail;
     wire mux_tree_tapbuf_size5_mem_9_ccff_tail;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
 
 assign chany_bottom_out[18] = chanx_left_in[19];
 assign chany_bottom_out[19] = chanx_left_in[20];
@@ -276,448 +276,448 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     mux_tree_tapbuf_size5_mem mem_bottom_track_1
     (
         .ccff_head(ccff_head),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_0_sram)
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_11
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_5_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_13
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_0_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_15
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_1_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_17
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_2_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_19
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_3_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_21
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_4_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_23
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_5_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_25
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_6_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_27
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_7_sram)
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_29
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_0_sram)
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_3
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_1_sram)
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_31
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_1_sram)
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_33
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_2_sram)
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_35
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_3_sram)
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_45
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_4_sram)
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_47
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_5_sram)
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_49
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_6_sram)
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_5
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_2_sram)
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_51
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_7_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_53
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_8_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_55
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_9_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_57
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_10_sram)
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_59
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_11_sram)
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_7
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_3_sram)
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_9
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_4_sram)
     );
     mux_tree_tapbuf_size5_mem mem_left_track_1
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_6_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_6_sram)
     );
     mux_tree_tapbuf_size5_mem mem_left_track_11
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_10_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_11_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_11_sram)
     );
     mux_tree_tapbuf_size3_mem mem_left_track_13
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_11_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_8_sram)
     );
     mux_tree_tapbuf_size3_mem mem_left_track_15
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_9_sram)
     );
     mux_tree_tapbuf_size3_mem mem_left_track_17
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_10_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_19
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_12_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_21
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_13_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_23
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_14_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_25
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_15_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_27
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_16_sram)
     );
     mux_tree_tapbuf_size3_mem mem_left_track_29
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_11_sram)
     );
     mux_tree_tapbuf_size5_mem mem_left_track_3
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_6_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_7_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_7_sram)
     );
     mux_tree_tapbuf_size3_mem mem_left_track_31
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_12_sram)
     );
     mux_tree_tapbuf_size3_mem mem_left_track_33
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_13_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_13_sram)
     );
     mux_tree_tapbuf_size3_mem mem_left_track_35
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_13_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_14_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_14_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_37
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_14_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_17_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_39
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_18_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_41
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_19_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_43
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_20_sram)
     );
     mux_tree_tapbuf_size3_mem mem_left_track_45
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_15_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_15_sram)
     );
     mux_tree_tapbuf_size3_mem mem_left_track_47
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_15_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_16_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_16_sram)
     );
     mux_tree_tapbuf_size3_mem mem_left_track_49
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_16_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size3_mem_17_ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_17_sram)
     );
     mux_tree_tapbuf_size5_mem mem_left_track_5
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_7_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_8_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_8_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_51
     (
         .ccff_head(mux_tree_tapbuf_size3_mem_17_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_21_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_53
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_22_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_55
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_23_sram)
     );
     mux_tree_tapbuf_size2_mem mem_left_track_57
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
         .mem_out(mux_tree_tapbuf_size2_24_sram)
     );
     mux_tree_tapbuf_size3_mem mem_left_track_59
     (
         .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
         .mem_out(mux_tree_tapbuf_size3_18_sram)
     );
     mux_tree_tapbuf_size5_mem mem_left_track_7
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_8_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_9_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_9_sram)
     );
     mux_tree_tapbuf_size5_mem mem_left_track_9
     (
         .ccff_head(mux_tree_tapbuf_size5_mem_9_ccff_tail),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(mux_tree_tapbuf_size5_mem_10_ccff_tail),
         .mem_out(mux_tree_tapbuf_size5_10_sram)
     );
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_left_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_left_tile.v
index f03df8a..9521428 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_left_tile.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_left_tile.v
@@ -5,8 +5,8 @@ module bottom_left_tile
     ccff_head,
     chanx_right_in,
     chany_top_in,
-    pReset,
     prog_clk,
+    prog_reset,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
     right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
     right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
@@ -23,8 +23,8 @@ module bottom_left_tile
     input ccff_head;
     input [29:0]chanx_right_in;
     input [29:0]chany_top_in;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
     input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
     input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
@@ -43,8 +43,8 @@ module bottom_left_tile
     wire [29:0]chanx_right_out;
     wire [29:0]chany_top_in;
     wire [29:0]chany_top_out;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
     wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
     wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
@@ -59,8 +59,8 @@ module bottom_left_tile
         .ccff_head(ccff_head),
         .chanx_right_in(chanx_right_in),
         .chany_top_in(chany_top_in),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_right_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_right_tile.v
index ca20c14..5e7e273 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_right_tile.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_right_tile.v
@@ -2,14 +2,14 @@
 //netlist name: FPGA88_SOFA_A
 module bottom_right_tile
 (
-    IO_ISOL_N,
     ccff_head,
     ccff_head_1,
     chanx_left_in,
     chany_top_in,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    pReset,
+    gfpga_pad_io_soc_in,
+    isol_n,
     prog_clk,
+    prog_reset,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
@@ -26,22 +26,22 @@ module bottom_right_tile
     ccff_tail_0,
     chanx_left_out,
     chany_top_out,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    gfpga_pad_io_soc_dir,
+    gfpga_pad_io_soc_out,
     top_width_0_height_0_subtile_0__pin_inpad_0_,
     top_width_0_height_0_subtile_1__pin_inpad_0_,
     top_width_0_height_0_subtile_2__pin_inpad_0_,
     top_width_0_height_0_subtile_3__pin_inpad_0_
 );
 
-    input IO_ISOL_N;
     input ccff_head;
     input ccff_head_1;
     input [29:0]chanx_left_in;
     input [29:0]chany_top_in;
-    input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    input pReset;
+    input [3:0]gfpga_pad_io_soc_in;
+    input isol_n;
     input prog_clk;
+    input prog_reset;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@@ -58,14 +58,13 @@ module bottom_right_tile
     output ccff_tail_0;
     output [29:0]chanx_left_out;
     output [29:0]chany_top_out;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output [3:0]gfpga_pad_io_soc_dir;
+    output [3:0]gfpga_pad_io_soc_out;
     output top_width_0_height_0_subtile_0__pin_inpad_0_;
     output top_width_0_height_0_subtile_1__pin_inpad_0_;
     output top_width_0_height_0_subtile_2__pin_inpad_0_;
     output top_width_0_height_0_subtile_3__pin_inpad_0_;
 
-    wire IO_ISOL_N;
     wire ccff_head;
     wire ccff_head_1;
     wire ccff_tail;
@@ -77,11 +76,12 @@ module bottom_right_tile
     wire [29:0]chanx_right_out;
     wire [29:0]chany_top_in;
     wire [29:0]chany_top_out;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    wire pReset;
+    wire [3:0]gfpga_pad_io_soc_dir;
+    wire [3:0]gfpga_pad_io_soc_in;
+    wire [3:0]gfpga_pad_io_soc_out;
+    wire isol_n;
     wire prog_clk;
+    wire prog_reset;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@@ -101,20 +101,20 @@ module bottom_right_tile
 
     cbx_1__0_ cbx_8__0_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(ccff_head),
         .ccff_head_0(ccff_tail_1),
         .chanx_left_in(chanx_left_in),
         .chanx_right_in(chanx_left_out_0),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
         .ccff_tail_0(ccff_tail_0),
         .chanx_left_out(chanx_left_out),
         .chanx_right_out(chanx_right_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
         .top_width_0_height_0_subtile_0__pin_inpad_0_(top_width_0_height_0_subtile_0__pin_inpad_0_),
         .top_width_0_height_0_subtile_1__pin_inpad_0_(top_width_0_height_0_subtile_1__pin_inpad_0_),
         .top_width_0_height_0_subtile_2__pin_inpad_0_(top_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -129,8 +129,8 @@ module bottom_right_tile
         .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(top_width_0_height_0_subtile_1__pin_inpad_0_),
         .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(top_width_0_height_0_subtile_2__pin_inpad_0_),
         .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(top_width_0_height_0_subtile_3__pin_inpad_0_),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_tile.v
index 987bd4e..58e056f 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_tile.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/bottom_tile.v
@@ -2,15 +2,15 @@
 //netlist name: FPGA88_SOFA_A
 module bottom_tile
 (
-    IO_ISOL_N,
     ccff_head,
     ccff_head_1,
     chanx_left_in,
     chanx_right_in_0,
     chany_top_in,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    pReset,
+    gfpga_pad_io_soc_in,
+    isol_n,
     prog_clk,
+    prog_reset,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
     right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
     right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
@@ -28,23 +28,23 @@ module bottom_tile
     chanx_left_out,
     chanx_right_out_0,
     chany_top_out,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    gfpga_pad_io_soc_dir,
+    gfpga_pad_io_soc_out,
     top_width_0_height_0_subtile_0__pin_inpad_0_,
     top_width_0_height_0_subtile_1__pin_inpad_0_,
     top_width_0_height_0_subtile_2__pin_inpad_0_,
     top_width_0_height_0_subtile_3__pin_inpad_0_
 );
 
-    input IO_ISOL_N;
     input ccff_head;
     input ccff_head_1;
     input [29:0]chanx_left_in;
     input [29:0]chanx_right_in_0;
     input [29:0]chany_top_in;
-    input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    input pReset;
+    input [3:0]gfpga_pad_io_soc_in;
+    input isol_n;
     input prog_clk;
+    input prog_reset;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
     input right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
     input right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
@@ -62,14 +62,13 @@ module bottom_tile
     output [29:0]chanx_left_out;
     output [29:0]chanx_right_out_0;
     output [29:0]chany_top_out;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output [3:0]gfpga_pad_io_soc_dir;
+    output [3:0]gfpga_pad_io_soc_out;
     output top_width_0_height_0_subtile_0__pin_inpad_0_;
     output top_width_0_height_0_subtile_1__pin_inpad_0_;
     output top_width_0_height_0_subtile_2__pin_inpad_0_;
     output top_width_0_height_0_subtile_3__pin_inpad_0_;
 
-    wire IO_ISOL_N;
     wire ccff_head;
     wire ccff_head_1;
     wire ccff_tail;
@@ -83,11 +82,12 @@ module bottom_tile
     wire [29:0]chanx_right_out_0;
     wire [29:0]chany_top_in;
     wire [29:0]chany_top_out;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    wire pReset;
+    wire [3:0]gfpga_pad_io_soc_dir;
+    wire [3:0]gfpga_pad_io_soc_in;
+    wire [3:0]gfpga_pad_io_soc_out;
+    wire isol_n;
     wire prog_clk;
+    wire prog_reset;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
     wire right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
     wire right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
@@ -107,20 +107,20 @@ module bottom_tile
 
     cbx_1__0_ cbx_1__0_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(ccff_head),
         .ccff_head_0(ccff_tail_1),
         .chanx_left_in(chanx_left_in),
         .chanx_right_in(chanx_left_out_0),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
         .ccff_tail_0(ccff_tail_0),
         .chanx_left_out(chanx_left_out),
         .chanx_right_out(chanx_right_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
         .top_width_0_height_0_subtile_0__pin_inpad_0_(top_width_0_height_0_subtile_0__pin_inpad_0_),
         .top_width_0_height_0_subtile_1__pin_inpad_0_(top_width_0_height_0_subtile_1__pin_inpad_0_),
         .top_width_0_height_0_subtile_2__pin_inpad_0_(top_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -136,8 +136,8 @@ module bottom_tile
         .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(top_width_0_height_0_subtile_1__pin_inpad_0_),
         .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(top_width_0_height_0_subtile_2__pin_inpad_0_),
         .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(top_width_0_height_0_subtile_3__pin_inpad_0_),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/left_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/left_tile.v
index 7666f02..8564646 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/left_tile.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/left_tile.v
@@ -2,15 +2,15 @@
 //netlist name: FPGA88_SOFA_A
 module left_tile
 (
-    IO_ISOL_N,
     ccff_head,
     ccff_head_0,
     chanx_right_in,
     chany_bottom_in,
     chany_top_in_0,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    pReset,
+    gfpga_pad_io_soc_in,
+    isol_n,
     prog_clk,
+    prog_reset,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
@@ -28,23 +28,23 @@ module left_tile
     chanx_right_out,
     chany_bottom_out,
     chany_top_out_0,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    gfpga_pad_io_soc_dir,
+    gfpga_pad_io_soc_out,
     right_width_0_height_0_subtile_0__pin_inpad_0_,
     right_width_0_height_0_subtile_1__pin_inpad_0_,
     right_width_0_height_0_subtile_2__pin_inpad_0_,
     right_width_0_height_0_subtile_3__pin_inpad_0_
 );
 
-    input IO_ISOL_N;
     input ccff_head;
     input ccff_head_0;
     input [29:0]chanx_right_in;
     input [29:0]chany_bottom_in;
     input [29:0]chany_top_in_0;
-    input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    input pReset;
+    input [3:0]gfpga_pad_io_soc_in;
+    input isol_n;
     input prog_clk;
+    input prog_reset;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@@ -62,14 +62,13 @@ module left_tile
     output [29:0]chanx_right_out;
     output [29:0]chany_bottom_out;
     output [29:0]chany_top_out_0;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output [3:0]gfpga_pad_io_soc_dir;
+    output [3:0]gfpga_pad_io_soc_out;
     output right_width_0_height_0_subtile_0__pin_inpad_0_;
     output right_width_0_height_0_subtile_1__pin_inpad_0_;
     output right_width_0_height_0_subtile_2__pin_inpad_0_;
     output right_width_0_height_0_subtile_3__pin_inpad_0_;
 
-    wire IO_ISOL_N;
     wire ccff_head;
     wire ccff_head_0;
     wire ccff_tail;
@@ -82,11 +81,12 @@ module left_tile
     wire [29:0]chany_top_in_0;
     wire [29:0]chany_top_out;
     wire [29:0]chany_top_out_0;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    wire pReset;
+    wire [3:0]gfpga_pad_io_soc_dir;
+    wire [3:0]gfpga_pad_io_soc_in;
+    wire [3:0]gfpga_pad_io_soc_out;
+    wire isol_n;
     wire prog_clk;
+    wire prog_reset;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@@ -106,18 +106,18 @@ module left_tile
 
     cby_0__1_ cby_0__1_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head_0(ccff_head_0),
         .chany_bottom_in(chany_bottom_in),
         .chany_top_in(chany_bottom_out_0),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail),
         .chany_bottom_out(chany_bottom_out),
         .chany_top_out(chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
         .right_width_0_height_0_subtile_0__pin_inpad_0_(right_width_0_height_0_subtile_0__pin_inpad_0_),
         .right_width_0_height_0_subtile_1__pin_inpad_0_(right_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_width_0_height_0_subtile_2__pin_inpad_0_(right_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -133,8 +133,8 @@ module left_tile
         .chanx_right_in(chanx_right_in),
         .chany_bottom_in(chany_top_out),
         .chany_top_in(chany_top_in_0),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/right_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/right_tile.v
index 74f8d7a..e2d6009 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/right_tile.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/right_tile.v
@@ -2,19 +2,19 @@
 //netlist name: FPGA88_SOFA_A
 module right_tile
 (
-    IO_ISOL_N,
-    Test_en,
     ccff_head_0_0,
     ccff_head_1,
     ccff_head_2,
     chanx_left_in,
     chany_bottom_in,
     chany_top_in_0,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
+    gfpga_pad_io_soc_in,
+    isol_n,
     left_width_0_height_0_subtile_0__pin_clk_0_,
     left_width_0_height_0_subtile_0__pin_reset_0_,
-    pReset,
     prog_clk,
+    prog_reset,
+    scan_enable,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
@@ -39,8 +39,8 @@ module right_tile
     chanx_left_out,
     chany_bottom_out,
     chany_top_out_0,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    gfpga_pad_io_soc_dir,
+    gfpga_pad_io_soc_out,
     left_width_0_height_0_subtile_0__pin_inpad_0_,
     left_width_0_height_0_subtile_1__pin_inpad_0_,
     left_width_0_height_0_subtile_2__pin_inpad_0_,
@@ -63,19 +63,19 @@ module right_tile
     top_width_0_height_0_subtile_0__pin_O_7_
 );
 
-    input IO_ISOL_N;
-    input Test_en;
     input ccff_head_0_0;
     input ccff_head_1;
     input ccff_head_2;
     input [29:0]chanx_left_in;
     input [29:0]chany_bottom_in;
     input [29:0]chany_top_in_0;
-    input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    input [3:0]gfpga_pad_io_soc_in;
+    input isol_n;
     input left_width_0_height_0_subtile_0__pin_clk_0_;
     input left_width_0_height_0_subtile_0__pin_reset_0_;
-    input pReset;
     input prog_clk;
+    input prog_reset;
+    input scan_enable;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@@ -100,8 +100,8 @@ module right_tile
     output [29:0]chanx_left_out;
     output [29:0]chany_bottom_out;
     output [29:0]chany_top_out_0;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output [3:0]gfpga_pad_io_soc_dir;
+    output [3:0]gfpga_pad_io_soc_out;
     output left_width_0_height_0_subtile_0__pin_inpad_0_;
     output left_width_0_height_0_subtile_1__pin_inpad_0_;
     output left_width_0_height_0_subtile_2__pin_inpad_0_;
@@ -123,8 +123,6 @@ module right_tile
     output top_width_0_height_0_subtile_0__pin_O_6_;
     output top_width_0_height_0_subtile_0__pin_O_7_;
 
-    wire IO_ISOL_N;
-    wire Test_en;
     wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
     wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
     wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
@@ -162,9 +160,10 @@ module right_tile
     wire [29:0]chany_top_in_0;
     wire [29:0]chany_top_out;
     wire [29:0]chany_top_out_0;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    wire [3:0]gfpga_pad_io_soc_dir;
+    wire [3:0]gfpga_pad_io_soc_in;
+    wire [3:0]gfpga_pad_io_soc_out;
+    wire isol_n;
     wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
     wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
     wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
@@ -187,8 +186,8 @@ module right_tile
     wire left_width_0_height_0_subtile_1__pin_inpad_0_;
     wire left_width_0_height_0_subtile_2__pin_inpad_0_;
     wire left_width_0_height_0_subtile_3__pin_inpad_0_;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
     wire right_width_0_height_0_subtile_0__pin_O_10_;
     wire right_width_0_height_0_subtile_0__pin_O_11_;
     wire right_width_0_height_0_subtile_0__pin_O_12_;
@@ -197,6 +196,7 @@ module right_tile
     wire right_width_0_height_0_subtile_0__pin_O_15_;
     wire right_width_0_height_0_subtile_0__pin_O_8_;
     wire right_width_0_height_0_subtile_0__pin_O_9_;
+    wire scan_enable;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@@ -226,8 +226,8 @@ module right_tile
         .ccff_head(ccff_tail_2),
         .chanx_left_in(chanx_left_in),
         .chanx_right_in(chanx_left_out_0),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -250,20 +250,20 @@ module right_tile
     );
     cby_8__1_ cby_8__1_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(ccff_head_1),
         .ccff_head_0(ccff_head_0_0),
         .chany_bottom_in(chany_bottom_in),
         .chany_top_in(chany_bottom_out_0),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail_1),
         .ccff_tail_0(ccff_tail_0_0),
         .chany_bottom_out(chany_bottom_out),
         .chany_top_out(chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
         .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
         .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
         .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),
@@ -287,12 +287,11 @@ module right_tile
     );
     grid_clb grid_clb_8__1_
     (
-        .Test_en(Test_en),
         .ccff_head(ccff_tail_0_0),
         .left_width_0_height_0_subtile_0__pin_clk_0_(left_width_0_height_0_subtile_0__pin_clk_0_),
         .left_width_0_height_0_subtile_0__pin_reset_0_(left_width_0_height_0_subtile_0__pin_reset_0_),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
         .right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
         .right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),
@@ -309,6 +308,7 @@ module right_tile
         .right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -375,8 +375,8 @@ module right_tile
         .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(top_width_0_height_0_subtile_0__pin_O_5_),
         .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(top_width_0_height_0_subtile_0__pin_O_6_),
         .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(top_width_0_height_0_subtile_0__pin_O_7_),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_(top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/tile.v
index 622f1f0..feeca0c 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/tile.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/tile.v
@@ -2,7 +2,6 @@
 //netlist name: FPGA88_SOFA_A
 module tile
 (
-    Test_en,
     ccff_head_1,
     ccff_head_2,
     chanx_left_in,
@@ -11,8 +10,8 @@ module tile
     chany_top_in_0,
     left_width_0_height_0_subtile_0__pin_clk_0_,
     left_width_0_height_0_subtile_0__pin_reset_0_,
-    pReset,
     prog_clk,
+    prog_reset,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
@@ -21,6 +20,7 @@ module tile
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_,
+    scan_enable,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_,
@@ -59,7 +59,6 @@ module tile
     top_width_0_height_0_subtile_0__pin_O_7_
 );
 
-    input Test_en;
     input ccff_head_1;
     input ccff_head_2;
     input [29:0]chanx_left_in;
@@ -68,8 +67,8 @@ module tile
     input [29:0]chany_top_in_0;
     input left_width_0_height_0_subtile_0__pin_clk_0_;
     input left_width_0_height_0_subtile_0__pin_reset_0_;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@@ -78,6 +77,7 @@ module tile
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_;
+    input scan_enable;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@@ -115,7 +115,6 @@ module tile
     output top_width_0_height_0_subtile_0__pin_O_6_;
     output top_width_0_height_0_subtile_0__pin_O_7_;
 
-    wire Test_en;
     wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
     wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
     wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
@@ -171,8 +170,8 @@ module tile
     wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
     wire left_width_0_height_0_subtile_0__pin_clk_0_;
     wire left_width_0_height_0_subtile_0__pin_reset_0_;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@@ -189,6 +188,7 @@ module tile
     wire right_width_0_height_0_subtile_0__pin_O_15_;
     wire right_width_0_height_0_subtile_0__pin_O_8_;
     wire right_width_0_height_0_subtile_0__pin_O_9_;
+    wire scan_enable;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_;
@@ -214,8 +214,8 @@ module tile
         .ccff_head(ccff_tail_2),
         .chanx_left_in(chanx_left_in),
         .chanx_right_in(chanx_left_out_0),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -241,8 +241,8 @@ module tile
         .ccff_head(ccff_head_1),
         .chany_bottom_in(chany_bottom_in),
         .chany_top_in(chany_bottom_out_0),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail_1),
         .chany_bottom_out(chany_bottom_out),
         .chany_top_out(chany_top_out),
@@ -265,12 +265,11 @@ module tile
     );
     grid_clb grid_clb_1__1_
     (
-        .Test_en(Test_en),
         .ccff_head(ccff_tail_1),
         .left_width_0_height_0_subtile_0__pin_clk_0_(left_width_0_height_0_subtile_0__pin_clk_0_),
         .left_width_0_height_0_subtile_0__pin_reset_0_(left_width_0_height_0_subtile_0__pin_reset_0_),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
         .right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
         .right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),
@@ -287,6 +286,7 @@ module tile
         .right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -350,8 +350,8 @@ module tile
         .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_(top_width_0_height_0_subtile_0__pin_O_5_),
         .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_(top_width_0_height_0_subtile_0__pin_O_6_),
         .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_(top_width_0_height_0_subtile_0__pin_O_7_),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_left_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_left_tile.v
index bc3bfcd..9fac6ec 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_left_tile.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_left_tile.v
@@ -2,14 +2,14 @@
 //netlist name: FPGA88_SOFA_A
 module top_left_tile
 (
-    IO_ISOL_N,
     ccff_head,
     ccff_head_0,
     chanx_right_in,
     chany_bottom_in_0,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    pReset,
+    gfpga_pad_io_soc_in,
+    isol_n,
     prog_clk,
+    prog_reset,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
@@ -26,22 +26,22 @@ module top_left_tile
     ccff_tail_0,
     chanx_right_out,
     chany_bottom_out_0,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    gfpga_pad_io_soc_dir,
+    gfpga_pad_io_soc_out,
     right_width_0_height_0_subtile_0__pin_inpad_0_,
     right_width_0_height_0_subtile_1__pin_inpad_0_,
     right_width_0_height_0_subtile_2__pin_inpad_0_,
     right_width_0_height_0_subtile_3__pin_inpad_0_
 );
 
-    input IO_ISOL_N;
     input ccff_head;
     input ccff_head_0;
     input [29:0]chanx_right_in;
     input [29:0]chany_bottom_in_0;
-    input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    input pReset;
+    input [3:0]gfpga_pad_io_soc_in;
+    input isol_n;
     input prog_clk;
+    input prog_reset;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@@ -58,14 +58,13 @@ module top_left_tile
     output ccff_tail_0;
     output [29:0]chanx_right_out;
     output [29:0]chany_bottom_out_0;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output [3:0]gfpga_pad_io_soc_dir;
+    output [3:0]gfpga_pad_io_soc_out;
     output right_width_0_height_0_subtile_0__pin_inpad_0_;
     output right_width_0_height_0_subtile_1__pin_inpad_0_;
     output right_width_0_height_0_subtile_2__pin_inpad_0_;
     output right_width_0_height_0_subtile_3__pin_inpad_0_;
 
-    wire IO_ISOL_N;
     wire ccff_head;
     wire ccff_head_0;
     wire ccff_tail;
@@ -76,11 +75,12 @@ module top_left_tile
     wire [29:0]chany_bottom_out;
     wire [29:0]chany_bottom_out_0;
     wire [29:0]chany_top_out;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    wire pReset;
+    wire [3:0]gfpga_pad_io_soc_dir;
+    wire [3:0]gfpga_pad_io_soc_in;
+    wire [3:0]gfpga_pad_io_soc_out;
+    wire isol_n;
     wire prog_clk;
+    wire prog_reset;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@@ -100,18 +100,18 @@ module top_left_tile
 
     cby_0__1_ cby_0__8_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head_0(ccff_head_0),
         .chany_bottom_in(chany_bottom_in_0),
         .chany_top_in(chany_bottom_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail_0),
         .chany_bottom_out(chany_bottom_out_0),
         .chany_top_out(chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
         .right_width_0_height_0_subtile_0__pin_inpad_0_(right_width_0_height_0_subtile_0__pin_inpad_0_),
         .right_width_0_height_0_subtile_1__pin_inpad_0_(right_width_0_height_0_subtile_1__pin_inpad_0_),
         .right_width_0_height_0_subtile_2__pin_inpad_0_(right_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -126,8 +126,8 @@ module top_left_tile
         .ccff_head(ccff_head),
         .chanx_right_in(chanx_right_in),
         .chany_bottom_in(chany_top_out),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_right_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_right_tile.v
index 7a1f8fc..c8d1924 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_right_tile.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_right_tile.v
@@ -2,18 +2,18 @@
 //netlist name: FPGA88_SOFA_A
 module top_right_tile
 (
-    IO_ISOL_N,
-    Test_en,
     ccff_head_0_0,
     ccff_head_1,
     chanx_left_in,
     chany_bottom_in,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN_0,
+    gfpga_pad_io_soc_in,
+    gfpga_pad_io_soc_in_0,
+    isol_n,
     left_width_0_height_0_subtile_0__pin_clk_0_,
     left_width_0_height_0_subtile_0__pin_reset_0_,
-    pReset,
     prog_clk,
+    prog_reset,
+    scan_enable,
     top_width_0_height_0_subtile_0__pin_cin_0_,
     top_width_0_height_0_subtile_0__pin_reg_in_0_,
     top_width_0_height_0_subtile_0__pin_sc_in_0_,
@@ -28,10 +28,10 @@ module top_right_tile
     ccff_tail_0,
     chanx_left_out,
     chany_bottom_out,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR_0,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_0,
+    gfpga_pad_io_soc_dir,
+    gfpga_pad_io_soc_dir_0,
+    gfpga_pad_io_soc_out,
+    gfpga_pad_io_soc_out_0,
     left_width_0_height_0_subtile_0__pin_inpad_0_,
     left_width_0_height_0_subtile_1__pin_inpad_0_,
     left_width_0_height_0_subtile_2__pin_inpad_0_,
@@ -54,18 +54,18 @@ module top_right_tile
     top_width_0_height_0_subtile_0__pin_O_7_
 );
 
-    input IO_ISOL_N;
-    input Test_en;
     input ccff_head_0_0;
     input ccff_head_1;
     input [29:0]chanx_left_in;
     input [29:0]chany_bottom_in;
-    input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN_0;
+    input [3:0]gfpga_pad_io_soc_in;
+    input [3:0]gfpga_pad_io_soc_in_0;
+    input isol_n;
     input left_width_0_height_0_subtile_0__pin_clk_0_;
     input left_width_0_height_0_subtile_0__pin_reset_0_;
-    input pReset;
     input prog_clk;
+    input prog_reset;
+    input scan_enable;
     input top_width_0_height_0_subtile_0__pin_cin_0_;
     input top_width_0_height_0_subtile_0__pin_reg_in_0_;
     input top_width_0_height_0_subtile_0__pin_sc_in_0_;
@@ -80,10 +80,10 @@ module top_right_tile
     output ccff_tail_0;
     output [29:0]chanx_left_out;
     output [29:0]chany_bottom_out;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR_0;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_0;
+    output [3:0]gfpga_pad_io_soc_dir;
+    output [3:0]gfpga_pad_io_soc_dir_0;
+    output [3:0]gfpga_pad_io_soc_out;
+    output [3:0]gfpga_pad_io_soc_out_0;
     output left_width_0_height_0_subtile_0__pin_inpad_0_;
     output left_width_0_height_0_subtile_1__pin_inpad_0_;
     output left_width_0_height_0_subtile_2__pin_inpad_0_;
@@ -105,8 +105,6 @@ module top_right_tile
     output top_width_0_height_0_subtile_0__pin_O_6_;
     output top_width_0_height_0_subtile_0__pin_O_7_;
 
-    wire IO_ISOL_N;
-    wire Test_en;
     wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
     wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
     wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
@@ -145,12 +143,13 @@ module top_right_tile
     wire [29:0]chany_bottom_out;
     wire [29:0]chany_bottom_out_0;
     wire [29:0]chany_top_out;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR_0;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN_0;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_0;
+    wire [3:0]gfpga_pad_io_soc_dir;
+    wire [3:0]gfpga_pad_io_soc_dir_0;
+    wire [3:0]gfpga_pad_io_soc_in;
+    wire [3:0]gfpga_pad_io_soc_in_0;
+    wire [3:0]gfpga_pad_io_soc_out;
+    wire [3:0]gfpga_pad_io_soc_out_0;
+    wire isol_n;
     wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
     wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
     wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
@@ -173,8 +172,8 @@ module top_right_tile
     wire left_width_0_height_0_subtile_1__pin_inpad_0_;
     wire left_width_0_height_0_subtile_2__pin_inpad_0_;
     wire left_width_0_height_0_subtile_3__pin_inpad_0_;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
     wire right_width_0_height_0_subtile_0__pin_O_10_;
     wire right_width_0_height_0_subtile_0__pin_O_11_;
     wire right_width_0_height_0_subtile_0__pin_O_12_;
@@ -183,6 +182,7 @@ module top_right_tile
     wire right_width_0_height_0_subtile_0__pin_O_15_;
     wire right_width_0_height_0_subtile_0__pin_O_8_;
     wire right_width_0_height_0_subtile_0__pin_O_9_;
+    wire scan_enable;
     wire top_width_0_height_0_subtile_0__pin_O_0_;
     wire top_width_0_height_0_subtile_0__pin_O_1_;
     wire top_width_0_height_0_subtile_0__pin_O_2_;
@@ -197,13 +197,13 @@ module top_right_tile
 
     cbx_1__8_ cbx_8__8_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head_0(ccff_tail_2),
         .chanx_left_in(chanx_left_in),
         .chanx_right_in(chanx_left_out_0),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -227,25 +227,25 @@ module top_right_tile
         .ccff_tail(ccff_tail_0),
         .chanx_left_out(chanx_left_out),
         .chanx_right_out(chanx_right_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT)
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out)
     );
     cby_8__1_ cby_8__8_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head(ccff_head_1),
         .ccff_head_0(ccff_head_0_0),
         .chany_bottom_in(chany_bottom_in),
         .chany_top_in(chany_bottom_out_0),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN_0),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in_0),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail_1),
         .ccff_tail_0(ccff_tail_0_0),
         .chany_bottom_out(chany_bottom_out),
         .chany_top_out(chany_top_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR_0),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT_0),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir_0),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out_0),
         .left_grid_right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
         .left_grid_right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
         .left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),
@@ -269,12 +269,11 @@ module top_right_tile
     );
     grid_clb grid_clb_8__8_
     (
-        .Test_en(Test_en),
         .ccff_head(ccff_tail_0_0),
         .left_width_0_height_0_subtile_0__pin_clk_0_(left_width_0_height_0_subtile_0__pin_clk_0_),
         .left_width_0_height_0_subtile_0__pin_reset_0_(left_width_0_height_0_subtile_0__pin_reset_0_),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
         .right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
         .right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),
@@ -291,6 +290,7 @@ module top_right_tile
         .right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -360,8 +360,8 @@ module top_right_tile
         .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(bottom_width_0_height_0_subtile_1__pin_inpad_0_),
         .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(bottom_width_0_height_0_subtile_2__pin_inpad_0_),
         .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(bottom_width_0_height_0_subtile_3__pin_inpad_0_),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail_2),
         .chanx_left_out(chanx_left_out_0),
         .chany_bottom_out(chany_bottom_out_0)
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_tile.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_tile.v
index 44b8c6e..f8eddaf 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_tile.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRC/tile/top_tile.v
@@ -2,18 +2,17 @@
 //netlist name: FPGA88_SOFA_A
 module top_tile
 (
-    IO_ISOL_N,
-    Test_en,
     ccff_head_1,
     ccff_head_2,
     chanx_left_in,
     chanx_right_in_0,
     chany_bottom_in,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
+    gfpga_pad_io_soc_in,
+    isol_n,
     left_width_0_height_0_subtile_0__pin_clk_0_,
     left_width_0_height_0_subtile_0__pin_reset_0_,
-    pReset,
     prog_clk,
+    prog_reset,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_,
     right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
@@ -26,6 +25,7 @@ module top_tile
     right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
     right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
     right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
+    scan_enable,
     top_width_0_height_0_subtile_0__pin_cin_0_,
     top_width_0_height_0_subtile_0__pin_reg_in_0_,
     top_width_0_height_0_subtile_0__pin_sc_in_0_,
@@ -41,8 +41,8 @@ module top_tile
     chanx_left_out,
     chanx_right_out_0,
     chany_bottom_out,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
+    gfpga_pad_io_soc_dir,
+    gfpga_pad_io_soc_out,
     right_width_0_height_0_subtile_0__pin_O_10_,
     right_width_0_height_0_subtile_0__pin_O_11_,
     right_width_0_height_0_subtile_0__pin_O_12_,
@@ -61,18 +61,17 @@ module top_tile
     top_width_0_height_0_subtile_0__pin_O_7_
 );
 
-    input IO_ISOL_N;
-    input Test_en;
     input ccff_head_1;
     input ccff_head_2;
     input [29:0]chanx_left_in;
     input [29:0]chanx_right_in_0;
     input [29:0]chany_bottom_in;
-    input [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+    input [3:0]gfpga_pad_io_soc_in;
+    input isol_n;
     input left_width_0_height_0_subtile_0__pin_clk_0_;
     input left_width_0_height_0_subtile_0__pin_reset_0_;
-    input pReset;
     input prog_clk;
+    input prog_reset;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
     input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@@ -85,6 +84,7 @@ module top_tile
     input right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
     input right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
     input right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
+    input scan_enable;
     input top_width_0_height_0_subtile_0__pin_cin_0_;
     input top_width_0_height_0_subtile_0__pin_reg_in_0_;
     input top_width_0_height_0_subtile_0__pin_sc_in_0_;
@@ -100,8 +100,8 @@ module top_tile
     output [29:0]chanx_left_out;
     output [29:0]chanx_right_out_0;
     output [29:0]chany_bottom_out;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    output [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    output [3:0]gfpga_pad_io_soc_dir;
+    output [3:0]gfpga_pad_io_soc_out;
     output right_width_0_height_0_subtile_0__pin_O_10_;
     output right_width_0_height_0_subtile_0__pin_O_11_;
     output right_width_0_height_0_subtile_0__pin_O_12_;
@@ -119,8 +119,6 @@ module top_tile
     output top_width_0_height_0_subtile_0__pin_O_6_;
     output top_width_0_height_0_subtile_0__pin_O_7_;
 
-    wire IO_ISOL_N;
-    wire Test_en;
     wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_;
     wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_;
     wire bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_;
@@ -160,9 +158,10 @@ module top_tile
     wire [29:0]chany_bottom_out;
     wire [29:0]chany_bottom_out_0;
     wire [29:0]chany_top_out;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [3:0]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+    wire [3:0]gfpga_pad_io_soc_dir;
+    wire [3:0]gfpga_pad_io_soc_in;
+    wire [3:0]gfpga_pad_io_soc_out;
+    wire isol_n;
     wire left_grid_right_width_0_height_0_subtile_0__pin_I4_0_;
     wire left_grid_right_width_0_height_0_subtile_0__pin_I4_1_;
     wire left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_;
@@ -181,8 +180,8 @@ module top_tile
     wire left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
     wire left_width_0_height_0_subtile_0__pin_clk_0_;
     wire left_width_0_height_0_subtile_0__pin_reset_0_;
-    wire pReset;
     wire prog_clk;
+    wire prog_reset;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_;
     wire right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
@@ -203,6 +202,7 @@ module top_tile
     wire right_width_0_height_0_subtile_0__pin_O_15_;
     wire right_width_0_height_0_subtile_0__pin_O_8_;
     wire right_width_0_height_0_subtile_0__pin_O_9_;
+    wire scan_enable;
     wire top_width_0_height_0_subtile_0__pin_O_0_;
     wire top_width_0_height_0_subtile_0__pin_O_1_;
     wire top_width_0_height_0_subtile_0__pin_O_2_;
@@ -217,13 +217,13 @@ module top_tile
 
     cbx_1__8_ cbx_1__8_
     (
-        .IO_ISOL_N(IO_ISOL_N),
         .ccff_head_0(ccff_tail_2),
         .chanx_left_in(chanx_left_in),
         .chanx_right_in(chanx_left_out_0),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
-        .pReset(pReset),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
+        .isol_n(isol_n),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -247,16 +247,16 @@ module top_tile
         .ccff_tail(ccff_tail_0),
         .chanx_left_out(chanx_left_out),
         .chanx_right_out(chanx_right_out),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT)
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out)
     );
     cby_1__1_ cby_1__8_
     (
         .ccff_head(ccff_head_1),
         .chany_bottom_in(chany_bottom_in),
         .chany_top_in(chany_bottom_out_0),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .ccff_tail(ccff_tail_1),
         .chany_bottom_out(chany_bottom_out),
         .chany_top_out(chany_top_out),
@@ -279,12 +279,11 @@ module top_tile
     );
     grid_clb grid_clb_1__8_
     (
-        .Test_en(Test_en),
         .ccff_head(ccff_tail_1),
         .left_width_0_height_0_subtile_0__pin_clk_0_(left_width_0_height_0_subtile_0__pin_clk_0_),
         .left_width_0_height_0_subtile_0__pin_reset_0_(left_width_0_height_0_subtile_0__pin_reset_0_),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_width_0_height_0_subtile_0__pin_I4_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4_0_),
         .right_width_0_height_0_subtile_0__pin_I4_1_(left_grid_right_width_0_height_0_subtile_0__pin_I4_1_),
         .right_width_0_height_0_subtile_0__pin_I4i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I4i_0_),
@@ -301,6 +300,7 @@ module top_tile
         .right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -367,8 +367,8 @@ module top_tile
         .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(bottom_width_0_height_0_subtile_1__pin_inpad_0_),
         .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(bottom_width_0_height_0_subtile_2__pin_inpad_0_),
         .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(bottom_width_0_height_0_subtile_3__pin_inpad_0_),
-        .pReset(pReset),
         .prog_clk(prog_clk),
+        .prog_reset(prog_reset),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_),
         .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/fpga_top.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/fpga_top.v
index 54050e1..7a2e681 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/fpga_top.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/fpga_top.v
@@ -3,39 +3,39 @@
 module fpga_top
 (
     clk,
-    Reset,
-    IO_ISOL_N,
-    pReset,
+    reset,
+    isol_n,
+    prog_reset,
     prog_clk,
-    Test_en,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    scan_enable,
+    gfpga_pad_io_soc_in,
+    gfpga_pad_io_soc_out,
+    gfpga_pad_io_soc_dir,
     ccff_head,
     ccff_tail
 );
 
     input clk;
-    input Reset;
-    input IO_ISOL_N;
-    input pReset;
+    input reset;
+    input isol_n;
+    input prog_reset;
     input prog_clk;
-    input Test_en;
-    input [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    output [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    output [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    input scan_enable;
+    input [0:127]gfpga_pad_io_soc_in;
+    output [0:127]gfpga_pad_io_soc_out;
+    output [0:127]gfpga_pad_io_soc_dir;
     input ccff_head;
     output ccff_tail;
 
     wire clk;
-    wire Reset;
-    wire IO_ISOL_N;
-    wire pReset;
+    wire reset;
+    wire isol_n;
+    wire prog_reset;
     wire prog_clk;
-    wire Test_en;
-    wire [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    wire [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire scan_enable;
+    wire [0:127]gfpga_pad_io_soc_in;
+    wire [0:127]gfpga_pad_io_soc_out;
+    wire [0:127]gfpga_pad_io_soc_dir;
     wire ccff_head;
     wire ccff_tail;
     wire cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;
@@ -4649,12 +4649,12 @@ module fpga_top
 
     grid_io_top_top grid_io_top_top_1__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:3]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0:3]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0:3]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0:3]),
         .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4668,12 +4668,12 @@ module fpga_top
     );
     grid_io_top_top grid_io_top_top_2__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4:7]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4:7]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4:7]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[4:7]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[4:7]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[4:7]),
         .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4687,12 +4687,12 @@ module fpga_top
     );
     grid_io_top_top grid_io_top_top_3__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8:11]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8:11]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8:11]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[8:11]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[8:11]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[8:11]),
         .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4706,12 +4706,12 @@ module fpga_top
     );
     grid_io_top_top grid_io_top_top_4__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12:15]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12:15]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12:15]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[12:15]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[12:15]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[12:15]),
         .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4725,12 +4725,12 @@ module fpga_top
     );
     grid_io_top_top grid_io_top_top_5__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16:19]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16:19]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16:19]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[16:19]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[16:19]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[16:19]),
         .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4744,12 +4744,12 @@ module fpga_top
     );
     grid_io_top_top grid_io_top_top_6__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20:23]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20:23]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20:23]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[20:23]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[20:23]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[20:23]),
         .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4763,12 +4763,12 @@ module fpga_top
     );
     grid_io_top_top grid_io_top_top_7__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24:27]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24:27]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24:27]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[24:27]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[24:27]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[24:27]),
         .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4782,12 +4782,12 @@ module fpga_top
     );
     grid_io_top_top grid_io_top_top_8__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28:31]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28:31]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[28:31]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[28:31]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[28:31]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[28:31]),
         .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4801,12 +4801,12 @@ module fpga_top
     );
     grid_io_right_right grid_io_right_right_9__8_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32:35]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32:35]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[32:35]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[32:35]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[32:35]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[32:35]),
         .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
         .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
         .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4820,12 +4820,12 @@ module fpga_top
     );
     grid_io_right_right grid_io_right_right_9__7_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36:39]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36:39]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[36:39]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[36:39]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[36:39]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[36:39]),
         .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
         .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
         .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4839,12 +4839,12 @@ module fpga_top
     );
     grid_io_right_right grid_io_right_right_9__6_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40:43]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40:43]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[40:43]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[40:43]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[40:43]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[40:43]),
         .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
         .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
         .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4858,12 +4858,12 @@ module fpga_top
     );
     grid_io_right_right grid_io_right_right_9__5_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44:47]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44:47]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[44:47]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[44:47]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[44:47]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[44:47]),
         .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
         .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
         .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4877,12 +4877,12 @@ module fpga_top
     );
     grid_io_right_right grid_io_right_right_9__4_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48:51]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48:51]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[48:51]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[48:51]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[48:51]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[48:51]),
         .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
         .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
         .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4896,12 +4896,12 @@ module fpga_top
     );
     grid_io_right_right grid_io_right_right_9__3_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52:55]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52:55]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[52:55]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[52:55]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[52:55]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[52:55]),
         .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
         .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
         .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4915,12 +4915,12 @@ module fpga_top
     );
     grid_io_right_right grid_io_right_right_9__2_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56:59]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56:59]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[56:59]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[56:59]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[56:59]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[56:59]),
         .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
         .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
         .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4934,12 +4934,12 @@ module fpga_top
     );
     grid_io_right_right grid_io_right_right_9__1_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60:63]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60:63]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60:63]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[60:63]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[60:63]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[60:63]),
         .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
         .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
         .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4953,12 +4953,12 @@ module fpga_top
     );
     grid_io_bottom_bottom grid_io_bottom_bottom_8__0_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64:67]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64:67]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[64:67]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[64:67]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[64:67]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[64:67]),
         .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
         .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
         .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4972,12 +4972,12 @@ module fpga_top
     );
     grid_io_bottom_bottom grid_io_bottom_bottom_7__0_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68:71]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68:71]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[68:71]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[68:71]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[68:71]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[68:71]),
         .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
         .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
         .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4991,12 +4991,12 @@ module fpga_top
     );
     grid_io_bottom_bottom grid_io_bottom_bottom_6__0_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72:75]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72:75]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[72:75]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[72:75]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[72:75]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[72:75]),
         .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
         .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
         .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5010,12 +5010,12 @@ module fpga_top
     );
     grid_io_bottom_bottom grid_io_bottom_bottom_5__0_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76:79]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76:79]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[76:79]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[76:79]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[76:79]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[76:79]),
         .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
         .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
         .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5029,12 +5029,12 @@ module fpga_top
     );
     grid_io_bottom_bottom grid_io_bottom_bottom_4__0_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80:83]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80:83]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[80:83]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[80:83]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[80:83]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[80:83]),
         .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
         .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
         .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5048,12 +5048,12 @@ module fpga_top
     );
     grid_io_bottom_bottom grid_io_bottom_bottom_3__0_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84:87]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84:87]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[84:87]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[84:87]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[84:87]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[84:87]),
         .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
         .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
         .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5067,12 +5067,12 @@ module fpga_top
     );
     grid_io_bottom_bottom grid_io_bottom_bottom_2__0_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88:91]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88:91]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[88:91]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[88:91]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[88:91]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[88:91]),
         .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
         .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
         .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5086,12 +5086,12 @@ module fpga_top
     );
     grid_io_bottom_bottom grid_io_bottom_bottom_1__0_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92:95]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92:95]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[92:95]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[92:95]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[92:95]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[92:95]),
         .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
         .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
         .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5105,12 +5105,12 @@ module fpga_top
     );
     grid_io_left_left grid_io_left_left_0__1_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96:99]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96:99]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96:99]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[96:99]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[96:99]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[96:99]),
         .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
         .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
         .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5124,12 +5124,12 @@ module fpga_top
     );
     grid_io_left_left grid_io_left_left_0__2_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100:103]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100:103]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[100:103]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[100:103]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[100:103]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[100:103]),
         .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
         .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
         .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5143,12 +5143,12 @@ module fpga_top
     );
     grid_io_left_left grid_io_left_left_0__3_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104:107]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104:107]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[104:107]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[104:107]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[104:107]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[104:107]),
         .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
         .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
         .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5162,12 +5162,12 @@ module fpga_top
     );
     grid_io_left_left grid_io_left_left_0__4_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108:111]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108:111]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[108:111]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[108:111]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[108:111]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[108:111]),
         .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
         .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
         .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5181,12 +5181,12 @@ module fpga_top
     );
     grid_io_left_left grid_io_left_left_0__5_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112:115]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112:115]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[112:115]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[112:115]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[112:115]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[112:115]),
         .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
         .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
         .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5200,12 +5200,12 @@ module fpga_top
     );
     grid_io_left_left grid_io_left_left_0__6_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116:119]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116:119]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[116:119]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[116:119]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[116:119]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[116:119]),
         .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
         .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
         .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5219,12 +5219,12 @@ module fpga_top
     );
     grid_io_left_left grid_io_left_left_0__7_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120:123]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120:123]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[120:123]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[120:123]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[120:123]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[120:123]),
         .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
         .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
         .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5238,12 +5238,12 @@ module fpga_top
     );
     grid_io_left_left grid_io_left_left_0__8_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124:127]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124:127]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[124:127]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[124:127]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[124:127]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[124:127]),
         .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
         .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
         .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5257,9 +5257,9 @@ module fpga_top
     );
     grid_clb grid_clb_1__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5295,7 +5295,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__0_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5321,9 +5321,9 @@ module fpga_top
     );
     grid_clb grid_clb_1__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5359,7 +5359,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__1_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5385,9 +5385,9 @@ module fpga_top
     );
     grid_clb grid_clb_1__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5423,7 +5423,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__2_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5449,9 +5449,9 @@ module fpga_top
     );
     grid_clb grid_clb_1__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5487,7 +5487,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__3_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5513,9 +5513,9 @@ module fpga_top
     );
     grid_clb grid_clb_1__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5551,7 +5551,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__4_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5577,9 +5577,9 @@ module fpga_top
     );
     grid_clb grid_clb_1__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5615,7 +5615,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__5_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5641,9 +5641,9 @@ module fpga_top
     );
     grid_clb grid_clb_1__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5679,7 +5679,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__6_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5705,9 +5705,9 @@ module fpga_top
     );
     grid_clb grid_clb_1__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5743,7 +5743,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__7_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5769,9 +5769,9 @@ module fpga_top
     );
     grid_clb grid_clb_2__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5807,7 +5807,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__8_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5833,9 +5833,9 @@ module fpga_top
     );
     grid_clb grid_clb_2__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5871,7 +5871,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__9_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5897,9 +5897,9 @@ module fpga_top
     );
     grid_clb grid_clb_2__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5935,7 +5935,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__10_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5961,9 +5961,9 @@ module fpga_top
     );
     grid_clb grid_clb_2__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5999,7 +5999,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__11_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6025,9 +6025,9 @@ module fpga_top
     );
     grid_clb grid_clb_2__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6063,7 +6063,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__12_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6089,9 +6089,9 @@ module fpga_top
     );
     grid_clb grid_clb_2__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6127,7 +6127,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__13_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6153,9 +6153,9 @@ module fpga_top
     );
     grid_clb grid_clb_2__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6191,7 +6191,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__14_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6217,9 +6217,9 @@ module fpga_top
     );
     grid_clb grid_clb_2__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6255,7 +6255,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__15_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6281,9 +6281,9 @@ module fpga_top
     );
     grid_clb grid_clb_3__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6319,7 +6319,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__16_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6345,9 +6345,9 @@ module fpga_top
     );
     grid_clb grid_clb_3__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6383,7 +6383,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__17_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6409,9 +6409,9 @@ module fpga_top
     );
     grid_clb grid_clb_3__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6447,7 +6447,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__18_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6473,9 +6473,9 @@ module fpga_top
     );
     grid_clb grid_clb_3__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6511,7 +6511,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__19_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6537,9 +6537,9 @@ module fpga_top
     );
     grid_clb grid_clb_3__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6575,7 +6575,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__20_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6601,9 +6601,9 @@ module fpga_top
     );
     grid_clb grid_clb_3__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6639,7 +6639,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__21_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6665,9 +6665,9 @@ module fpga_top
     );
     grid_clb grid_clb_3__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6703,7 +6703,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__22_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6729,9 +6729,9 @@ module fpga_top
     );
     grid_clb grid_clb_3__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6767,7 +6767,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__23_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6793,9 +6793,9 @@ module fpga_top
     );
     grid_clb grid_clb_4__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6831,7 +6831,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__24_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6857,9 +6857,9 @@ module fpga_top
     );
     grid_clb grid_clb_4__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6895,7 +6895,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__25_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6921,9 +6921,9 @@ module fpga_top
     );
     grid_clb grid_clb_4__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6959,7 +6959,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__26_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6985,9 +6985,9 @@ module fpga_top
     );
     grid_clb grid_clb_4__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7023,7 +7023,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__27_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7049,9 +7049,9 @@ module fpga_top
     );
     grid_clb grid_clb_4__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7087,7 +7087,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__28_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7113,9 +7113,9 @@ module fpga_top
     );
     grid_clb grid_clb_4__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7151,7 +7151,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__29_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7177,9 +7177,9 @@ module fpga_top
     );
     grid_clb grid_clb_4__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7215,7 +7215,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__30_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7241,9 +7241,9 @@ module fpga_top
     );
     grid_clb grid_clb_4__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7279,7 +7279,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__31_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7305,9 +7305,9 @@ module fpga_top
     );
     grid_clb grid_clb_5__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7343,7 +7343,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__32_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7369,9 +7369,9 @@ module fpga_top
     );
     grid_clb grid_clb_5__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7407,7 +7407,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__33_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7433,9 +7433,9 @@ module fpga_top
     );
     grid_clb grid_clb_5__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7471,7 +7471,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__34_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7497,9 +7497,9 @@ module fpga_top
     );
     grid_clb grid_clb_5__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7535,7 +7535,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__35_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7561,9 +7561,9 @@ module fpga_top
     );
     grid_clb grid_clb_5__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7599,7 +7599,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__36_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7625,9 +7625,9 @@ module fpga_top
     );
     grid_clb grid_clb_5__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7663,7 +7663,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__37_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7689,9 +7689,9 @@ module fpga_top
     );
     grid_clb grid_clb_5__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7727,7 +7727,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__38_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7753,9 +7753,9 @@ module fpga_top
     );
     grid_clb grid_clb_5__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7791,7 +7791,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__39_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7817,9 +7817,9 @@ module fpga_top
     );
     grid_clb grid_clb_6__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7855,7 +7855,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__40_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7881,9 +7881,9 @@ module fpga_top
     );
     grid_clb grid_clb_6__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7919,7 +7919,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__41_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7945,9 +7945,9 @@ module fpga_top
     );
     grid_clb grid_clb_6__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7983,7 +7983,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__42_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8009,9 +8009,9 @@ module fpga_top
     );
     grid_clb grid_clb_6__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8047,7 +8047,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__43_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8073,9 +8073,9 @@ module fpga_top
     );
     grid_clb grid_clb_6__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8111,7 +8111,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__44_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8137,9 +8137,9 @@ module fpga_top
     );
     grid_clb grid_clb_6__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8175,7 +8175,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__45_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8201,9 +8201,9 @@ module fpga_top
     );
     grid_clb grid_clb_6__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8239,7 +8239,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__46_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8265,9 +8265,9 @@ module fpga_top
     );
     grid_clb grid_clb_6__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8303,7 +8303,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__47_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8329,9 +8329,9 @@ module fpga_top
     );
     grid_clb grid_clb_7__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8367,7 +8367,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__48_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8393,9 +8393,9 @@ module fpga_top
     );
     grid_clb grid_clb_7__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8431,7 +8431,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__49_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8457,9 +8457,9 @@ module fpga_top
     );
     grid_clb grid_clb_7__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8495,7 +8495,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__50_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8521,9 +8521,9 @@ module fpga_top
     );
     grid_clb grid_clb_7__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8559,7 +8559,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__51_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8585,9 +8585,9 @@ module fpga_top
     );
     grid_clb grid_clb_7__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8623,7 +8623,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__52_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8649,9 +8649,9 @@ module fpga_top
     );
     grid_clb grid_clb_7__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8687,7 +8687,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__53_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8713,9 +8713,9 @@ module fpga_top
     );
     grid_clb grid_clb_7__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8751,7 +8751,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__54_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8777,9 +8777,9 @@ module fpga_top
     );
     grid_clb grid_clb_7__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8815,7 +8815,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__55_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8841,9 +8841,9 @@ module fpga_top
     );
     grid_clb grid_clb_8__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8879,7 +8879,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_8__1__0_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8905,9 +8905,9 @@ module fpga_top
     );
     grid_clb grid_clb_8__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8943,7 +8943,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_8__1__1_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8969,9 +8969,9 @@ module fpga_top
     );
     grid_clb grid_clb_8__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9007,7 +9007,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_8__1__2_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -9033,9 +9033,9 @@ module fpga_top
     );
     grid_clb grid_clb_8__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9071,7 +9071,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_8__1__3_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -9097,9 +9097,9 @@ module fpga_top
     );
     grid_clb grid_clb_8__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9135,7 +9135,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_8__1__4_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -9161,9 +9161,9 @@ module fpga_top
     );
     grid_clb grid_clb_8__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9199,7 +9199,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_8__1__5_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -9225,9 +9225,9 @@ module fpga_top
     );
     grid_clb grid_clb_8__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9263,7 +9263,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_8__1__6_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -9289,9 +9289,9 @@ module fpga_top
     );
     grid_clb grid_clb_8__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9327,7 +9327,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_8__1__7_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -9353,7 +9353,7 @@ module fpga_top
     );
     sb_0__0_ sb_0__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_0__1__0_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9372,7 +9372,7 @@ module fpga_top
     );
     sb_0__1_ sb_0__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_0__1__1_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9401,7 +9401,7 @@ module fpga_top
     );
     sb_0__1_ sb_0__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_0__1__2_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9430,7 +9430,7 @@ module fpga_top
     );
     sb_0__1_ sb_0__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_0__1__3_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9459,7 +9459,7 @@ module fpga_top
     );
     sb_0__1_ sb_0__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_0__1__4_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9488,7 +9488,7 @@ module fpga_top
     );
     sb_0__1_ sb_0__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_0__1__5_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9517,7 +9517,7 @@ module fpga_top
     );
     sb_0__1_ sb_0__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_0__1__6_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9546,7 +9546,7 @@ module fpga_top
     );
     sb_0__1_ sb_0__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_0__1__7_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9575,7 +9575,7 @@ module fpga_top
     );
     sb_0__8_ sb_0__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_right_in(cbx_1__8__0_chanx_left_out),
         .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9602,7 +9602,7 @@ module fpga_top
     );
     sb_1__0_ sb_1__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__0_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9631,7 +9631,7 @@ module fpga_top
     );
     sb_1__0_ sb_2__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__8_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9660,7 +9660,7 @@ module fpga_top
     );
     sb_1__0_ sb_3__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__16_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9689,7 +9689,7 @@ module fpga_top
     );
     sb_1__0_ sb_4__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__24_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9718,7 +9718,7 @@ module fpga_top
     );
     sb_1__0_ sb_5__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__32_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9747,7 +9747,7 @@ module fpga_top
     );
     sb_1__0_ sb_6__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__40_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9776,7 +9776,7 @@ module fpga_top
     );
     sb_1__0_ sb_7__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__48_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9805,7 +9805,7 @@ module fpga_top
     );
     sb_1__1_ sb_1__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__1_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9852,7 +9852,7 @@ module fpga_top
     );
     sb_1__1_ sb_1__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__2_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9899,7 +9899,7 @@ module fpga_top
     );
     sb_1__1_ sb_1__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__3_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9946,7 +9946,7 @@ module fpga_top
     );
     sb_1__1_ sb_1__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__4_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9993,7 +9993,7 @@ module fpga_top
     );
     sb_1__1_ sb_1__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__5_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10040,7 +10040,7 @@ module fpga_top
     );
     sb_1__1_ sb_1__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__6_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10087,7 +10087,7 @@ module fpga_top
     );
     sb_1__1_ sb_1__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__7_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10134,7 +10134,7 @@ module fpga_top
     );
     sb_1__1_ sb_2__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__9_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10181,7 +10181,7 @@ module fpga_top
     );
     sb_1__1_ sb_2__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__10_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10228,7 +10228,7 @@ module fpga_top
     );
     sb_1__1_ sb_2__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__11_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10275,7 +10275,7 @@ module fpga_top
     );
     sb_1__1_ sb_2__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__12_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10322,7 +10322,7 @@ module fpga_top
     );
     sb_1__1_ sb_2__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__13_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10369,7 +10369,7 @@ module fpga_top
     );
     sb_1__1_ sb_2__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__14_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10416,7 +10416,7 @@ module fpga_top
     );
     sb_1__1_ sb_2__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__15_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10463,7 +10463,7 @@ module fpga_top
     );
     sb_1__1_ sb_3__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__17_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10510,7 +10510,7 @@ module fpga_top
     );
     sb_1__1_ sb_3__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__18_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10557,7 +10557,7 @@ module fpga_top
     );
     sb_1__1_ sb_3__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__19_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10604,7 +10604,7 @@ module fpga_top
     );
     sb_1__1_ sb_3__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__20_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10651,7 +10651,7 @@ module fpga_top
     );
     sb_1__1_ sb_3__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__21_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10698,7 +10698,7 @@ module fpga_top
     );
     sb_1__1_ sb_3__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__22_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10745,7 +10745,7 @@ module fpga_top
     );
     sb_1__1_ sb_3__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__23_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10792,7 +10792,7 @@ module fpga_top
     );
     sb_1__1_ sb_4__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__25_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10839,7 +10839,7 @@ module fpga_top
     );
     sb_1__1_ sb_4__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__26_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10886,7 +10886,7 @@ module fpga_top
     );
     sb_1__1_ sb_4__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__27_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10933,7 +10933,7 @@ module fpga_top
     );
     sb_1__1_ sb_4__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__28_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10980,7 +10980,7 @@ module fpga_top
     );
     sb_1__1_ sb_4__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__29_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11027,7 +11027,7 @@ module fpga_top
     );
     sb_1__1_ sb_4__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__30_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11074,7 +11074,7 @@ module fpga_top
     );
     sb_1__1_ sb_4__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__31_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11121,7 +11121,7 @@ module fpga_top
     );
     sb_1__1_ sb_5__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__33_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11168,7 +11168,7 @@ module fpga_top
     );
     sb_1__1_ sb_5__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__34_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11215,7 +11215,7 @@ module fpga_top
     );
     sb_1__1_ sb_5__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__35_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11262,7 +11262,7 @@ module fpga_top
     );
     sb_1__1_ sb_5__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__36_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11309,7 +11309,7 @@ module fpga_top
     );
     sb_1__1_ sb_5__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__37_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11356,7 +11356,7 @@ module fpga_top
     );
     sb_1__1_ sb_5__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__38_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11403,7 +11403,7 @@ module fpga_top
     );
     sb_1__1_ sb_5__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__39_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11450,7 +11450,7 @@ module fpga_top
     );
     sb_1__1_ sb_6__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__41_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11497,7 +11497,7 @@ module fpga_top
     );
     sb_1__1_ sb_6__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__42_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11544,7 +11544,7 @@ module fpga_top
     );
     sb_1__1_ sb_6__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__43_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11591,7 +11591,7 @@ module fpga_top
     );
     sb_1__1_ sb_6__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__44_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11638,7 +11638,7 @@ module fpga_top
     );
     sb_1__1_ sb_6__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__45_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11685,7 +11685,7 @@ module fpga_top
     );
     sb_1__1_ sb_6__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__46_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11732,7 +11732,7 @@ module fpga_top
     );
     sb_1__1_ sb_6__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__47_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11779,7 +11779,7 @@ module fpga_top
     );
     sb_1__1_ sb_7__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__49_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11826,7 +11826,7 @@ module fpga_top
     );
     sb_1__1_ sb_7__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__50_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11873,7 +11873,7 @@ module fpga_top
     );
     sb_1__1_ sb_7__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__51_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11920,7 +11920,7 @@ module fpga_top
     );
     sb_1__1_ sb_7__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__52_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11967,7 +11967,7 @@ module fpga_top
     );
     sb_1__1_ sb_7__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__53_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12014,7 +12014,7 @@ module fpga_top
     );
     sb_1__1_ sb_7__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__54_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12061,7 +12061,7 @@ module fpga_top
     );
     sb_1__1_ sb_7__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__55_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12108,7 +12108,7 @@ module fpga_top
     );
     sb_1__8_ sb_1__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_right_in(cbx_1__8__1_chanx_left_out),
         .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12153,7 +12153,7 @@ module fpga_top
     );
     sb_1__8_ sb_2__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_right_in(cbx_1__8__2_chanx_left_out),
         .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12198,7 +12198,7 @@ module fpga_top
     );
     sb_1__8_ sb_3__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_right_in(cbx_1__8__3_chanx_left_out),
         .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12243,7 +12243,7 @@ module fpga_top
     );
     sb_1__8_ sb_4__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_right_in(cbx_1__8__4_chanx_left_out),
         .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12288,7 +12288,7 @@ module fpga_top
     );
     sb_1__8_ sb_5__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_right_in(cbx_1__8__5_chanx_left_out),
         .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12333,7 +12333,7 @@ module fpga_top
     );
     sb_1__8_ sb_6__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_right_in(cbx_1__8__6_chanx_left_out),
         .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12378,7 +12378,7 @@ module fpga_top
     );
     sb_1__8_ sb_7__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_right_in(cbx_1__8__7_chanx_left_out),
         .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12423,7 +12423,7 @@ module fpga_top
     );
     sb_8__0_ sb_8__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_8__1__0_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12450,7 +12450,7 @@ module fpga_top
     );
     sb_8__1_ sb_8__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_8__1__1_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12495,7 +12495,7 @@ module fpga_top
     );
     sb_8__1_ sb_8__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_8__1__2_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12540,7 +12540,7 @@ module fpga_top
     );
     sb_8__1_ sb_8__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_8__1__3_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12585,7 +12585,7 @@ module fpga_top
     );
     sb_8__1_ sb_8__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_8__1__4_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12630,7 +12630,7 @@ module fpga_top
     );
     sb_8__1_ sb_8__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_8__1__5_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12675,7 +12675,7 @@ module fpga_top
     );
     sb_8__1_ sb_8__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_8__1__6_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12720,7 +12720,7 @@ module fpga_top
     );
     sb_8__1_ sb_8__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_8__1__7_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12765,7 +12765,7 @@ module fpga_top
     );
     sb_8__8_ sb_8__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(cby_8__1__7_chany_top_out),
         .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12800,7 +12800,7 @@ module fpga_top
     );
     cbx_1__0_ cbx_1__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_0__0__0_chanx_right_out),
         .chanx_right_in(sb_1__0__0_chanx_left_out),
@@ -12815,7 +12815,7 @@ module fpga_top
     );
     cbx_1__0_ cbx_2__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__0__0_chanx_right_out),
         .chanx_right_in(sb_1__0__1_chanx_left_out),
@@ -12830,7 +12830,7 @@ module fpga_top
     );
     cbx_1__0_ cbx_3__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__0__1_chanx_right_out),
         .chanx_right_in(sb_1__0__2_chanx_left_out),
@@ -12845,7 +12845,7 @@ module fpga_top
     );
     cbx_1__0_ cbx_4__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__0__2_chanx_right_out),
         .chanx_right_in(sb_1__0__3_chanx_left_out),
@@ -12860,7 +12860,7 @@ module fpga_top
     );
     cbx_1__0_ cbx_5__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__0__3_chanx_right_out),
         .chanx_right_in(sb_1__0__4_chanx_left_out),
@@ -12875,7 +12875,7 @@ module fpga_top
     );
     cbx_1__0_ cbx_6__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__0__4_chanx_right_out),
         .chanx_right_in(sb_1__0__5_chanx_left_out),
@@ -12890,7 +12890,7 @@ module fpga_top
     );
     cbx_1__0_ cbx_7__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__0__5_chanx_right_out),
         .chanx_right_in(sb_1__0__6_chanx_left_out),
@@ -12905,7 +12905,7 @@ module fpga_top
     );
     cbx_1__0_ cbx_8__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__0__6_chanx_right_out),
         .chanx_right_in(sb_8__0__0_chanx_left_out),
@@ -12920,7 +12920,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_1__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_0__1__0_chanx_right_out),
         .chanx_right_in(sb_1__1__0_chanx_left_out),
@@ -12947,7 +12947,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_1__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_0__1__1_chanx_right_out),
         .chanx_right_in(sb_1__1__1_chanx_left_out),
@@ -12974,7 +12974,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_1__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_0__1__2_chanx_right_out),
         .chanx_right_in(sb_1__1__2_chanx_left_out),
@@ -13001,7 +13001,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_1__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_0__1__3_chanx_right_out),
         .chanx_right_in(sb_1__1__3_chanx_left_out),
@@ -13028,7 +13028,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_1__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_0__1__4_chanx_right_out),
         .chanx_right_in(sb_1__1__4_chanx_left_out),
@@ -13055,7 +13055,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_1__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_0__1__5_chanx_right_out),
         .chanx_right_in(sb_1__1__5_chanx_left_out),
@@ -13082,7 +13082,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_1__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_0__1__6_chanx_right_out),
         .chanx_right_in(sb_1__1__6_chanx_left_out),
@@ -13109,7 +13109,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_2__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__0_chanx_right_out),
         .chanx_right_in(sb_1__1__7_chanx_left_out),
@@ -13136,7 +13136,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_2__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__1_chanx_right_out),
         .chanx_right_in(sb_1__1__8_chanx_left_out),
@@ -13163,7 +13163,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_2__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__2_chanx_right_out),
         .chanx_right_in(sb_1__1__9_chanx_left_out),
@@ -13190,7 +13190,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_2__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__3_chanx_right_out),
         .chanx_right_in(sb_1__1__10_chanx_left_out),
@@ -13217,7 +13217,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_2__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__4_chanx_right_out),
         .chanx_right_in(sb_1__1__11_chanx_left_out),
@@ -13244,7 +13244,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_2__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__5_chanx_right_out),
         .chanx_right_in(sb_1__1__12_chanx_left_out),
@@ -13271,7 +13271,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_2__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__6_chanx_right_out),
         .chanx_right_in(sb_1__1__13_chanx_left_out),
@@ -13298,7 +13298,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_3__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__7_chanx_right_out),
         .chanx_right_in(sb_1__1__14_chanx_left_out),
@@ -13325,7 +13325,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_3__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__8_chanx_right_out),
         .chanx_right_in(sb_1__1__15_chanx_left_out),
@@ -13352,7 +13352,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_3__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__9_chanx_right_out),
         .chanx_right_in(sb_1__1__16_chanx_left_out),
@@ -13379,7 +13379,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_3__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__10_chanx_right_out),
         .chanx_right_in(sb_1__1__17_chanx_left_out),
@@ -13406,7 +13406,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_3__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__11_chanx_right_out),
         .chanx_right_in(sb_1__1__18_chanx_left_out),
@@ -13433,7 +13433,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_3__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__12_chanx_right_out),
         .chanx_right_in(sb_1__1__19_chanx_left_out),
@@ -13460,7 +13460,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_3__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__13_chanx_right_out),
         .chanx_right_in(sb_1__1__20_chanx_left_out),
@@ -13487,7 +13487,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_4__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__14_chanx_right_out),
         .chanx_right_in(sb_1__1__21_chanx_left_out),
@@ -13514,7 +13514,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_4__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__15_chanx_right_out),
         .chanx_right_in(sb_1__1__22_chanx_left_out),
@@ -13541,7 +13541,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_4__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__16_chanx_right_out),
         .chanx_right_in(sb_1__1__23_chanx_left_out),
@@ -13568,7 +13568,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_4__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__17_chanx_right_out),
         .chanx_right_in(sb_1__1__24_chanx_left_out),
@@ -13595,7 +13595,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_4__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__18_chanx_right_out),
         .chanx_right_in(sb_1__1__25_chanx_left_out),
@@ -13622,7 +13622,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_4__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__19_chanx_right_out),
         .chanx_right_in(sb_1__1__26_chanx_left_out),
@@ -13649,7 +13649,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_4__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__20_chanx_right_out),
         .chanx_right_in(sb_1__1__27_chanx_left_out),
@@ -13676,7 +13676,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_5__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__21_chanx_right_out),
         .chanx_right_in(sb_1__1__28_chanx_left_out),
@@ -13703,7 +13703,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_5__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__22_chanx_right_out),
         .chanx_right_in(sb_1__1__29_chanx_left_out),
@@ -13730,7 +13730,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_5__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__23_chanx_right_out),
         .chanx_right_in(sb_1__1__30_chanx_left_out),
@@ -13757,7 +13757,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_5__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__24_chanx_right_out),
         .chanx_right_in(sb_1__1__31_chanx_left_out),
@@ -13784,7 +13784,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_5__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__25_chanx_right_out),
         .chanx_right_in(sb_1__1__32_chanx_left_out),
@@ -13811,7 +13811,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_5__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__26_chanx_right_out),
         .chanx_right_in(sb_1__1__33_chanx_left_out),
@@ -13838,7 +13838,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_5__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__27_chanx_right_out),
         .chanx_right_in(sb_1__1__34_chanx_left_out),
@@ -13865,7 +13865,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_6__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__28_chanx_right_out),
         .chanx_right_in(sb_1__1__35_chanx_left_out),
@@ -13892,7 +13892,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_6__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__29_chanx_right_out),
         .chanx_right_in(sb_1__1__36_chanx_left_out),
@@ -13919,7 +13919,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_6__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__30_chanx_right_out),
         .chanx_right_in(sb_1__1__37_chanx_left_out),
@@ -13946,7 +13946,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_6__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__31_chanx_right_out),
         .chanx_right_in(sb_1__1__38_chanx_left_out),
@@ -13973,7 +13973,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_6__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__32_chanx_right_out),
         .chanx_right_in(sb_1__1__39_chanx_left_out),
@@ -14000,7 +14000,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_6__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__33_chanx_right_out),
         .chanx_right_in(sb_1__1__40_chanx_left_out),
@@ -14027,7 +14027,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_6__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__34_chanx_right_out),
         .chanx_right_in(sb_1__1__41_chanx_left_out),
@@ -14054,7 +14054,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_7__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__35_chanx_right_out),
         .chanx_right_in(sb_1__1__42_chanx_left_out),
@@ -14081,7 +14081,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_7__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__36_chanx_right_out),
         .chanx_right_in(sb_1__1__43_chanx_left_out),
@@ -14108,7 +14108,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_7__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__37_chanx_right_out),
         .chanx_right_in(sb_1__1__44_chanx_left_out),
@@ -14135,7 +14135,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_7__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__38_chanx_right_out),
         .chanx_right_in(sb_1__1__45_chanx_left_out),
@@ -14162,7 +14162,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_7__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__39_chanx_right_out),
         .chanx_right_in(sb_1__1__46_chanx_left_out),
@@ -14189,7 +14189,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_7__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__40_chanx_right_out),
         .chanx_right_in(sb_1__1__47_chanx_left_out),
@@ -14216,7 +14216,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_7__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__41_chanx_right_out),
         .chanx_right_in(sb_1__1__48_chanx_left_out),
@@ -14243,7 +14243,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_8__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__42_chanx_right_out),
         .chanx_right_in(sb_8__1__0_chanx_left_out),
@@ -14270,7 +14270,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_8__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__43_chanx_right_out),
         .chanx_right_in(sb_8__1__1_chanx_left_out),
@@ -14297,7 +14297,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_8__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__44_chanx_right_out),
         .chanx_right_in(sb_8__1__2_chanx_left_out),
@@ -14324,7 +14324,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_8__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__45_chanx_right_out),
         .chanx_right_in(sb_8__1__3_chanx_left_out),
@@ -14351,7 +14351,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_8__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__46_chanx_right_out),
         .chanx_right_in(sb_8__1__4_chanx_left_out),
@@ -14378,7 +14378,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_8__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__47_chanx_right_out),
         .chanx_right_in(sb_8__1__5_chanx_left_out),
@@ -14405,7 +14405,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_8__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__48_chanx_right_out),
         .chanx_right_in(sb_8__1__6_chanx_left_out),
@@ -14432,7 +14432,7 @@ module fpga_top
     );
     cbx_1__8_ cbx_1__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_0__8__0_chanx_right_out),
         .chanx_right_in(sb_1__8__0_chanx_left_out),
@@ -14463,7 +14463,7 @@ module fpga_top
     );
     cbx_1__8_ cbx_2__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__8__0_chanx_right_out),
         .chanx_right_in(sb_1__8__1_chanx_left_out),
@@ -14494,7 +14494,7 @@ module fpga_top
     );
     cbx_1__8_ cbx_3__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__8__1_chanx_right_out),
         .chanx_right_in(sb_1__8__2_chanx_left_out),
@@ -14525,7 +14525,7 @@ module fpga_top
     );
     cbx_1__8_ cbx_4__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__8__2_chanx_right_out),
         .chanx_right_in(sb_1__8__3_chanx_left_out),
@@ -14556,7 +14556,7 @@ module fpga_top
     );
     cbx_1__8_ cbx_5__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__8__3_chanx_right_out),
         .chanx_right_in(sb_1__8__4_chanx_left_out),
@@ -14587,7 +14587,7 @@ module fpga_top
     );
     cbx_1__8_ cbx_6__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__8__4_chanx_right_out),
         .chanx_right_in(sb_1__8__5_chanx_left_out),
@@ -14618,7 +14618,7 @@ module fpga_top
     );
     cbx_1__8_ cbx_7__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__8__5_chanx_right_out),
         .chanx_right_in(sb_1__8__6_chanx_left_out),
@@ -14649,7 +14649,7 @@ module fpga_top
     );
     cbx_1__8_ cbx_8__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__8__6_chanx_right_out),
         .chanx_right_in(sb_8__8__0_chanx_left_out),
@@ -14680,7 +14680,7 @@ module fpga_top
     );
     cby_0__1_ cby_0__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_0__0__0_chany_top_out),
         .chany_top_in(sb_0__1__0_chany_bottom_out),
@@ -14695,7 +14695,7 @@ module fpga_top
     );
     cby_0__1_ cby_0__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_0__1__0_chany_top_out),
         .chany_top_in(sb_0__1__1_chany_bottom_out),
@@ -14710,7 +14710,7 @@ module fpga_top
     );
     cby_0__1_ cby_0__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_0__1__1_chany_top_out),
         .chany_top_in(sb_0__1__2_chany_bottom_out),
@@ -14725,7 +14725,7 @@ module fpga_top
     );
     cby_0__1_ cby_0__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_0__1__2_chany_top_out),
         .chany_top_in(sb_0__1__3_chany_bottom_out),
@@ -14740,7 +14740,7 @@ module fpga_top
     );
     cby_0__1_ cby_0__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_0__1__3_chany_top_out),
         .chany_top_in(sb_0__1__4_chany_bottom_out),
@@ -14755,7 +14755,7 @@ module fpga_top
     );
     cby_0__1_ cby_0__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_0__1__4_chany_top_out),
         .chany_top_in(sb_0__1__5_chany_bottom_out),
@@ -14770,7 +14770,7 @@ module fpga_top
     );
     cby_0__1_ cby_0__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_0__1__5_chany_top_out),
         .chany_top_in(sb_0__1__6_chany_bottom_out),
@@ -14785,7 +14785,7 @@ module fpga_top
     );
     cby_0__1_ cby_0__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_0__1__6_chany_top_out),
         .chany_top_in(sb_0__8__0_chany_bottom_out),
@@ -14800,7 +14800,7 @@ module fpga_top
     );
     cby_1__1_ cby_1__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__0__0_chany_top_out),
         .chany_top_in(sb_1__1__0_chany_bottom_out),
@@ -14827,7 +14827,7 @@ module fpga_top
     );
     cby_1__1_ cby_1__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__0_chany_top_out),
         .chany_top_in(sb_1__1__1_chany_bottom_out),
@@ -14854,7 +14854,7 @@ module fpga_top
     );
     cby_1__1_ cby_1__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__1_chany_top_out),
         .chany_top_in(sb_1__1__2_chany_bottom_out),
@@ -14881,7 +14881,7 @@ module fpga_top
     );
     cby_1__1_ cby_1__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__2_chany_top_out),
         .chany_top_in(sb_1__1__3_chany_bottom_out),
@@ -14908,7 +14908,7 @@ module fpga_top
     );
     cby_1__1_ cby_1__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__3_chany_top_out),
         .chany_top_in(sb_1__1__4_chany_bottom_out),
@@ -14935,7 +14935,7 @@ module fpga_top
     );
     cby_1__1_ cby_1__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__4_chany_top_out),
         .chany_top_in(sb_1__1__5_chany_bottom_out),
@@ -14962,7 +14962,7 @@ module fpga_top
     );
     cby_1__1_ cby_1__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__5_chany_top_out),
         .chany_top_in(sb_1__1__6_chany_bottom_out),
@@ -14989,7 +14989,7 @@ module fpga_top
     );
     cby_1__1_ cby_1__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__6_chany_top_out),
         .chany_top_in(sb_1__8__0_chany_bottom_out),
@@ -15016,7 +15016,7 @@ module fpga_top
     );
     cby_1__1_ cby_2__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__0__1_chany_top_out),
         .chany_top_in(sb_1__1__7_chany_bottom_out),
@@ -15043,7 +15043,7 @@ module fpga_top
     );
     cby_1__1_ cby_2__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__7_chany_top_out),
         .chany_top_in(sb_1__1__8_chany_bottom_out),
@@ -15070,7 +15070,7 @@ module fpga_top
     );
     cby_1__1_ cby_2__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__8_chany_top_out),
         .chany_top_in(sb_1__1__9_chany_bottom_out),
@@ -15097,7 +15097,7 @@ module fpga_top
     );
     cby_1__1_ cby_2__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__9_chany_top_out),
         .chany_top_in(sb_1__1__10_chany_bottom_out),
@@ -15124,7 +15124,7 @@ module fpga_top
     );
     cby_1__1_ cby_2__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__10_chany_top_out),
         .chany_top_in(sb_1__1__11_chany_bottom_out),
@@ -15151,7 +15151,7 @@ module fpga_top
     );
     cby_1__1_ cby_2__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__11_chany_top_out),
         .chany_top_in(sb_1__1__12_chany_bottom_out),
@@ -15178,7 +15178,7 @@ module fpga_top
     );
     cby_1__1_ cby_2__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__12_chany_top_out),
         .chany_top_in(sb_1__1__13_chany_bottom_out),
@@ -15205,7 +15205,7 @@ module fpga_top
     );
     cby_1__1_ cby_2__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__13_chany_top_out),
         .chany_top_in(sb_1__8__1_chany_bottom_out),
@@ -15232,7 +15232,7 @@ module fpga_top
     );
     cby_1__1_ cby_3__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__0__2_chany_top_out),
         .chany_top_in(sb_1__1__14_chany_bottom_out),
@@ -15259,7 +15259,7 @@ module fpga_top
     );
     cby_1__1_ cby_3__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__14_chany_top_out),
         .chany_top_in(sb_1__1__15_chany_bottom_out),
@@ -15286,7 +15286,7 @@ module fpga_top
     );
     cby_1__1_ cby_3__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__15_chany_top_out),
         .chany_top_in(sb_1__1__16_chany_bottom_out),
@@ -15313,7 +15313,7 @@ module fpga_top
     );
     cby_1__1_ cby_3__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__16_chany_top_out),
         .chany_top_in(sb_1__1__17_chany_bottom_out),
@@ -15340,7 +15340,7 @@ module fpga_top
     );
     cby_1__1_ cby_3__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__17_chany_top_out),
         .chany_top_in(sb_1__1__18_chany_bottom_out),
@@ -15367,7 +15367,7 @@ module fpga_top
     );
     cby_1__1_ cby_3__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__18_chany_top_out),
         .chany_top_in(sb_1__1__19_chany_bottom_out),
@@ -15394,7 +15394,7 @@ module fpga_top
     );
     cby_1__1_ cby_3__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__19_chany_top_out),
         .chany_top_in(sb_1__1__20_chany_bottom_out),
@@ -15421,7 +15421,7 @@ module fpga_top
     );
     cby_1__1_ cby_3__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__20_chany_top_out),
         .chany_top_in(sb_1__8__2_chany_bottom_out),
@@ -15448,7 +15448,7 @@ module fpga_top
     );
     cby_1__1_ cby_4__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__0__3_chany_top_out),
         .chany_top_in(sb_1__1__21_chany_bottom_out),
@@ -15475,7 +15475,7 @@ module fpga_top
     );
     cby_1__1_ cby_4__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__21_chany_top_out),
         .chany_top_in(sb_1__1__22_chany_bottom_out),
@@ -15502,7 +15502,7 @@ module fpga_top
     );
     cby_1__1_ cby_4__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__22_chany_top_out),
         .chany_top_in(sb_1__1__23_chany_bottom_out),
@@ -15529,7 +15529,7 @@ module fpga_top
     );
     cby_1__1_ cby_4__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__23_chany_top_out),
         .chany_top_in(sb_1__1__24_chany_bottom_out),
@@ -15556,7 +15556,7 @@ module fpga_top
     );
     cby_1__1_ cby_4__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__24_chany_top_out),
         .chany_top_in(sb_1__1__25_chany_bottom_out),
@@ -15583,7 +15583,7 @@ module fpga_top
     );
     cby_1__1_ cby_4__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__25_chany_top_out),
         .chany_top_in(sb_1__1__26_chany_bottom_out),
@@ -15610,7 +15610,7 @@ module fpga_top
     );
     cby_1__1_ cby_4__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__26_chany_top_out),
         .chany_top_in(sb_1__1__27_chany_bottom_out),
@@ -15637,7 +15637,7 @@ module fpga_top
     );
     cby_1__1_ cby_4__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__27_chany_top_out),
         .chany_top_in(sb_1__8__3_chany_bottom_out),
@@ -15664,7 +15664,7 @@ module fpga_top
     );
     cby_1__1_ cby_5__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__0__4_chany_top_out),
         .chany_top_in(sb_1__1__28_chany_bottom_out),
@@ -15691,7 +15691,7 @@ module fpga_top
     );
     cby_1__1_ cby_5__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__28_chany_top_out),
         .chany_top_in(sb_1__1__29_chany_bottom_out),
@@ -15718,7 +15718,7 @@ module fpga_top
     );
     cby_1__1_ cby_5__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__29_chany_top_out),
         .chany_top_in(sb_1__1__30_chany_bottom_out),
@@ -15745,7 +15745,7 @@ module fpga_top
     );
     cby_1__1_ cby_5__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__30_chany_top_out),
         .chany_top_in(sb_1__1__31_chany_bottom_out),
@@ -15772,7 +15772,7 @@ module fpga_top
     );
     cby_1__1_ cby_5__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__31_chany_top_out),
         .chany_top_in(sb_1__1__32_chany_bottom_out),
@@ -15799,7 +15799,7 @@ module fpga_top
     );
     cby_1__1_ cby_5__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__32_chany_top_out),
         .chany_top_in(sb_1__1__33_chany_bottom_out),
@@ -15826,7 +15826,7 @@ module fpga_top
     );
     cby_1__1_ cby_5__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__33_chany_top_out),
         .chany_top_in(sb_1__1__34_chany_bottom_out),
@@ -15853,7 +15853,7 @@ module fpga_top
     );
     cby_1__1_ cby_5__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__34_chany_top_out),
         .chany_top_in(sb_1__8__4_chany_bottom_out),
@@ -15880,7 +15880,7 @@ module fpga_top
     );
     cby_1__1_ cby_6__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__0__5_chany_top_out),
         .chany_top_in(sb_1__1__35_chany_bottom_out),
@@ -15907,7 +15907,7 @@ module fpga_top
     );
     cby_1__1_ cby_6__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__35_chany_top_out),
         .chany_top_in(sb_1__1__36_chany_bottom_out),
@@ -15934,7 +15934,7 @@ module fpga_top
     );
     cby_1__1_ cby_6__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__36_chany_top_out),
         .chany_top_in(sb_1__1__37_chany_bottom_out),
@@ -15961,7 +15961,7 @@ module fpga_top
     );
     cby_1__1_ cby_6__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__37_chany_top_out),
         .chany_top_in(sb_1__1__38_chany_bottom_out),
@@ -15988,7 +15988,7 @@ module fpga_top
     );
     cby_1__1_ cby_6__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__38_chany_top_out),
         .chany_top_in(sb_1__1__39_chany_bottom_out),
@@ -16015,7 +16015,7 @@ module fpga_top
     );
     cby_1__1_ cby_6__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__39_chany_top_out),
         .chany_top_in(sb_1__1__40_chany_bottom_out),
@@ -16042,7 +16042,7 @@ module fpga_top
     );
     cby_1__1_ cby_6__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__40_chany_top_out),
         .chany_top_in(sb_1__1__41_chany_bottom_out),
@@ -16069,7 +16069,7 @@ module fpga_top
     );
     cby_1__1_ cby_6__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__41_chany_top_out),
         .chany_top_in(sb_1__8__5_chany_bottom_out),
@@ -16096,7 +16096,7 @@ module fpga_top
     );
     cby_1__1_ cby_7__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__0__6_chany_top_out),
         .chany_top_in(sb_1__1__42_chany_bottom_out),
@@ -16123,7 +16123,7 @@ module fpga_top
     );
     cby_1__1_ cby_7__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__42_chany_top_out),
         .chany_top_in(sb_1__1__43_chany_bottom_out),
@@ -16150,7 +16150,7 @@ module fpga_top
     );
     cby_1__1_ cby_7__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__43_chany_top_out),
         .chany_top_in(sb_1__1__44_chany_bottom_out),
@@ -16177,7 +16177,7 @@ module fpga_top
     );
     cby_1__1_ cby_7__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__44_chany_top_out),
         .chany_top_in(sb_1__1__45_chany_bottom_out),
@@ -16204,7 +16204,7 @@ module fpga_top
     );
     cby_1__1_ cby_7__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__45_chany_top_out),
         .chany_top_in(sb_1__1__46_chany_bottom_out),
@@ -16231,7 +16231,7 @@ module fpga_top
     );
     cby_1__1_ cby_7__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__46_chany_top_out),
         .chany_top_in(sb_1__1__47_chany_bottom_out),
@@ -16258,7 +16258,7 @@ module fpga_top
     );
     cby_1__1_ cby_7__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__47_chany_top_out),
         .chany_top_in(sb_1__1__48_chany_bottom_out),
@@ -16285,7 +16285,7 @@ module fpga_top
     );
     cby_1__1_ cby_7__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__48_chany_top_out),
         .chany_top_in(sb_1__8__6_chany_bottom_out),
@@ -16312,7 +16312,7 @@ module fpga_top
     );
     cby_8__1_ cby_8__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_8__0__0_chany_top_out),
         .chany_top_in(sb_8__1__0_chany_bottom_out),
@@ -16343,7 +16343,7 @@ module fpga_top
     );
     cby_8__1_ cby_8__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_8__1__0_chany_top_out),
         .chany_top_in(sb_8__1__1_chany_bottom_out),
@@ -16374,7 +16374,7 @@ module fpga_top
     );
     cby_8__1_ cby_8__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_8__1__1_chany_top_out),
         .chany_top_in(sb_8__1__2_chany_bottom_out),
@@ -16405,7 +16405,7 @@ module fpga_top
     );
     cby_8__1_ cby_8__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_8__1__2_chany_top_out),
         .chany_top_in(sb_8__1__3_chany_bottom_out),
@@ -16436,7 +16436,7 @@ module fpga_top
     );
     cby_8__1_ cby_8__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_8__1__3_chany_top_out),
         .chany_top_in(sb_8__1__4_chany_bottom_out),
@@ -16467,7 +16467,7 @@ module fpga_top
     );
     cby_8__1_ cby_8__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_8__1__4_chany_top_out),
         .chany_top_in(sb_8__1__5_chany_bottom_out),
@@ -16498,7 +16498,7 @@ module fpga_top
     );
     cby_8__1_ cby_8__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_8__1__5_chany_top_out),
         .chany_top_in(sb_8__1__6_chany_bottom_out),
@@ -16529,7 +16529,7 @@ module fpga_top
     );
     cby_8__1_ cby_8__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_8__1__6_chany_top_out),
         .chany_top_in(sb_8__8__0_chany_bottom_out),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_clb.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_clb.v
index cde4367..abe7b72 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_clb.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_clb.v
@@ -2,9 +2,9 @@
 //netlist name: FPGA88_SOFA_A
 module grid_clb
 (
-    pReset,
+    prog_reset,
     prog_clk,
-    Test_en,
+    scan_enable,
     top_width_0_height_0_subtile_0__pin_I0_0_,
     top_width_0_height_0_subtile_0__pin_I0_1_,
     top_width_0_height_0_subtile_0__pin_I0i_0_,
@@ -65,9 +65,9 @@ module grid_clb
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
-    input Test_en;
+    input scan_enable;
     input top_width_0_height_0_subtile_0__pin_I0_0_;
     input top_width_0_height_0_subtile_0__pin_I0_1_;
     input top_width_0_height_0_subtile_0__pin_I0i_0_;
@@ -127,9 +127,9 @@ module grid_clb
     output bottom_width_0_height_0_subtile_0__pin_cout_0_;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
-    wire Test_en;
+    wire scan_enable;
     wire top_width_0_height_0_subtile_0__pin_I0_0_;
     wire top_width_0_height_0_subtile_0__pin_I0_1_;
     wire top_width_0_height_0_subtile_0__pin_I0i_0_;
@@ -191,9 +191,9 @@ module grid_clb
 
     logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .clb_I0({top_width_0_height_0_subtile_0__pin_I0_0_, top_width_0_height_0_subtile_0__pin_I0_1_}),
         .clb_I0i({top_width_0_height_0_subtile_0__pin_I0i_0_, top_width_0_height_0_subtile_0__pin_I0i_1_}),
         .clb_I1({top_width_0_height_0_subtile_0__pin_I1_0_, top_width_0_height_0_subtile_0__pin_I1_1_}),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_bottom_bottom.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_bottom_bottom.v
index 053e8b5..184ee0d 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_bottom_bottom.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_bottom_bottom.v
@@ -2,12 +2,12 @@
 //netlist name: FPGA88_SOFA_A
 module grid_io_bottom_bottom
 (
-    IO_ISOL_N,
-    pReset,
+    isol_n,
+    prog_reset,
     prog_clk,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_io_soc_in,
+    gfpga_pad_io_soc_out,
+    gfpga_pad_io_soc_dir,
     top_width_0_height_0_subtile_0__pin_outpad_0_,
     top_width_0_height_0_subtile_1__pin_outpad_0_,
     top_width_0_height_0_subtile_2__pin_outpad_0_,
@@ -20,12 +20,12 @@ module grid_io_bottom_bottom
     ccff_tail
 );
 
-    input IO_ISOL_N;
-    input pReset;
+    input isol_n;
+    input prog_reset;
     input prog_clk;
-    input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    input [0:3]gfpga_pad_io_soc_in;
+    output [0:3]gfpga_pad_io_soc_out;
+    output [0:3]gfpga_pad_io_soc_dir;
     input top_width_0_height_0_subtile_0__pin_outpad_0_;
     input top_width_0_height_0_subtile_1__pin_outpad_0_;
     input top_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -37,12 +37,12 @@ module grid_io_bottom_bottom
     output top_width_0_height_0_subtile_3__pin_inpad_0_;
     output ccff_tail;
 
-    wire IO_ISOL_N;
-    wire pReset;
+    wire isol_n;
+    wire prog_reset;
     wire prog_clk;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire [0:3]gfpga_pad_io_soc_in;
+    wire [0:3]gfpga_pad_io_soc_out;
+    wire [0:3]gfpga_pad_io_soc_dir;
     wire top_width_0_height_0_subtile_0__pin_outpad_0_;
     wire top_width_0_height_0_subtile_1__pin_outpad_0_;
     wire top_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -59,12 +59,12 @@ module grid_io_bottom_bottom
 
     logical_tile_io_mode_io_ logical_tile_io_mode_io__0
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
         .io_outpad(top_width_0_height_0_subtile_0__pin_outpad_0_),
         .ccff_head(ccff_head),
         .io_inpad(top_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -72,12 +72,12 @@ module grid_io_bottom_bottom
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__1
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
         .io_outpad(top_width_0_height_0_subtile_1__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__0_ccff_tail),
         .io_inpad(top_width_0_height_0_subtile_1__pin_inpad_0_),
@@ -85,12 +85,12 @@ module grid_io_bottom_bottom
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__2
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
         .io_outpad(top_width_0_height_0_subtile_2__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__1_ccff_tail),
         .io_inpad(top_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -98,12 +98,12 @@ module grid_io_bottom_bottom
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__3
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
         .io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__2_ccff_tail),
         .io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_left_left.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_left_left.v
index 5d235de..65d713a 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_left_left.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_left_left.v
@@ -2,12 +2,12 @@
 //netlist name: FPGA88_SOFA_A
 module grid_io_left_left
 (
-    IO_ISOL_N,
-    pReset,
+    isol_n,
+    prog_reset,
     prog_clk,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_io_soc_in,
+    gfpga_pad_io_soc_out,
+    gfpga_pad_io_soc_dir,
     right_width_0_height_0_subtile_0__pin_outpad_0_,
     right_width_0_height_0_subtile_1__pin_outpad_0_,
     right_width_0_height_0_subtile_2__pin_outpad_0_,
@@ -20,12 +20,12 @@ module grid_io_left_left
     ccff_tail
 );
 
-    input IO_ISOL_N;
-    input pReset;
+    input isol_n;
+    input prog_reset;
     input prog_clk;
-    input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    input [0:3]gfpga_pad_io_soc_in;
+    output [0:3]gfpga_pad_io_soc_out;
+    output [0:3]gfpga_pad_io_soc_dir;
     input right_width_0_height_0_subtile_0__pin_outpad_0_;
     input right_width_0_height_0_subtile_1__pin_outpad_0_;
     input right_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -37,12 +37,12 @@ module grid_io_left_left
     output right_width_0_height_0_subtile_3__pin_inpad_0_;
     output ccff_tail;
 
-    wire IO_ISOL_N;
-    wire pReset;
+    wire isol_n;
+    wire prog_reset;
     wire prog_clk;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire [0:3]gfpga_pad_io_soc_in;
+    wire [0:3]gfpga_pad_io_soc_out;
+    wire [0:3]gfpga_pad_io_soc_dir;
     wire right_width_0_height_0_subtile_0__pin_outpad_0_;
     wire right_width_0_height_0_subtile_1__pin_outpad_0_;
     wire right_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -59,12 +59,12 @@ module grid_io_left_left
 
     logical_tile_io_mode_io_ logical_tile_io_mode_io__0
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
         .io_outpad(right_width_0_height_0_subtile_0__pin_outpad_0_),
         .ccff_head(ccff_head),
         .io_inpad(right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -72,12 +72,12 @@ module grid_io_left_left
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__1
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
         .io_outpad(right_width_0_height_0_subtile_1__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__0_ccff_tail),
         .io_inpad(right_width_0_height_0_subtile_1__pin_inpad_0_),
@@ -85,12 +85,12 @@ module grid_io_left_left
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__2
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
         .io_outpad(right_width_0_height_0_subtile_2__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__1_ccff_tail),
         .io_inpad(right_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -98,12 +98,12 @@ module grid_io_left_left
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__3
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
         .io_outpad(right_width_0_height_0_subtile_3__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__2_ccff_tail),
         .io_inpad(right_width_0_height_0_subtile_3__pin_inpad_0_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_right_right.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_right_right.v
index 42d3271..0e9d97d 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_right_right.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_right_right.v
@@ -2,12 +2,12 @@
 //netlist name: FPGA88_SOFA_A
 module grid_io_right_right
 (
-    IO_ISOL_N,
-    pReset,
+    isol_n,
+    prog_reset,
     prog_clk,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_io_soc_in,
+    gfpga_pad_io_soc_out,
+    gfpga_pad_io_soc_dir,
     left_width_0_height_0_subtile_0__pin_outpad_0_,
     left_width_0_height_0_subtile_1__pin_outpad_0_,
     left_width_0_height_0_subtile_2__pin_outpad_0_,
@@ -20,12 +20,12 @@ module grid_io_right_right
     ccff_tail
 );
 
-    input IO_ISOL_N;
-    input pReset;
+    input isol_n;
+    input prog_reset;
     input prog_clk;
-    input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    input [0:3]gfpga_pad_io_soc_in;
+    output [0:3]gfpga_pad_io_soc_out;
+    output [0:3]gfpga_pad_io_soc_dir;
     input left_width_0_height_0_subtile_0__pin_outpad_0_;
     input left_width_0_height_0_subtile_1__pin_outpad_0_;
     input left_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -37,12 +37,12 @@ module grid_io_right_right
     output left_width_0_height_0_subtile_3__pin_inpad_0_;
     output ccff_tail;
 
-    wire IO_ISOL_N;
-    wire pReset;
+    wire isol_n;
+    wire prog_reset;
     wire prog_clk;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire [0:3]gfpga_pad_io_soc_in;
+    wire [0:3]gfpga_pad_io_soc_out;
+    wire [0:3]gfpga_pad_io_soc_dir;
     wire left_width_0_height_0_subtile_0__pin_outpad_0_;
     wire left_width_0_height_0_subtile_1__pin_outpad_0_;
     wire left_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -59,12 +59,12 @@ module grid_io_right_right
 
     logical_tile_io_mode_io_ logical_tile_io_mode_io__0
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
         .io_outpad(left_width_0_height_0_subtile_0__pin_outpad_0_),
         .ccff_head(ccff_head),
         .io_inpad(left_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -72,12 +72,12 @@ module grid_io_right_right
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__1
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
         .io_outpad(left_width_0_height_0_subtile_1__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__0_ccff_tail),
         .io_inpad(left_width_0_height_0_subtile_1__pin_inpad_0_),
@@ -85,12 +85,12 @@ module grid_io_right_right
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__2
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
         .io_outpad(left_width_0_height_0_subtile_2__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__1_ccff_tail),
         .io_inpad(left_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -98,12 +98,12 @@ module grid_io_right_right
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__3
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
         .io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__2_ccff_tail),
         .io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_top_top.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_top_top.v
index b2f5320..d5ab728 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_top_top.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/grid_io_top_top.v
@@ -2,12 +2,12 @@
 //netlist name: FPGA88_SOFA_A
 module grid_io_top_top
 (
-    IO_ISOL_N,
-    pReset,
+    isol_n,
+    prog_reset,
     prog_clk,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_io_soc_in,
+    gfpga_pad_io_soc_out,
+    gfpga_pad_io_soc_dir,
     bottom_width_0_height_0_subtile_0__pin_outpad_0_,
     bottom_width_0_height_0_subtile_1__pin_outpad_0_,
     bottom_width_0_height_0_subtile_2__pin_outpad_0_,
@@ -20,12 +20,12 @@ module grid_io_top_top
     ccff_tail
 );
 
-    input IO_ISOL_N;
-    input pReset;
+    input isol_n;
+    input prog_reset;
     input prog_clk;
-    input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    input [0:3]gfpga_pad_io_soc_in;
+    output [0:3]gfpga_pad_io_soc_out;
+    output [0:3]gfpga_pad_io_soc_dir;
     input bottom_width_0_height_0_subtile_0__pin_outpad_0_;
     input bottom_width_0_height_0_subtile_1__pin_outpad_0_;
     input bottom_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -37,12 +37,12 @@ module grid_io_top_top
     output bottom_width_0_height_0_subtile_3__pin_inpad_0_;
     output ccff_tail;
 
-    wire IO_ISOL_N;
-    wire pReset;
+    wire isol_n;
+    wire prog_reset;
     wire prog_clk;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire [0:3]gfpga_pad_io_soc_in;
+    wire [0:3]gfpga_pad_io_soc_out;
+    wire [0:3]gfpga_pad_io_soc_dir;
     wire bottom_width_0_height_0_subtile_0__pin_outpad_0_;
     wire bottom_width_0_height_0_subtile_1__pin_outpad_0_;
     wire bottom_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -59,12 +59,12 @@ module grid_io_top_top
 
     logical_tile_io_mode_io_ logical_tile_io_mode_io__0
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
         .io_outpad(bottom_width_0_height_0_subtile_0__pin_outpad_0_),
         .ccff_head(ccff_head),
         .io_inpad(bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -72,12 +72,12 @@ module grid_io_top_top
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__1
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
         .io_outpad(bottom_width_0_height_0_subtile_1__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__0_ccff_tail),
         .io_inpad(bottom_width_0_height_0_subtile_1__pin_inpad_0_),
@@ -85,12 +85,12 @@ module grid_io_top_top
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__2
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
         .io_outpad(bottom_width_0_height_0_subtile_2__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__1_ccff_tail),
         .io_inpad(bottom_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -98,12 +98,12 @@ module grid_io_top_top
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__3
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
         .io_outpad(bottom_width_0_height_0_subtile_3__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__2_ccff_tail),
         .io_inpad(bottom_width_0_height_0_subtile_3__pin_inpad_0_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_clb_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_clb_.v
index 8b2da1e..473f444 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_clb_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_clb_.v
@@ -2,9 +2,9 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_clb_mode_clb_
 (
-    pReset,
+    prog_reset,
     prog_clk,
-    Test_en,
+    scan_enable,
     clb_I0,
     clb_I0i,
     clb_I1,
@@ -34,9 +34,9 @@ module logical_tile_clb_mode_clb_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
-    input Test_en;
+    input scan_enable;
     input [0:1]clb_I0;
     input [0:1]clb_I0i;
     input [0:1]clb_I1;
@@ -65,9 +65,9 @@ module logical_tile_clb_mode_clb_
     output clb_cout;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
-    wire Test_en;
+    wire scan_enable;
     wire [0:1]clb_I0;
     wire [0:1]clb_I0i;
     wire [0:1]clb_I1;
@@ -209,9 +209,9 @@ module logical_tile_clb_mode_clb_
 
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .fle_in({direct_interc_19_out, direct_interc_20_out, direct_interc_21_out, direct_interc_22_out}),
         .fle_reg_in(direct_interc_23_out),
         .fle_sc_in(direct_interc_24_out),
@@ -227,9 +227,9 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .fle_in({direct_interc_28_out, direct_interc_29_out, direct_interc_30_out, direct_interc_31_out}),
         .fle_reg_in(direct_interc_32_out),
         .fle_sc_in(direct_interc_33_out),
@@ -245,9 +245,9 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .fle_in({direct_interc_37_out, direct_interc_38_out, direct_interc_39_out, direct_interc_40_out}),
         .fle_reg_in(direct_interc_41_out),
         .fle_sc_in(direct_interc_42_out),
@@ -263,9 +263,9 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .fle_in({direct_interc_46_out, direct_interc_47_out, direct_interc_48_out, direct_interc_49_out}),
         .fle_reg_in(direct_interc_50_out),
         .fle_sc_in(direct_interc_51_out),
@@ -281,9 +281,9 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .fle_in({direct_interc_55_out, direct_interc_56_out, direct_interc_57_out, direct_interc_58_out}),
         .fle_reg_in(direct_interc_59_out),
         .fle_sc_in(direct_interc_60_out),
@@ -299,9 +299,9 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .fle_in({direct_interc_64_out, direct_interc_65_out, direct_interc_66_out, direct_interc_67_out}),
         .fle_reg_in(direct_interc_68_out),
         .fle_sc_in(direct_interc_69_out),
@@ -317,9 +317,9 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .fle_in({direct_interc_73_out, direct_interc_74_out, direct_interc_75_out, direct_interc_76_out}),
         .fle_reg_in(direct_interc_77_out),
         .fle_sc_in(direct_interc_78_out),
@@ -335,9 +335,9 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .fle_in({direct_interc_82_out, direct_interc_83_out, direct_interc_84_out, direct_interc_85_out}),
         .fle_reg_in(direct_interc_86_out),
         .fle_sc_in(direct_interc_87_out),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle.v
index b19563a..45091c4 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle.v
@@ -2,9 +2,9 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_clb_mode_default__fle
 (
-    pReset,
+    prog_reset,
     prog_clk,
-    Test_en,
+    scan_enable,
     fle_in,
     fle_reg_in,
     fle_sc_in,
@@ -19,9 +19,9 @@ module logical_tile_clb_mode_default__fle
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
-    input Test_en;
+    input scan_enable;
     input [0:3]fle_in;
     input fle_reg_in;
     input fle_sc_in;
@@ -35,9 +35,9 @@ module logical_tile_clb_mode_default__fle
     output fle_cout;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
-    wire Test_en;
+    wire scan_enable;
     wire [0:3]fle_in;
     wire fle_reg_in;
     wire fle_sc_in;
@@ -66,9 +66,9 @@ module logical_tile_clb_mode_default__fle
 
     logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .fabric_in({direct_interc_5_out, direct_interc_6_out, direct_interc_7_out, direct_interc_8_out}),
         .fabric_reg_in(direct_interc_9_out),
         .fabric_sc_in(direct_interc_10_out),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
index 817e939..a28b131 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
@@ -2,9 +2,9 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_clb_mode_default__fle_mode_physical__fabric
 (
-    pReset,
+    prog_reset,
     prog_clk,
-    Test_en,
+    scan_enable,
     fabric_in,
     fabric_reg_in,
     fabric_sc_in,
@@ -19,9 +19,9 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
-    input Test_en;
+    input scan_enable;
     input [0:3]fabric_in;
     input fabric_reg_in;
     input fabric_sc_in;
@@ -35,9 +35,9 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     output fabric_cout;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
-    wire Test_en;
+    wire scan_enable;
     wire [0:3]fabric_in;
     wire fabric_reg_in;
     wire fabric_sc_in;
@@ -82,7 +82,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
 
     logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .frac_logic_in({direct_interc_3_out, direct_interc_4_out, direct_interc_5_out, direct_interc_6_out}),
         .frac_logic_cin(direct_interc_7_out),
@@ -93,7 +93,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     );
     logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0
     (
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .ff_D(mux_tree_size2_2_out),
         .ff_DI(direct_interc_8_out),
         .ff_reset(direct_interc_9_out),
@@ -102,7 +102,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     );
     logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1
     (
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .ff_D(mux_tree_size2_3_out),
         .ff_DI(direct_interc_11_out),
         .ff_reset(direct_interc_12_out),
@@ -139,7 +139,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     );
     mux_tree_size2_mem mem_fabric_out_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail),
         .ccff_tail(mux_tree_size2_mem_0_ccff_tail),
@@ -147,7 +147,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     );
     mux_tree_size2_mem mem_fabric_out_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_size2_mem_0_ccff_tail),
         .ccff_tail(mux_tree_size2_mem_1_ccff_tail),
@@ -155,7 +155,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     );
     mux_tree_size2_mem mem_ff_0_D_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_size2_mem_1_ccff_tail),
         .ccff_tail(mux_tree_size2_mem_2_ccff_tail),
@@ -163,7 +163,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     );
     mux_tree_size2_mem mem_ff_1_D_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_size2_mem_2_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v
index 72a652c..eb2974e 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
 (
-    Test_en,
+    scan_enable,
     ff_D,
     ff_DI,
     ff_reset,
@@ -10,14 +10,14 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
     ff_clk
 );
 
-    input Test_en;
+    input scan_enable;
     input ff_D;
     input ff_DI;
     input ff_reset;
     output ff_Q;
     input ff_clk;
 
-    wire Test_en;
+    wire scan_enable;
     wire ff_D;
     wire ff_DI;
     wire ff_reset;
@@ -26,7 +26,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
 
     sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_
     (
-        .SCE(Test_en),
+        .SCE(scan_enable),
         .D(ff_D),
         .SCD(ff_DI),
         .RESET_B(ff_reset),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v
index 87e59c3..86236b0 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic
 (
-    pReset,
+    prog_reset,
     prog_clk,
     frac_logic_in,
     frac_logic_cin,
@@ -12,7 +12,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:3]frac_logic_in;
     input frac_logic_cin;
@@ -21,7 +21,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
     output frac_logic_cout;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:3]frac_logic_in;
     wire frac_logic_cin;
@@ -49,7 +49,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
 
     logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .frac_lut4_in({direct_interc_2_out, direct_interc_3_out, mux_tree_size2_1_out, direct_interc_4_out}),
         .ccff_head(ccff_head),
@@ -81,7 +81,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
     );
     mux_tree_size2_mem mem_frac_logic_out_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail),
         .ccff_tail(mux_tree_size2_mem_0_ccff_tail),
@@ -89,7 +89,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
     );
     mux_tree_size2_mem mem_frac_lut4_0_in_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_size2_mem_0_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v
index 03b1192..cd58b06 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4
 (
-    pReset,
+    prog_reset,
     prog_clk,
     frac_lut4_in,
     ccff_head,
@@ -12,7 +12,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:3]frac_lut4_in;
     input ccff_head;
@@ -21,7 +21,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
     output frac_lut4_lut4_out;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:3]frac_lut4_in;
     wire ccff_head;
@@ -47,7 +47,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
     );
     frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_io_mode_io_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_io_mode_io_.v
index 73136e0..dbb1895 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_io_mode_io_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_io_mode_io_.v
@@ -2,35 +2,35 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_io_mode_io_
 (
-    IO_ISOL_N,
-    pReset,
+    isol_n,
+    prog_reset,
     prog_clk,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_io_soc_in,
+    gfpga_pad_io_soc_out,
+    gfpga_pad_io_soc_dir,
     io_outpad,
     ccff_head,
     io_inpad,
     ccff_tail
 );
 
-    input IO_ISOL_N;
-    input pReset;
+    input isol_n;
+    input prog_reset;
     input prog_clk;
-    input gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    output gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    output gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    input gfpga_pad_io_soc_in;
+    output gfpga_pad_io_soc_out;
+    output gfpga_pad_io_soc_dir;
     input io_outpad;
     input ccff_head;
     output io_inpad;
     output ccff_tail;
 
-    wire IO_ISOL_N;
-    wire pReset;
+    wire isol_n;
+    wire prog_reset;
     wire prog_clk;
-    wire gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    wire gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire gfpga_pad_io_soc_in;
+    wire gfpga_pad_io_soc_out;
+    wire gfpga_pad_io_soc_dir;
     wire io_outpad;
     wire ccff_head;
     wire io_inpad;
@@ -40,12 +40,12 @@ module logical_tile_io_mode_io_
 
     logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
         .iopad_outpad(direct_interc_1_out),
         .ccff_head(ccff_head),
         .iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_io_mode_physical__iopad.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_io_mode_physical__iopad.v
index 3b88cdc..08f0023 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_io_mode_physical__iopad.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/lb/logical_tile_io_mode_physical__iopad.v
@@ -2,58 +2,58 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_io_mode_physical__iopad
 (
-    IO_ISOL_N,
-    pReset,
+    isol_n,
+    prog_reset,
     prog_clk,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_io_soc_in,
+    gfpga_pad_io_soc_out,
+    gfpga_pad_io_soc_dir,
     iopad_outpad,
     ccff_head,
     iopad_inpad,
     ccff_tail
 );
 
-    input IO_ISOL_N;
-    input pReset;
+    input isol_n;
+    input prog_reset;
     input prog_clk;
-    input gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    output gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    output gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    input gfpga_pad_io_soc_in;
+    output gfpga_pad_io_soc_out;
+    output gfpga_pad_io_soc_dir;
     input iopad_outpad;
     input ccff_head;
     output iopad_inpad;
     output ccff_tail;
 
-    wire IO_ISOL_N;
-    wire pReset;
+    wire isol_n;
+    wire prog_reset;
     wire prog_clk;
-    wire gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    wire gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire gfpga_pad_io_soc_in;
+    wire gfpga_pad_io_soc_out;
+    wire gfpga_pad_io_soc_dir;
     wire iopad_outpad;
     wire ccff_head;
     wire iopad_inpad;
     wire ccff_tail;
-    wire EMBEDDED_IO_HD_0_en;
+    wire io_0_en;
 
-    EMBEDDED_IO_HD EMBEDDED_IO_HD_0_
+    io io_0_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
-        .SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
-        .SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
+        .IO_ISOL_N(isol_n),
+        .SOC_IN(gfpga_pad_io_soc_in),
+        .SOC_OUT(gfpga_pad_io_soc_out),
+        .SOC_DIR(gfpga_pad_io_soc_dir),
         .FPGA_OUT(iopad_outpad),
-        .FPGA_DIR(EMBEDDED_IO_HD_0_en),
+        .FPGA_DIR(io_0_en),
         .FPGA_IN(iopad_inpad)
     );
-    EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem
+    io_sky130_fd_sc_hd__dfrtp_1_mem io_sky130_fd_sc_hd__dfrtp_1_mem
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(ccff_tail),
-        .mem_out(EMBEDDED_IO_HD_0_en)
+        .mem_out(io_0_en)
     );
 endmodule
 
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__0_.v
index 44990ca..872e897 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__0_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__0_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module cbx_1__0_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chanx_left_in,
     chanx_right_in,
@@ -16,7 +16,7 @@ module cbx_1__0_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chanx_left_in;
     input [0:29]chanx_right_in;
@@ -29,7 +29,7 @@ module cbx_1__0_
     output bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chanx_left_in;
     wire [0:29]chanx_right_in;
@@ -143,7 +143,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
@@ -151,7 +151,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
@@ -159,7 +159,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
@@ -167,7 +167,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__1_.v
index b218cae..49ef1ce 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__1_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module cbx_1__1_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chanx_left_in,
     chanx_right_in,
@@ -28,7 +28,7 @@ module cbx_1__1_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chanx_left_in;
     input [0:29]chanx_right_in;
@@ -53,7 +53,7 @@ module cbx_1__1_
     output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chanx_left_in;
     wire [0:29]chanx_right_in;
@@ -243,7 +243,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
@@ -251,7 +251,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
@@ -259,7 +259,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
@@ -267,7 +267,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
@@ -275,7 +275,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_8
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
@@ -283,7 +283,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
@@ -291,7 +291,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
@@ -299,7 +299,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_14
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
@@ -363,7 +363,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
@@ -371,7 +371,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
@@ -379,7 +379,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
@@ -387,7 +387,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
@@ -395,7 +395,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_9
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
@@ -403,7 +403,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
@@ -411,7 +411,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
@@ -419,7 +419,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_15
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__8_.v
index 11749f0..61b52dd 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__8_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cbx_1__8_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module cbx_1__8_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chanx_left_in,
     chanx_right_in,
@@ -32,7 +32,7 @@ module cbx_1__8_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chanx_left_in;
     input [0:29]chanx_right_in;
@@ -61,7 +61,7 @@ module cbx_1__8_
     output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chanx_left_in;
     wire [0:29]chanx_right_in;
@@ -295,7 +295,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_bottom_ipin_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
@@ -303,7 +303,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_bottom_ipin_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
@@ -311,7 +311,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_bottom_ipin_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
@@ -319,7 +319,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_bottom_ipin_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
@@ -327,7 +327,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
@@ -335,7 +335,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
@@ -343,7 +343,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
@@ -351,7 +351,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
@@ -359,7 +359,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_8
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail),
@@ -367,7 +367,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail),
@@ -375,7 +375,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail),
@@ -383,7 +383,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_14
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail),
@@ -447,7 +447,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
@@ -455,7 +455,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
@@ -463,7 +463,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
@@ -471,7 +471,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
@@ -479,7 +479,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_9
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
@@ -487,7 +487,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
@@ -495,7 +495,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
@@ -503,7 +503,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_15
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_0__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_0__1_.v
index b25d4b1..bd7d02a 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_0__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_0__1_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module cby_0__1_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chany_bottom_in,
     chany_top_in,
@@ -16,7 +16,7 @@ module cby_0__1_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chany_bottom_in;
     input [0:29]chany_top_in;
@@ -29,7 +29,7 @@ module cby_0__1_
     output left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chany_bottom_in;
     wire [0:29]chany_top_in;
@@ -143,7 +143,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
@@ -151,7 +151,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
@@ -159,7 +159,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
@@ -167,7 +167,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_1__1_.v
index e07ffde..6f6be57 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_1__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_1__1_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module cby_1__1_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chany_bottom_in,
     chany_top_in,
@@ -28,7 +28,7 @@ module cby_1__1_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chany_bottom_in;
     input [0:29]chany_top_in;
@@ -53,7 +53,7 @@ module cby_1__1_
     output left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chany_bottom_in;
     wire [0:29]chany_top_in;
@@ -243,7 +243,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
@@ -251,7 +251,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
@@ -259,7 +259,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
@@ -267,7 +267,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
@@ -275,7 +275,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_8
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
@@ -283,7 +283,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
@@ -291,7 +291,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
@@ -299,7 +299,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_14
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
@@ -363,7 +363,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
@@ -371,7 +371,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
@@ -379,7 +379,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
@@ -387,7 +387,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
@@ -395,7 +395,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_9
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
@@ -403,7 +403,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
@@ -411,7 +411,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
@@ -419,7 +419,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_15
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_8__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_8__1_.v
index 3400642..fa7c84d 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_8__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/cby_8__1_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module cby_8__1_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chany_bottom_in,
     chany_top_in,
@@ -32,7 +32,7 @@ module cby_8__1_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chany_bottom_in;
     input [0:29]chany_top_in;
@@ -61,7 +61,7 @@ module cby_8__1_
     output left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chany_bottom_in;
     wire [0:29]chany_top_in;
@@ -295,7 +295,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_left_ipin_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
@@ -303,7 +303,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_left_ipin_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
@@ -311,7 +311,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_left_ipin_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
@@ -319,7 +319,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_left_ipin_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
@@ -327,7 +327,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
@@ -335,7 +335,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
@@ -343,7 +343,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
@@ -351,7 +351,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
@@ -359,7 +359,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_8
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail),
@@ -367,7 +367,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail),
@@ -375,7 +375,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail),
@@ -383,7 +383,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_14
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail),
@@ -447,7 +447,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
@@ -455,7 +455,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
@@ -463,7 +463,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
@@ -471,7 +471,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
@@ -479,7 +479,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_9
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
@@ -487,7 +487,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
@@ -495,7 +495,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
@@ -503,7 +503,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_15
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__0_.v
index cbaa50a..9951895 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__0_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__0_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module sb_0__0_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chany_top_in,
     top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
@@ -20,7 +20,7 @@ module sb_0__0_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chany_top_in;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
@@ -37,7 +37,7 @@ module sb_0__0_
     output [0:29]chanx_right_out;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chany_top_in;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
@@ -215,7 +215,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@@ -223,7 +223,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@@ -231,7 +231,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@@ -239,7 +239,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@@ -471,7 +471,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@@ -479,7 +479,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@@ -487,7 +487,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_8
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@@ -495,7 +495,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@@ -503,7 +503,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@@ -511,7 +511,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_14
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@@ -519,7 +519,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_16
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
@@ -527,7 +527,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_18
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
@@ -535,7 +535,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
@@ -543,7 +543,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_30
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
@@ -551,7 +551,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_32
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
@@ -559,7 +559,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_34
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
@@ -567,7 +567,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
@@ -575,7 +575,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_46
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
@@ -583,7 +583,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_48
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
@@ -591,7 +591,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_50
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
@@ -599,7 +599,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
@@ -607,7 +607,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
@@ -615,7 +615,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_8
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
@@ -623,7 +623,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
@@ -631,7 +631,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
@@ -639,7 +639,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_14
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
@@ -647,7 +647,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_16
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
@@ -655,7 +655,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_18
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
@@ -663,7 +663,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
@@ -671,7 +671,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_30
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
@@ -679,7 +679,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_32
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
@@ -687,7 +687,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_34
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail),
@@ -695,7 +695,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_28_ccff_tail),
@@ -703,7 +703,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_46
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_28_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_29_ccff_tail),
@@ -711,7 +711,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_48
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_29_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_30_ccff_tail),
@@ -719,7 +719,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_50
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_30_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__1_.v
index d28f361..9e83a5c 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__1_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module sb_0__1_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chany_top_in,
     top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
@@ -30,7 +30,7 @@ module sb_0__1_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chany_top_in;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
@@ -57,7 +57,7 @@ module sb_0__1_
     output [0:29]chany_bottom_out;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chany_top_in;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
@@ -309,7 +309,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_top_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
@@ -317,7 +317,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_top_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
@@ -325,7 +325,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_top_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
@@ -333,7 +333,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_bottom_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
@@ -341,7 +341,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_bottom_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
@@ -433,7 +433,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_top_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
@@ -441,7 +441,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_top_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
@@ -449,7 +449,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_top_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
@@ -457,7 +457,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_top_track_20
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
@@ -465,7 +465,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
@@ -473,7 +473,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
@@ -481,7 +481,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_8
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
@@ -489,7 +489,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
@@ -497,7 +497,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
@@ -505,7 +505,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
@@ -513,7 +513,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_21
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail),
@@ -521,7 +521,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail),
@@ -571,7 +571,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_top_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
@@ -579,7 +579,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
@@ -587,7 +587,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
@@ -595,7 +595,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@@ -603,7 +603,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
@@ -611,7 +611,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_37
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
@@ -689,7 +689,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_top_track_36
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
@@ -697,7 +697,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_top_track_52
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
@@ -705,7 +705,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_right_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
@@ -713,7 +713,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_right_track_14
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
@@ -721,7 +721,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_right_track_16
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
@@ -729,7 +729,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_right_track_18
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail),
@@ -737,7 +737,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_right_track_20
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail),
@@ -745,7 +745,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_right_track_22
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_7_ccff_tail),
@@ -753,7 +753,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_right_track_36
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_8_ccff_tail),
@@ -761,7 +761,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_bottom_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_9_ccff_tail),
@@ -832,7 +832,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@@ -840,7 +840,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_24
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@@ -848,7 +848,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_26
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@@ -856,7 +856,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@@ -864,7 +864,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_30
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
@@ -872,7 +872,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_32
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
@@ -880,7 +880,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_34
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
@@ -888,7 +888,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_50
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
@@ -896,7 +896,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_53
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_9_ccff_tail),
         .ccff_tail(ccff_tail),
@@ -960,7 +960,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_38
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@@ -968,7 +968,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_40
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@@ -976,7 +976,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@@ -984,7 +984,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_46
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@@ -992,7 +992,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_48
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@@ -1000,7 +1000,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_52
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@@ -1008,7 +1008,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_54
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
@@ -1016,7 +1016,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_56
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__8_.v
index a9fc3df..e154d41 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__8_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_0__8_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module sb_0__8_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chanx_right_in,
     right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
@@ -28,7 +28,7 @@ module sb_0__8_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chanx_right_in;
     input right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
@@ -53,7 +53,7 @@ module sb_0__8_
     output [0:29]chany_bottom_out;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chanx_right_in;
     wire right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
@@ -277,7 +277,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
@@ -285,7 +285,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
@@ -293,7 +293,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
@@ -301,7 +301,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@@ -309,7 +309,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_8
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
@@ -317,7 +317,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
@@ -416,7 +416,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@@ -424,7 +424,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_14
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@@ -432,7 +432,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_16
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@@ -440,7 +440,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@@ -448,7 +448,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_30
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
@@ -456,7 +456,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_32
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
@@ -464,7 +464,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_34
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
@@ -472,7 +472,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
@@ -480,7 +480,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_46
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
@@ -488,7 +488,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_48
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
@@ -496,7 +496,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_58
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
@@ -504,7 +504,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail),
@@ -512,7 +512,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail),
@@ -723,7 +723,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_18
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@@ -731,7 +731,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_20
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@@ -739,7 +739,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_22
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@@ -747,7 +747,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_24
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@@ -755,7 +755,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_26
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@@ -763,7 +763,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_36
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@@ -771,7 +771,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_38
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
@@ -779,7 +779,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_40
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
@@ -787,7 +787,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_42
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
@@ -795,7 +795,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_50
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
@@ -803,7 +803,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_52
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
@@ -811,7 +811,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_54
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
@@ -819,7 +819,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_56
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
@@ -827,7 +827,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
@@ -835,7 +835,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
@@ -843,7 +843,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_9
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
@@ -851,7 +851,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
@@ -859,7 +859,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
@@ -867,7 +867,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_15
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
@@ -875,7 +875,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_17
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
@@ -883,7 +883,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_19
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
@@ -891,7 +891,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
@@ -899,7 +899,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_31
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
@@ -907,7 +907,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_33
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
@@ -915,7 +915,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_35
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
@@ -923,7 +923,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
@@ -931,7 +931,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_47
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
@@ -939,7 +939,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_49
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail),
@@ -947,7 +947,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_51
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__0_.v
index 8e5fb2d..8c735e6 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__0_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__0_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module sb_1__0_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chany_top_in,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
@@ -30,7 +30,7 @@ module sb_1__0_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chany_top_in;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@@ -57,7 +57,7 @@ module sb_1__0_
     output [0:29]chanx_left_out;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chany_top_in;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@@ -306,7 +306,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_top_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
@@ -314,7 +314,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_right_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
@@ -322,7 +322,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_right_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
@@ -330,7 +330,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_left_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
@@ -338,7 +338,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_left_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
@@ -437,7 +437,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_top_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
@@ -445,7 +445,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_top_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
@@ -453,7 +453,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_top_track_8
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
@@ -461,7 +461,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
@@ -469,7 +469,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
@@ -477,7 +477,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
@@ -485,7 +485,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
@@ -493,7 +493,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_20
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
@@ -501,7 +501,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
@@ -509,7 +509,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_left_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
@@ -517,7 +517,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_left_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail),
@@ -525,7 +525,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_left_track_21
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail),
@@ -533,7 +533,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_left_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_12_ccff_tail),
@@ -583,7 +583,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_top_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
@@ -591,7 +591,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_top_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
@@ -599,7 +599,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_36
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
@@ -607,7 +607,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@@ -615,7 +615,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
@@ -623,7 +623,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_37
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_12_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
@@ -673,7 +673,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_top_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
@@ -681,7 +681,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_top_track_14
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
@@ -689,7 +689,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_top_track_16
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
@@ -697,7 +697,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_top_track_18
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
@@ -705,7 +705,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_left_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
@@ -713,7 +713,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_left_track_53
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
         .ccff_tail(ccff_tail),
@@ -770,7 +770,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_20
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@@ -778,7 +778,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_22
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@@ -786,7 +786,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_24
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@@ -794,7 +794,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_26
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@@ -802,7 +802,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_36
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
@@ -810,7 +810,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
@@ -818,7 +818,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_52
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
@@ -903,7 +903,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@@ -911,7 +911,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_30
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@@ -919,7 +919,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_32
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@@ -927,7 +927,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_34
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@@ -935,7 +935,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_40
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@@ -943,7 +943,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_42
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@@ -951,7 +951,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
@@ -959,7 +959,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_46
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
@@ -967,7 +967,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_48
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
@@ -975,7 +975,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_50
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
@@ -983,7 +983,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_58
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__1_.v
index 834c68d..87b0f60 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__1_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module sb_1__1_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chany_top_in,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
@@ -48,7 +48,7 @@ module sb_1__1_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chany_top_in;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@@ -93,7 +93,7 @@ module sb_1__1_
     output [0:29]chanx_left_out;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chany_top_in;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@@ -403,7 +403,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_top_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail),
@@ -411,7 +411,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_top_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail),
@@ -419,7 +419,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_right_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail),
@@ -427,7 +427,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_right_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_3_ccff_tail),
@@ -435,7 +435,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_bottom_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_4_ccff_tail),
@@ -443,7 +443,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_bottom_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_5_ccff_tail),
@@ -451,7 +451,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_left_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_6_ccff_tail),
@@ -459,7 +459,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_left_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_7_ccff_tail),
@@ -551,7 +551,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_top_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
@@ -559,7 +559,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_top_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
@@ -567,7 +567,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_top_track_20
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
@@ -575,7 +575,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_right_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
@@ -583,7 +583,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_right_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
@@ -591,7 +591,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_right_track_20
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
@@ -599,7 +599,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_bottom_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
@@ -607,7 +607,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_bottom_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail),
@@ -615,7 +615,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_bottom_track_21
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail),
@@ -623,7 +623,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_left_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail),
@@ -631,7 +631,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_left_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail),
@@ -639,7 +639,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_left_track_21
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail),
@@ -703,7 +703,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size12_mem mem_top_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
@@ -711,7 +711,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size12_mem mem_top_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
@@ -719,7 +719,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size12_mem mem_right_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
@@ -727,7 +727,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size12_mem mem_right_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
@@ -735,7 +735,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size12_mem mem_bottom_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
@@ -743,7 +743,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size12_mem mem_bottom_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
@@ -751,7 +751,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size12_mem mem_left_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
@@ -759,7 +759,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size12_mem mem_left_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
@@ -795,7 +795,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size9_mem mem_top_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
@@ -803,7 +803,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size9_mem mem_right_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
@@ -811,7 +811,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size9_mem mem_bottom_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail),
@@ -819,7 +819,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size9_mem mem_left_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail),
@@ -911,7 +911,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_top_track_36
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
@@ -919,7 +919,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_top_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
@@ -927,7 +927,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_top_track_52
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
@@ -935,7 +935,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_36
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
@@ -943,7 +943,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
@@ -951,7 +951,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_52
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
@@ -959,7 +959,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_37
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
@@ -967,7 +967,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
@@ -975,7 +975,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_53
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
@@ -983,7 +983,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_left_track_37
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
@@ -991,7 +991,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_left_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail),
@@ -999,7 +999,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_left_track_53
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__8_.v
index 0d620a7..7ab0304 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__8_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_1__8_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module sb_1__8_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chanx_right_in,
     right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
@@ -46,7 +46,7 @@ module sb_1__8_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chanx_right_in;
     input right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
@@ -89,7 +89,7 @@ module sb_1__8_
     output [0:29]chanx_left_out;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chanx_right_in;
     wire right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
@@ -340,7 +340,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size8_mem mem_right_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail),
@@ -348,7 +348,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size8_mem mem_right_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail),
@@ -356,7 +356,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size8_mem mem_left_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail),
@@ -385,7 +385,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size9_mem mem_right_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
@@ -393,7 +393,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size9_mem mem_left_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
@@ -401,7 +401,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size9_mem mem_left_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail),
@@ -437,7 +437,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_right_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail),
@@ -445,7 +445,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_right_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail),
@@ -453,7 +453,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_left_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail),
@@ -461,7 +461,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_left_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_3_ccff_tail),
@@ -511,7 +511,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_right_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
@@ -519,7 +519,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_right_track_20
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
@@ -527,7 +527,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_right_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
@@ -535,7 +535,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_left_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
@@ -543,7 +543,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_left_track_21
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
@@ -551,7 +551,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_left_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail),
@@ -608,7 +608,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_36
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
@@ -616,7 +616,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
@@ -624,7 +624,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
@@ -632,7 +632,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
@@ -640,7 +640,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
@@ -648,7 +648,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_9
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
@@ -656,7 +656,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_left_track_37
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
@@ -699,7 +699,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_52
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
@@ -707,7 +707,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
@@ -715,7 +715,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
@@ -723,7 +723,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@@ -731,7 +731,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_53
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
         .ccff_tail(ccff_tail),
@@ -774,7 +774,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_bottom_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
@@ -782,7 +782,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_bottom_track_15
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
@@ -790,7 +790,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_bottom_track_17
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
@@ -798,7 +798,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_bottom_track_19
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
@@ -806,7 +806,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_bottom_track_37
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
@@ -842,7 +842,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_21
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@@ -850,7 +850,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_23
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@@ -858,7 +858,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_25
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@@ -866,7 +866,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_27
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@@ -951,7 +951,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@@ -959,7 +959,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_31
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@@ -967,7 +967,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_33
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@@ -975,7 +975,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_35
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@@ -983,7 +983,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_39
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@@ -991,7 +991,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_41
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@@ -999,7 +999,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_43
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
@@ -1007,7 +1007,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
@@ -1015,7 +1015,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_47
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
@@ -1023,7 +1023,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_49
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
@@ -1031,7 +1031,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_51
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__0_.v
index 51920ee..a2f5e54 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__0_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__0_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module sb_8__0_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chany_top_in,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
@@ -28,7 +28,7 @@ module sb_8__0_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chany_top_in;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@@ -53,7 +53,7 @@ module sb_8__0_
     output [0:29]chanx_left_out;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chany_top_in;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@@ -269,7 +269,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size5_mem mem_top_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
@@ -277,7 +277,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size5_mem mem_top_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
@@ -285,7 +285,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size5_mem mem_top_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
@@ -293,7 +293,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size5_mem mem_top_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@@ -301,7 +301,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size5_mem mem_top_track_8
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
@@ -309,7 +309,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size5_mem mem_top_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
@@ -387,7 +387,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@@ -395,7 +395,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_14
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@@ -403,7 +403,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_16
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@@ -411,7 +411,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_18
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@@ -419,7 +419,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
@@ -427,7 +427,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_46
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
@@ -435,7 +435,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_48
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
@@ -443,7 +443,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_50
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
@@ -451,7 +451,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
@@ -459,7 +459,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
@@ -663,7 +663,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_20
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@@ -671,7 +671,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_22
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@@ -679,7 +679,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_24
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@@ -687,7 +687,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_26
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@@ -695,7 +695,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@@ -703,7 +703,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_30
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@@ -711,7 +711,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_32
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
@@ -719,7 +719,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_34
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
@@ -727,7 +727,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_36
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
@@ -735,7 +735,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_38
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
@@ -743,7 +743,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_40
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
@@ -751,7 +751,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_42
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
@@ -759,7 +759,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
@@ -767,7 +767,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
@@ -775,7 +775,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_9
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
@@ -783,7 +783,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
@@ -791,7 +791,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
@@ -799,7 +799,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_15
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
@@ -807,7 +807,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_17
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
@@ -815,7 +815,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_19
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
@@ -823,7 +823,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
@@ -831,7 +831,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_31
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
@@ -839,7 +839,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_33
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
@@ -847,7 +847,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_35
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
@@ -855,7 +855,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
@@ -863,7 +863,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_47
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
@@ -871,7 +871,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_49
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
@@ -879,7 +879,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_51
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__1_.v
index bdabe6b..b0b256a 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__1_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module sb_8__1_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chany_top_in,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
@@ -46,7 +46,7 @@ module sb_8__1_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chany_top_in;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@@ -89,7 +89,7 @@ module sb_8__1_
     output [0:29]chanx_left_out;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chany_top_in;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@@ -349,7 +349,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size9_mem mem_top_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
@@ -357,7 +357,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size9_mem mem_bottom_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
@@ -365,7 +365,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size9_mem mem_bottom_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail),
@@ -373,7 +373,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size9_mem mem_bottom_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail),
@@ -395,7 +395,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size8_mem mem_top_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail),
@@ -403,7 +403,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size8_mem mem_top_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail),
@@ -418,7 +418,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size10_mem mem_top_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
@@ -447,7 +447,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size11_mem mem_top_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail),
@@ -455,7 +455,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size11_mem mem_bottom_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail),
@@ -463,7 +463,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size11_mem mem_bottom_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail),
@@ -506,7 +506,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size7_mem mem_top_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
@@ -514,7 +514,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size7_mem mem_top_track_20
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
@@ -522,7 +522,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size7_mem mem_top_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
@@ -530,7 +530,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size7_mem mem_bottom_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
@@ -538,7 +538,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size7_mem mem_bottom_track_21
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
@@ -609,7 +609,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size6_mem mem_top_track_36
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
@@ -617,7 +617,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size6_mem mem_top_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
@@ -625,7 +625,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size6_mem mem_top_track_52
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
@@ -633,7 +633,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
@@ -641,7 +641,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_53
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
@@ -649,7 +649,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size6_mem mem_left_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
@@ -657,7 +657,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size6_mem mem_left_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
@@ -665,7 +665,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size6_mem mem_left_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
@@ -673,7 +673,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size6_mem mem_left_track_9
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
@@ -709,7 +709,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_37
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
@@ -717,7 +717,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
@@ -725,7 +725,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size5_mem mem_left_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
@@ -733,7 +733,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size5_mem mem_left_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@@ -783,7 +783,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size4_mem mem_left_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
@@ -791,7 +791,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size4_mem mem_left_track_15
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
@@ -799,7 +799,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size4_mem mem_left_track_17
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
@@ -807,7 +807,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size4_mem mem_left_track_19
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
@@ -815,7 +815,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size4_mem mem_left_track_21
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
@@ -823,7 +823,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size4_mem mem_left_track_23
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail),
@@ -887,7 +887,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size3_mem mem_left_track_25
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@@ -895,7 +895,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size3_mem mem_left_track_27
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@@ -903,7 +903,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size3_mem mem_left_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@@ -911,7 +911,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size3_mem mem_left_track_31
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@@ -919,7 +919,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size3_mem mem_left_track_33
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
@@ -927,7 +927,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size3_mem mem_left_track_35
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
@@ -935,7 +935,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size3_mem mem_left_track_37
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
@@ -943,7 +943,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size3_mem mem_left_track_51
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
@@ -1000,7 +1000,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size2_mem mem_left_track_41
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@@ -1008,7 +1008,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size2_mem mem_left_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@@ -1016,7 +1016,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size2_mem mem_left_track_47
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@@ -1024,7 +1024,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size2_mem mem_left_track_49
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@@ -1032,7 +1032,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size2_mem mem_left_track_53
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@@ -1040,7 +1040,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size2_mem mem_left_track_55
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@@ -1048,7 +1048,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size2_mem mem_left_track_57
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__8_.v
index 79a9f96..071801a 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__8_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/routing/sb_8__8_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module sb_8__8_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chany_bottom_in,
     bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
@@ -36,7 +36,7 @@ module sb_8__8_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chany_bottom_in;
     input bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
@@ -69,7 +69,7 @@ module sb_8__8_
     output [0:29]chanx_left_out;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chany_bottom_in;
     wire bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
@@ -359,7 +359,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
@@ -367,7 +367,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
@@ -375,7 +375,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
@@ -383,7 +383,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@@ -391,7 +391,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_9
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
@@ -399,7 +399,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
@@ -407,7 +407,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_6_ccff_tail),
@@ -415,7 +415,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_7_ccff_tail),
@@ -423,7 +423,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_8_ccff_tail),
@@ -431,7 +431,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_9_ccff_tail),
@@ -439,7 +439,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_9
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_10_ccff_tail),
@@ -447,7 +447,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_11_ccff_tail),
@@ -630,7 +630,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@@ -638,7 +638,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_15
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@@ -646,7 +646,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_17
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@@ -654,7 +654,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_19
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@@ -662,7 +662,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_21
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@@ -670,7 +670,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_23
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@@ -678,7 +678,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_25
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
@@ -686,7 +686,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_27
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
@@ -694,7 +694,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_53
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
@@ -702,7 +702,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_55
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
@@ -710,7 +710,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_57
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
@@ -718,7 +718,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_59
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
@@ -726,7 +726,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_19
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
@@ -734,7 +734,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_21
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
@@ -742,7 +742,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_23
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
@@ -750,7 +750,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_25
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
@@ -758,7 +758,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_27
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
@@ -766,7 +766,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_37
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_14_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
@@ -774,7 +774,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_39
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
@@ -782,7 +782,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_41
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
@@ -790,7 +790,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_43
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
@@ -798,7 +798,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_51
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_17_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
@@ -806,7 +806,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_53
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
@@ -814,7 +814,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_55
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
@@ -822,7 +822,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_57
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
@@ -963,7 +963,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@@ -971,7 +971,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_31
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@@ -979,7 +979,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_33
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@@ -987,7 +987,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_35
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@@ -995,7 +995,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
@@ -1003,7 +1003,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_47
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
@@ -1011,7 +1011,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_49
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
@@ -1019,7 +1019,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_51
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
@@ -1027,7 +1027,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_11_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
@@ -1035,7 +1035,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_15
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
@@ -1043,7 +1043,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_17
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
@@ -1051,7 +1051,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail),
@@ -1059,7 +1059,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_31
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail),
@@ -1067,7 +1067,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_33
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_13_ccff_tail),
@@ -1075,7 +1075,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_35
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_13_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_14_ccff_tail),
@@ -1083,7 +1083,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_15_ccff_tail),
@@ -1091,7 +1091,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_47
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_15_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_16_ccff_tail),
@@ -1099,7 +1099,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_49
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_16_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_17_ccff_tail),
@@ -1107,7 +1107,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_59
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/memories.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/memories.v
index 7c86232..ac63aaa 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/memories.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/memories.v
@@ -2,20 +2,20 @@
 //netlist name: FPGA88_SOFA_A
 module mux_tree_tapbuf_size12_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:3]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -24,28 +24,28 @@ module mux_tree_tapbuf_size12_mem
 assign ccff_tail = mem_out[3];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[1]),
         .Q(mem_out[2])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[2]),
         .Q(mem_out[3])
@@ -54,20 +54,20 @@ endmodule
 
 module mux_tree_tapbuf_size10_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:3]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -76,28 +76,28 @@ module mux_tree_tapbuf_size10_mem
 assign ccff_tail = mem_out[3];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[1]),
         .Q(mem_out[2])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[2]),
         .Q(mem_out[3])
@@ -106,20 +106,20 @@ endmodule
 
 module mux_tree_tapbuf_size3_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:1]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -128,14 +128,14 @@ module mux_tree_tapbuf_size3_mem
 assign ccff_tail = mem_out[1];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
@@ -144,20 +144,20 @@ endmodule
 
 module mux_tree_tapbuf_size7_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:2]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -166,21 +166,21 @@ module mux_tree_tapbuf_size7_mem
 assign ccff_tail = mem_out[2];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[1]),
         .Q(mem_out[2])
@@ -189,20 +189,20 @@ endmodule
 
 module mux_tree_tapbuf_size2_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:1]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -211,14 +211,14 @@ module mux_tree_tapbuf_size2_mem
 assign ccff_tail = mem_out[1];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
@@ -227,20 +227,20 @@ endmodule
 
 module mux_tree_tapbuf_size5_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:2]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -249,21 +249,21 @@ module mux_tree_tapbuf_size5_mem
 assign ccff_tail = mem_out[2];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[1]),
         .Q(mem_out[2])
@@ -272,20 +272,20 @@ endmodule
 
 module mux_tree_tapbuf_size6_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:2]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -294,21 +294,21 @@ module mux_tree_tapbuf_size6_mem
 assign ccff_tail = mem_out[2];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[1]),
         .Q(mem_out[2])
@@ -317,20 +317,20 @@ endmodule
 
 module mux_tree_tapbuf_size4_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:2]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -339,21 +339,21 @@ module mux_tree_tapbuf_size4_mem
 assign ccff_tail = mem_out[2];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[1]),
         .Q(mem_out[2])
@@ -362,20 +362,20 @@ endmodule
 
 module mux_tree_tapbuf_size11_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:3]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -384,28 +384,28 @@ module mux_tree_tapbuf_size11_mem
 assign ccff_tail = mem_out[3];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[1]),
         .Q(mem_out[2])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[2]),
         .Q(mem_out[3])
@@ -414,20 +414,20 @@ endmodule
 
 module mux_tree_tapbuf_size9_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:3]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -436,28 +436,28 @@ module mux_tree_tapbuf_size9_mem
 assign ccff_tail = mem_out[3];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[1]),
         .Q(mem_out[2])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[2]),
         .Q(mem_out[3])
@@ -466,20 +466,20 @@ endmodule
 
 module mux_tree_tapbuf_size8_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:3]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -488,28 +488,28 @@ module mux_tree_tapbuf_size8_mem
 assign ccff_tail = mem_out[3];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[1]),
         .Q(mem_out[2])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[2]),
         .Q(mem_out[3])
@@ -518,20 +518,20 @@ endmodule
 
 module mux_tree_size2_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:1]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -540,14 +540,14 @@ module mux_tree_size2_mem
 assign ccff_tail = mem_out[1];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
@@ -556,20 +556,20 @@ endmodule
 
 module frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:16]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -578,141 +578,141 @@ module frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem
 assign ccff_tail = mem_out[16];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[1]),
         .Q(mem_out[2])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[2]),
         .Q(mem_out[3])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[3]),
         .Q(mem_out[4])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[4]),
         .Q(mem_out[5])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[5]),
         .Q(mem_out[6])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[6]),
         .Q(mem_out[7])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[7]),
         .Q(mem_out[8])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[8]),
         .Q(mem_out[9])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[9]),
         .Q(mem_out[10])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[10]),
         .Q(mem_out[11])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[11]),
         .Q(mem_out[12])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[12]),
         .Q(mem_out[13])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[13]),
         .Q(mem_out[14])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[14]),
         .Q(mem_out[15])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[15]),
         .Q(mem_out[16])
     );
 endmodule
 
-module EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem
+module io_sky130_fd_sc_hd__dfrtp_1_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -721,7 +721,7 @@ module EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem
 assign ccff_tail = mem_out;
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out)
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/user_defined_templates.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/user_defined_templates.v
index 6647581..2498fb3 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/user_defined_templates.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCLint/sub_module/user_defined_templates.v
@@ -139,7 +139,7 @@ module sky130_fd_sc_hd__dfrtp_1
 
 endmodule
 
-module EMBEDDED_IO_HD
+module io
 (
     IO_ISOL_N,
     SOC_IN,
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/fpga_top.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/fpga_top.v
index eba438e..5fbffb0 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/fpga_top.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/fpga_top.v
@@ -12,34 +12,34 @@
 
 // ----- Verilog module for fpga_top -----
 module fpga_top(clk,
-                Reset,
-                IO_ISOL_N,
-                pReset,
+                reset,
+                isol_n,
+                prog_reset,
                 prog_clk,
-                Test_en,
-                gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-                gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-                gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+                scan_enable,
+                gfpga_pad_io_soc_in,
+                gfpga_pad_io_soc_out,
+                gfpga_pad_io_soc_dir,
                 ccff_head,
                 ccff_tail);
 //----- GLOBAL PORTS -----
 input [0:0] clk;
 //----- GLOBAL PORTS -----
-input [0:0] Reset;
+input [0:0] reset;
 //----- GLOBAL PORTS -----
-input [0:0] IO_ISOL_N;
+input [0:0] isol_n;
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- GLOBAL PORTS -----
-input [0:0] Test_en;
+input [0:0] scan_enable;
 //----- GPIN PORTS -----
-input [0:127] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+input [0:127] gfpga_pad_io_soc_in;
 //----- GPOUT PORTS -----
-output [0:127] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+output [0:127] gfpga_pad_io_soc_out;
 //----- GPOUT PORTS -----
-output [0:127] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+output [0:127] gfpga_pad_io_soc_dir;
 //----- INPUT PORTS -----
 input [0:0] ccff_head;
 //----- OUTPUT PORTS -----
@@ -4668,12 +4668,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 // ----- END Local output short connections -----
 
 	grid_io_top_top grid_io_top_top_1__9_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:3]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:3]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:3]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0:3]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0:3]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0:3]),
 		.bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
 		.bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
 		.bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4686,12 +4686,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_top_top_0_ccff_tail));
 
 	grid_io_top_top grid_io_top_top_2__9_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4:7]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4:7]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4:7]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[4:7]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[4:7]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[4:7]),
 		.bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
 		.bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
 		.bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4704,12 +4704,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_top_top_1_ccff_tail));
 
 	grid_io_top_top grid_io_top_top_3__9_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8:11]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8:11]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8:11]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[8:11]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[8:11]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[8:11]),
 		.bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
 		.bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
 		.bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4722,12 +4722,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_top_top_2_ccff_tail));
 
 	grid_io_top_top grid_io_top_top_4__9_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12:15]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12:15]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12:15]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[12:15]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[12:15]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[12:15]),
 		.bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
 		.bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
 		.bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4740,12 +4740,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_top_top_3_ccff_tail));
 
 	grid_io_top_top grid_io_top_top_5__9_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16:19]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16:19]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16:19]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[16:19]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[16:19]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[16:19]),
 		.bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
 		.bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
 		.bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4758,12 +4758,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_top_top_4_ccff_tail));
 
 	grid_io_top_top grid_io_top_top_6__9_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20:23]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20:23]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20:23]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[20:23]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[20:23]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[20:23]),
 		.bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
 		.bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
 		.bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4776,12 +4776,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_top_top_5_ccff_tail));
 
 	grid_io_top_top grid_io_top_top_7__9_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24:27]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24:27]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24:27]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[24:27]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[24:27]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[24:27]),
 		.bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
 		.bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
 		.bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4794,12 +4794,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_top_top_6_ccff_tail));
 
 	grid_io_top_top grid_io_top_top_8__9_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28:31]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28:31]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[28:31]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[28:31]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[28:31]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[28:31]),
 		.bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
 		.bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
 		.bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4812,12 +4812,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_top_top_7_ccff_tail));
 
 	grid_io_right_right grid_io_right_right_9__8_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32:35]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32:35]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[32:35]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[32:35]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[32:35]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[32:35]),
 		.left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
 		.left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
 		.left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4830,12 +4830,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_right_right_0_ccff_tail));
 
 	grid_io_right_right grid_io_right_right_9__7_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36:39]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36:39]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[36:39]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[36:39]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[36:39]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[36:39]),
 		.left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
 		.left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
 		.left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4848,12 +4848,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_right_right_1_ccff_tail));
 
 	grid_io_right_right grid_io_right_right_9__6_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40:43]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40:43]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[40:43]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[40:43]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[40:43]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[40:43]),
 		.left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
 		.left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
 		.left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4866,12 +4866,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_right_right_2_ccff_tail));
 
 	grid_io_right_right grid_io_right_right_9__5_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44:47]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44:47]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[44:47]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[44:47]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[44:47]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[44:47]),
 		.left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
 		.left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
 		.left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4884,12 +4884,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_right_right_3_ccff_tail));
 
 	grid_io_right_right grid_io_right_right_9__4_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48:51]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48:51]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[48:51]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[48:51]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[48:51]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[48:51]),
 		.left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
 		.left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
 		.left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4902,12 +4902,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_right_right_4_ccff_tail));
 
 	grid_io_right_right grid_io_right_right_9__3_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52:55]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52:55]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[52:55]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[52:55]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[52:55]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[52:55]),
 		.left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
 		.left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
 		.left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4920,12 +4920,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_right_right_5_ccff_tail));
 
 	grid_io_right_right grid_io_right_right_9__2_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56:59]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56:59]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[56:59]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[56:59]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[56:59]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[56:59]),
 		.left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
 		.left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
 		.left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4938,12 +4938,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_right_right_6_ccff_tail));
 
 	grid_io_right_right grid_io_right_right_9__1_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60:63]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60:63]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60:63]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[60:63]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[60:63]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[60:63]),
 		.left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
 		.left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
 		.left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4956,12 +4956,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_right_right_7_ccff_tail));
 
 	grid_io_bottom_bottom grid_io_bottom_bottom_8__0_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64:67]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64:67]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[64:67]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[64:67]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[64:67]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[64:67]),
 		.top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
 		.top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
 		.top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4974,12 +4974,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_bottom_bottom_0_ccff_tail));
 
 	grid_io_bottom_bottom grid_io_bottom_bottom_7__0_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68:71]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68:71]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[68:71]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[68:71]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[68:71]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[68:71]),
 		.top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
 		.top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
 		.top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4992,12 +4992,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_bottom_bottom_1_ccff_tail));
 
 	grid_io_bottom_bottom grid_io_bottom_bottom_6__0_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72:75]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72:75]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[72:75]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[72:75]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[72:75]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[72:75]),
 		.top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
 		.top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
 		.top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5010,12 +5010,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_bottom_bottom_2_ccff_tail));
 
 	grid_io_bottom_bottom grid_io_bottom_bottom_5__0_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76:79]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76:79]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[76:79]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[76:79]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[76:79]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[76:79]),
 		.top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
 		.top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
 		.top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5028,12 +5028,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_bottom_bottom_3_ccff_tail));
 
 	grid_io_bottom_bottom grid_io_bottom_bottom_4__0_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80:83]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80:83]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[80:83]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[80:83]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[80:83]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[80:83]),
 		.top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
 		.top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
 		.top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5046,12 +5046,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_bottom_bottom_4_ccff_tail));
 
 	grid_io_bottom_bottom grid_io_bottom_bottom_3__0_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84:87]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84:87]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[84:87]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[84:87]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[84:87]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[84:87]),
 		.top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
 		.top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
 		.top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5064,12 +5064,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_bottom_bottom_5_ccff_tail));
 
 	grid_io_bottom_bottom grid_io_bottom_bottom_2__0_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88:91]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88:91]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[88:91]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[88:91]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[88:91]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[88:91]),
 		.top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
 		.top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
 		.top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5082,12 +5082,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_bottom_bottom_6_ccff_tail));
 
 	grid_io_bottom_bottom grid_io_bottom_bottom_1__0_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92:95]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92:95]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[92:95]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[92:95]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[92:95]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[92:95]),
 		.top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
 		.top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
 		.top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5100,12 +5100,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_bottom_bottom_7_ccff_tail));
 
 	grid_io_left_left grid_io_left_left_0__1_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96:99]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96:99]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96:99]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[96:99]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[96:99]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[96:99]),
 		.right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
 		.right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
 		.right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5118,12 +5118,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_left_left_0_ccff_tail));
 
 	grid_io_left_left grid_io_left_left_0__2_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100:103]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100:103]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[100:103]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[100:103]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[100:103]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[100:103]),
 		.right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
 		.right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
 		.right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5136,12 +5136,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_left_left_1_ccff_tail));
 
 	grid_io_left_left grid_io_left_left_0__3_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104:107]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104:107]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[104:107]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[104:107]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[104:107]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[104:107]),
 		.right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
 		.right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
 		.right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5154,12 +5154,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_left_left_2_ccff_tail));
 
 	grid_io_left_left grid_io_left_left_0__4_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108:111]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108:111]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[108:111]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[108:111]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[108:111]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[108:111]),
 		.right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
 		.right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
 		.right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5172,12 +5172,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_left_left_3_ccff_tail));
 
 	grid_io_left_left grid_io_left_left_0__5_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112:115]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112:115]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[112:115]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[112:115]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[112:115]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[112:115]),
 		.right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
 		.right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
 		.right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5190,12 +5190,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_left_left_4_ccff_tail));
 
 	grid_io_left_left grid_io_left_left_0__6_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116:119]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116:119]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[116:119]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[116:119]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[116:119]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[116:119]),
 		.right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
 		.right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
 		.right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5208,12 +5208,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_left_left_5_ccff_tail));
 
 	grid_io_left_left grid_io_left_left_0__7_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120:123]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120:123]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[120:123]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[120:123]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[120:123]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[120:123]),
 		.right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
 		.right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
 		.right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5226,12 +5226,12 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_left_left_6_ccff_tail));
 
 	grid_io_left_left grid_io_left_left_0__8_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124:127]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124:127]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[124:127]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[124:127]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[124:127]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[124:127]),
 		.right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
 		.right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
 		.right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5244,9 +5244,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_io_left_left_7_ccff_tail));
 
 	grid_clb grid_clb_1__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5282,7 +5282,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__0_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5307,9 +5307,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_0_ccff_tail));
 
 	grid_clb grid_clb_1__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5345,7 +5345,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__1_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5370,9 +5370,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_1_ccff_tail));
 
 	grid_clb grid_clb_1__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5408,7 +5408,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__2_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5433,9 +5433,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_2_ccff_tail));
 
 	grid_clb grid_clb_1__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5471,7 +5471,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__3_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5496,9 +5496,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_3_ccff_tail));
 
 	grid_clb grid_clb_1__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5534,7 +5534,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__4_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5559,9 +5559,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_4_ccff_tail));
 
 	grid_clb grid_clb_1__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5597,7 +5597,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__5_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5622,9 +5622,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_5_ccff_tail));
 
 	grid_clb grid_clb_1__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5660,7 +5660,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__6_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5685,9 +5685,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_6_ccff_tail));
 
 	grid_clb grid_clb_1__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5723,7 +5723,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__7_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5748,9 +5748,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(ccff_tail));
 
 	grid_clb grid_clb_2__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5786,7 +5786,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__8_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5811,9 +5811,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_8_ccff_tail));
 
 	grid_clb grid_clb_2__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5849,7 +5849,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__9_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5874,9 +5874,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_9_ccff_tail));
 
 	grid_clb grid_clb_2__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5912,7 +5912,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__10_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5937,9 +5937,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_10_ccff_tail));
 
 	grid_clb grid_clb_2__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5975,7 +5975,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__11_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6000,9 +6000,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_11_ccff_tail));
 
 	grid_clb grid_clb_2__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6038,7 +6038,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__12_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6063,9 +6063,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_12_ccff_tail));
 
 	grid_clb grid_clb_2__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6101,7 +6101,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__13_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6126,9 +6126,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_13_ccff_tail));
 
 	grid_clb grid_clb_2__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6164,7 +6164,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__14_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6189,9 +6189,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_14_ccff_tail));
 
 	grid_clb grid_clb_2__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6227,7 +6227,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__15_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6252,9 +6252,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_15_ccff_tail));
 
 	grid_clb grid_clb_3__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6290,7 +6290,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__16_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6315,9 +6315,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_16_ccff_tail));
 
 	grid_clb grid_clb_3__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6353,7 +6353,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__17_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6378,9 +6378,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_17_ccff_tail));
 
 	grid_clb grid_clb_3__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6416,7 +6416,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__18_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6441,9 +6441,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_18_ccff_tail));
 
 	grid_clb grid_clb_3__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6479,7 +6479,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__19_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6504,9 +6504,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_19_ccff_tail));
 
 	grid_clb grid_clb_3__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6542,7 +6542,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__20_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6567,9 +6567,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_20_ccff_tail));
 
 	grid_clb grid_clb_3__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6605,7 +6605,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__21_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6630,9 +6630,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_21_ccff_tail));
 
 	grid_clb grid_clb_3__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6668,7 +6668,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__22_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6693,9 +6693,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_22_ccff_tail));
 
 	grid_clb grid_clb_3__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6731,7 +6731,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__23_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6756,9 +6756,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_23_ccff_tail));
 
 	grid_clb grid_clb_4__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6794,7 +6794,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__24_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6819,9 +6819,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_24_ccff_tail));
 
 	grid_clb grid_clb_4__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6857,7 +6857,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__25_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6882,9 +6882,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_25_ccff_tail));
 
 	grid_clb grid_clb_4__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6920,7 +6920,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__26_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6945,9 +6945,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_26_ccff_tail));
 
 	grid_clb grid_clb_4__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6983,7 +6983,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__27_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7008,9 +7008,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_27_ccff_tail));
 
 	grid_clb grid_clb_4__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7046,7 +7046,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__28_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7071,9 +7071,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_28_ccff_tail));
 
 	grid_clb grid_clb_4__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7109,7 +7109,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__29_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7134,9 +7134,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_29_ccff_tail));
 
 	grid_clb grid_clb_4__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7172,7 +7172,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__30_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7197,9 +7197,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_30_ccff_tail));
 
 	grid_clb grid_clb_4__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7235,7 +7235,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__31_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7260,9 +7260,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_31_ccff_tail));
 
 	grid_clb grid_clb_5__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7298,7 +7298,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__32_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7323,9 +7323,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_32_ccff_tail));
 
 	grid_clb grid_clb_5__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7361,7 +7361,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__33_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7386,9 +7386,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_33_ccff_tail));
 
 	grid_clb grid_clb_5__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7424,7 +7424,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__34_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7449,9 +7449,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_34_ccff_tail));
 
 	grid_clb grid_clb_5__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7487,7 +7487,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__35_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7512,9 +7512,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_35_ccff_tail));
 
 	grid_clb grid_clb_5__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7550,7 +7550,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__36_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7575,9 +7575,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_36_ccff_tail));
 
 	grid_clb grid_clb_5__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7613,7 +7613,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__37_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7638,9 +7638,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_37_ccff_tail));
 
 	grid_clb grid_clb_5__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7676,7 +7676,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__38_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7701,9 +7701,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_38_ccff_tail));
 
 	grid_clb grid_clb_5__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7739,7 +7739,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__39_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7764,9 +7764,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_39_ccff_tail));
 
 	grid_clb grid_clb_6__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7802,7 +7802,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__40_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7827,9 +7827,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_40_ccff_tail));
 
 	grid_clb grid_clb_6__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7865,7 +7865,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__41_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7890,9 +7890,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_41_ccff_tail));
 
 	grid_clb grid_clb_6__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7928,7 +7928,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__42_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7953,9 +7953,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_42_ccff_tail));
 
 	grid_clb grid_clb_6__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7991,7 +7991,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__43_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8016,9 +8016,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_43_ccff_tail));
 
 	grid_clb grid_clb_6__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8054,7 +8054,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__44_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8079,9 +8079,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_44_ccff_tail));
 
 	grid_clb grid_clb_6__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8117,7 +8117,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__45_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8142,9 +8142,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_45_ccff_tail));
 
 	grid_clb grid_clb_6__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8180,7 +8180,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__46_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8205,9 +8205,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_46_ccff_tail));
 
 	grid_clb grid_clb_6__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8243,7 +8243,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__47_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8268,9 +8268,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_47_ccff_tail));
 
 	grid_clb grid_clb_7__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8306,7 +8306,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__48_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8331,9 +8331,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_48_ccff_tail));
 
 	grid_clb grid_clb_7__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8369,7 +8369,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__49_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8394,9 +8394,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_49_ccff_tail));
 
 	grid_clb grid_clb_7__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8432,7 +8432,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__50_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8457,9 +8457,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_50_ccff_tail));
 
 	grid_clb grid_clb_7__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8495,7 +8495,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__51_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8520,9 +8520,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_51_ccff_tail));
 
 	grid_clb grid_clb_7__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8558,7 +8558,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__52_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8583,9 +8583,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_52_ccff_tail));
 
 	grid_clb grid_clb_7__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8621,7 +8621,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__53_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8646,9 +8646,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_53_ccff_tail));
 
 	grid_clb grid_clb_7__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8684,7 +8684,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__54_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8709,9 +8709,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_54_ccff_tail));
 
 	grid_clb grid_clb_7__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8747,7 +8747,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_1__1__55_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8772,9 +8772,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_55_ccff_tail));
 
 	grid_clb grid_clb_8__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8810,7 +8810,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_8__1__0_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8835,9 +8835,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_56_ccff_tail));
 
 	grid_clb grid_clb_8__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8873,7 +8873,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_8__1__1_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8898,9 +8898,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_57_ccff_tail));
 
 	grid_clb grid_clb_8__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8936,7 +8936,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_8__1__2_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8961,9 +8961,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_58_ccff_tail));
 
 	grid_clb grid_clb_8__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8999,7 +8999,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_8__1__3_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -9024,9 +9024,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_59_ccff_tail));
 
 	grid_clb grid_clb_8__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9062,7 +9062,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_8__1__4_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -9087,9 +9087,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_60_ccff_tail));
 
 	grid_clb grid_clb_8__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9125,7 +9125,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_8__1__5_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -9150,9 +9150,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_61_ccff_tail));
 
 	grid_clb grid_clb_8__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9188,7 +9188,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_8__1__6_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -9213,9 +9213,9 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_62_ccff_tail));
 
 	grid_clb grid_clb_8__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
 		.top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
 		.top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9251,7 +9251,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
 		.right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
 		.right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-		.left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+		.left_width_0_height_0_subtile_0__pin_reset_0_(reset),
 		.left_width_0_height_0_subtile_0__pin_clk_0_(clk),
 		.ccff_head(cby_8__1__7_ccff_tail),
 		.top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -9276,7 +9276,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(grid_clb_63_ccff_tail));
 
 	sb_0__0_ sb_0__0_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_0__1__0_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9294,7 +9294,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_0__0__0_ccff_tail));
 
 	sb_0__1_ sb_0__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_0__1__1_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9322,7 +9322,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_0__1__0_ccff_tail));
 
 	sb_0__1_ sb_0__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_0__1__2_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9350,7 +9350,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_0__1__1_ccff_tail));
 
 	sb_0__1_ sb_0__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_0__1__3_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9378,7 +9378,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_0__1__2_ccff_tail));
 
 	sb_0__1_ sb_0__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_0__1__4_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9406,7 +9406,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_0__1__3_ccff_tail));
 
 	sb_0__1_ sb_0__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_0__1__5_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9434,7 +9434,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_0__1__4_ccff_tail));
 
 	sb_0__1_ sb_0__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_0__1__6_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9462,7 +9462,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_0__1__5_ccff_tail));
 
 	sb_0__1_ sb_0__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_0__1__7_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9490,7 +9490,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_0__1__6_ccff_tail));
 
 	sb_0__8_ sb_0__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_right_in(cbx_1__8__0_chanx_left_out[0:29]),
 		.right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9516,7 +9516,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_0__8__0_ccff_tail));
 
 	sb_1__0_ sb_1__0_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__0_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9544,7 +9544,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__0__0_ccff_tail));
 
 	sb_1__0_ sb_2__0_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__8_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9572,7 +9572,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__0__1_ccff_tail));
 
 	sb_1__0_ sb_3__0_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__16_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9600,7 +9600,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__0__2_ccff_tail));
 
 	sb_1__0_ sb_4__0_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__24_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9628,7 +9628,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__0__3_ccff_tail));
 
 	sb_1__0_ sb_5__0_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__32_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9656,7 +9656,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__0__4_ccff_tail));
 
 	sb_1__0_ sb_6__0_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__40_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9684,7 +9684,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__0__5_ccff_tail));
 
 	sb_1__0_ sb_7__0_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__48_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9712,7 +9712,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__0__6_ccff_tail));
 
 	sb_1__1_ sb_1__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__1_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9758,7 +9758,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__0_ccff_tail));
 
 	sb_1__1_ sb_1__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__2_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9804,7 +9804,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__1_ccff_tail));
 
 	sb_1__1_ sb_1__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__3_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9850,7 +9850,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__2_ccff_tail));
 
 	sb_1__1_ sb_1__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__4_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9896,7 +9896,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__3_ccff_tail));
 
 	sb_1__1_ sb_1__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__5_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9942,7 +9942,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__4_ccff_tail));
 
 	sb_1__1_ sb_1__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__6_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9988,7 +9988,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__5_ccff_tail));
 
 	sb_1__1_ sb_1__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__7_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10034,7 +10034,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__6_ccff_tail));
 
 	sb_1__1_ sb_2__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__9_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10080,7 +10080,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__7_ccff_tail));
 
 	sb_1__1_ sb_2__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__10_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10126,7 +10126,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__8_ccff_tail));
 
 	sb_1__1_ sb_2__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__11_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10172,7 +10172,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__9_ccff_tail));
 
 	sb_1__1_ sb_2__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__12_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10218,7 +10218,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__10_ccff_tail));
 
 	sb_1__1_ sb_2__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__13_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10264,7 +10264,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__11_ccff_tail));
 
 	sb_1__1_ sb_2__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__14_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10310,7 +10310,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__12_ccff_tail));
 
 	sb_1__1_ sb_2__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__15_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10356,7 +10356,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__13_ccff_tail));
 
 	sb_1__1_ sb_3__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__17_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10402,7 +10402,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__14_ccff_tail));
 
 	sb_1__1_ sb_3__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__18_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10448,7 +10448,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__15_ccff_tail));
 
 	sb_1__1_ sb_3__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__19_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10494,7 +10494,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__16_ccff_tail));
 
 	sb_1__1_ sb_3__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__20_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10540,7 +10540,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__17_ccff_tail));
 
 	sb_1__1_ sb_3__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__21_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10586,7 +10586,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__18_ccff_tail));
 
 	sb_1__1_ sb_3__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__22_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10632,7 +10632,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__19_ccff_tail));
 
 	sb_1__1_ sb_3__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__23_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10678,7 +10678,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__20_ccff_tail));
 
 	sb_1__1_ sb_4__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__25_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10724,7 +10724,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__21_ccff_tail));
 
 	sb_1__1_ sb_4__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__26_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10770,7 +10770,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__22_ccff_tail));
 
 	sb_1__1_ sb_4__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__27_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10816,7 +10816,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__23_ccff_tail));
 
 	sb_1__1_ sb_4__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__28_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10862,7 +10862,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__24_ccff_tail));
 
 	sb_1__1_ sb_4__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__29_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10908,7 +10908,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__25_ccff_tail));
 
 	sb_1__1_ sb_4__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__30_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10954,7 +10954,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__26_ccff_tail));
 
 	sb_1__1_ sb_4__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__31_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11000,7 +11000,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__27_ccff_tail));
 
 	sb_1__1_ sb_5__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__33_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11046,7 +11046,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__28_ccff_tail));
 
 	sb_1__1_ sb_5__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__34_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11092,7 +11092,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__29_ccff_tail));
 
 	sb_1__1_ sb_5__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__35_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11138,7 +11138,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__30_ccff_tail));
 
 	sb_1__1_ sb_5__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__36_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11184,7 +11184,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__31_ccff_tail));
 
 	sb_1__1_ sb_5__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__37_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11230,7 +11230,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__32_ccff_tail));
 
 	sb_1__1_ sb_5__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__38_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11276,7 +11276,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__33_ccff_tail));
 
 	sb_1__1_ sb_5__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__39_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11322,7 +11322,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__34_ccff_tail));
 
 	sb_1__1_ sb_6__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__41_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11368,7 +11368,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__35_ccff_tail));
 
 	sb_1__1_ sb_6__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__42_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11414,7 +11414,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__36_ccff_tail));
 
 	sb_1__1_ sb_6__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__43_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11460,7 +11460,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__37_ccff_tail));
 
 	sb_1__1_ sb_6__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__44_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11506,7 +11506,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__38_ccff_tail));
 
 	sb_1__1_ sb_6__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__45_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11552,7 +11552,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__39_ccff_tail));
 
 	sb_1__1_ sb_6__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__46_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11598,7 +11598,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__40_ccff_tail));
 
 	sb_1__1_ sb_6__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__47_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11644,7 +11644,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__41_ccff_tail));
 
 	sb_1__1_ sb_7__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__49_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11690,7 +11690,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__42_ccff_tail));
 
 	sb_1__1_ sb_7__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__50_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11736,7 +11736,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__43_ccff_tail));
 
 	sb_1__1_ sb_7__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__51_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11782,7 +11782,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__44_ccff_tail));
 
 	sb_1__1_ sb_7__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__52_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11828,7 +11828,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__45_ccff_tail));
 
 	sb_1__1_ sb_7__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__53_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11874,7 +11874,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__46_ccff_tail));
 
 	sb_1__1_ sb_7__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__54_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11920,7 +11920,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__47_ccff_tail));
 
 	sb_1__1_ sb_7__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_1__1__55_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11966,7 +11966,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__1__48_ccff_tail));
 
 	sb_1__8_ sb_1__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_right_in(cbx_1__8__1_chanx_left_out[0:29]),
 		.right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12010,7 +12010,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__8__0_ccff_tail));
 
 	sb_1__8_ sb_2__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_right_in(cbx_1__8__2_chanx_left_out[0:29]),
 		.right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12054,7 +12054,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__8__1_ccff_tail));
 
 	sb_1__8_ sb_3__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_right_in(cbx_1__8__3_chanx_left_out[0:29]),
 		.right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12098,7 +12098,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__8__2_ccff_tail));
 
 	sb_1__8_ sb_4__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_right_in(cbx_1__8__4_chanx_left_out[0:29]),
 		.right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12142,7 +12142,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__8__3_ccff_tail));
 
 	sb_1__8_ sb_5__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_right_in(cbx_1__8__5_chanx_left_out[0:29]),
 		.right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12186,7 +12186,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__8__4_ccff_tail));
 
 	sb_1__8_ sb_6__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_right_in(cbx_1__8__6_chanx_left_out[0:29]),
 		.right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12230,7 +12230,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__8__5_ccff_tail));
 
 	sb_1__8_ sb_7__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_right_in(cbx_1__8__7_chanx_left_out[0:29]),
 		.right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12274,7 +12274,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_1__8__6_ccff_tail));
 
 	sb_8__0_ sb_8__0_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_8__1__0_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12300,7 +12300,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_8__0__0_ccff_tail));
 
 	sb_8__1_ sb_8__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_8__1__1_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12344,7 +12344,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_8__1__0_ccff_tail));
 
 	sb_8__1_ sb_8__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_8__1__2_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12388,7 +12388,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_8__1__1_ccff_tail));
 
 	sb_8__1_ sb_8__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_8__1__3_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12432,7 +12432,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_8__1__2_ccff_tail));
 
 	sb_8__1_ sb_8__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_8__1__4_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12476,7 +12476,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_8__1__3_ccff_tail));
 
 	sb_8__1_ sb_8__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_8__1__5_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12520,7 +12520,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_8__1__4_ccff_tail));
 
 	sb_8__1_ sb_8__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_8__1__6_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12564,7 +12564,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_8__1__5_ccff_tail));
 
 	sb_8__1_ sb_8__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_top_in(cby_8__1__7_chany_bottom_out[0:29]),
 		.top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12608,7 +12608,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_8__1__6_ccff_tail));
 
 	sb_8__8_ sb_8__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(cby_8__1__7_chany_top_out[0:29]),
 		.bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12642,7 +12642,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(sb_8__8__0_ccff_tail));
 
 	cbx_1__0_ cbx_1__0_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_0__0__0_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__0__0_chanx_left_out[0:29]),
@@ -12656,7 +12656,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__0__0_ccff_tail));
 
 	cbx_1__0_ cbx_2__0_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__0__0_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__0__1_chanx_left_out[0:29]),
@@ -12670,7 +12670,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__0__1_ccff_tail));
 
 	cbx_1__0_ cbx_3__0_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__0__1_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__0__2_chanx_left_out[0:29]),
@@ -12684,7 +12684,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__0__2_ccff_tail));
 
 	cbx_1__0_ cbx_4__0_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__0__2_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__0__3_chanx_left_out[0:29]),
@@ -12698,7 +12698,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__0__3_ccff_tail));
 
 	cbx_1__0_ cbx_5__0_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__0__3_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__0__4_chanx_left_out[0:29]),
@@ -12712,7 +12712,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__0__4_ccff_tail));
 
 	cbx_1__0_ cbx_6__0_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__0__4_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__0__5_chanx_left_out[0:29]),
@@ -12726,7 +12726,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__0__5_ccff_tail));
 
 	cbx_1__0_ cbx_7__0_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__0__5_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__0__6_chanx_left_out[0:29]),
@@ -12740,7 +12740,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__0__6_ccff_tail));
 
 	cbx_1__0_ cbx_8__0_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__0__6_chanx_right_out[0:29]),
 		.chanx_right_in(sb_8__0__0_chanx_left_out[0:29]),
@@ -12754,7 +12754,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__0__7_ccff_tail));
 
 	cbx_1__1_ cbx_1__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_0__1__0_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__0_chanx_left_out[0:29]),
@@ -12780,7 +12780,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__0_ccff_tail));
 
 	cbx_1__1_ cbx_1__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_0__1__1_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__1_chanx_left_out[0:29]),
@@ -12806,7 +12806,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__1_ccff_tail));
 
 	cbx_1__1_ cbx_1__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_0__1__2_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__2_chanx_left_out[0:29]),
@@ -12832,7 +12832,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__2_ccff_tail));
 
 	cbx_1__1_ cbx_1__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_0__1__3_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__3_chanx_left_out[0:29]),
@@ -12858,7 +12858,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__3_ccff_tail));
 
 	cbx_1__1_ cbx_1__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_0__1__4_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__4_chanx_left_out[0:29]),
@@ -12884,7 +12884,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__4_ccff_tail));
 
 	cbx_1__1_ cbx_1__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_0__1__5_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__5_chanx_left_out[0:29]),
@@ -12910,7 +12910,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__5_ccff_tail));
 
 	cbx_1__1_ cbx_1__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_0__1__6_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__6_chanx_left_out[0:29]),
@@ -12936,7 +12936,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__6_ccff_tail));
 
 	cbx_1__1_ cbx_2__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__0_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__7_chanx_left_out[0:29]),
@@ -12962,7 +12962,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__7_ccff_tail));
 
 	cbx_1__1_ cbx_2__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__1_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__8_chanx_left_out[0:29]),
@@ -12988,7 +12988,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__8_ccff_tail));
 
 	cbx_1__1_ cbx_2__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__2_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__9_chanx_left_out[0:29]),
@@ -13014,7 +13014,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__9_ccff_tail));
 
 	cbx_1__1_ cbx_2__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__3_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__10_chanx_left_out[0:29]),
@@ -13040,7 +13040,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__10_ccff_tail));
 
 	cbx_1__1_ cbx_2__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__4_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__11_chanx_left_out[0:29]),
@@ -13066,7 +13066,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__11_ccff_tail));
 
 	cbx_1__1_ cbx_2__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__5_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__12_chanx_left_out[0:29]),
@@ -13092,7 +13092,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__12_ccff_tail));
 
 	cbx_1__1_ cbx_2__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__6_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__13_chanx_left_out[0:29]),
@@ -13118,7 +13118,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__13_ccff_tail));
 
 	cbx_1__1_ cbx_3__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__7_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__14_chanx_left_out[0:29]),
@@ -13144,7 +13144,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__14_ccff_tail));
 
 	cbx_1__1_ cbx_3__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__8_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__15_chanx_left_out[0:29]),
@@ -13170,7 +13170,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__15_ccff_tail));
 
 	cbx_1__1_ cbx_3__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__9_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__16_chanx_left_out[0:29]),
@@ -13196,7 +13196,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__16_ccff_tail));
 
 	cbx_1__1_ cbx_3__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__10_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__17_chanx_left_out[0:29]),
@@ -13222,7 +13222,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__17_ccff_tail));
 
 	cbx_1__1_ cbx_3__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__11_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__18_chanx_left_out[0:29]),
@@ -13248,7 +13248,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__18_ccff_tail));
 
 	cbx_1__1_ cbx_3__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__12_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__19_chanx_left_out[0:29]),
@@ -13274,7 +13274,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__19_ccff_tail));
 
 	cbx_1__1_ cbx_3__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__13_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__20_chanx_left_out[0:29]),
@@ -13300,7 +13300,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__20_ccff_tail));
 
 	cbx_1__1_ cbx_4__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__14_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__21_chanx_left_out[0:29]),
@@ -13326,7 +13326,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__21_ccff_tail));
 
 	cbx_1__1_ cbx_4__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__15_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__22_chanx_left_out[0:29]),
@@ -13352,7 +13352,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__22_ccff_tail));
 
 	cbx_1__1_ cbx_4__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__16_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__23_chanx_left_out[0:29]),
@@ -13378,7 +13378,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__23_ccff_tail));
 
 	cbx_1__1_ cbx_4__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__17_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__24_chanx_left_out[0:29]),
@@ -13404,7 +13404,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__24_ccff_tail));
 
 	cbx_1__1_ cbx_4__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__18_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__25_chanx_left_out[0:29]),
@@ -13430,7 +13430,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__25_ccff_tail));
 
 	cbx_1__1_ cbx_4__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__19_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__26_chanx_left_out[0:29]),
@@ -13456,7 +13456,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__26_ccff_tail));
 
 	cbx_1__1_ cbx_4__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__20_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__27_chanx_left_out[0:29]),
@@ -13482,7 +13482,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__27_ccff_tail));
 
 	cbx_1__1_ cbx_5__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__21_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__28_chanx_left_out[0:29]),
@@ -13508,7 +13508,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__28_ccff_tail));
 
 	cbx_1__1_ cbx_5__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__22_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__29_chanx_left_out[0:29]),
@@ -13534,7 +13534,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__29_ccff_tail));
 
 	cbx_1__1_ cbx_5__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__23_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__30_chanx_left_out[0:29]),
@@ -13560,7 +13560,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__30_ccff_tail));
 
 	cbx_1__1_ cbx_5__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__24_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__31_chanx_left_out[0:29]),
@@ -13586,7 +13586,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__31_ccff_tail));
 
 	cbx_1__1_ cbx_5__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__25_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__32_chanx_left_out[0:29]),
@@ -13612,7 +13612,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__32_ccff_tail));
 
 	cbx_1__1_ cbx_5__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__26_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__33_chanx_left_out[0:29]),
@@ -13638,7 +13638,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__33_ccff_tail));
 
 	cbx_1__1_ cbx_5__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__27_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__34_chanx_left_out[0:29]),
@@ -13664,7 +13664,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__34_ccff_tail));
 
 	cbx_1__1_ cbx_6__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__28_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__35_chanx_left_out[0:29]),
@@ -13690,7 +13690,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__35_ccff_tail));
 
 	cbx_1__1_ cbx_6__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__29_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__36_chanx_left_out[0:29]),
@@ -13716,7 +13716,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__36_ccff_tail));
 
 	cbx_1__1_ cbx_6__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__30_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__37_chanx_left_out[0:29]),
@@ -13742,7 +13742,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__37_ccff_tail));
 
 	cbx_1__1_ cbx_6__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__31_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__38_chanx_left_out[0:29]),
@@ -13768,7 +13768,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__38_ccff_tail));
 
 	cbx_1__1_ cbx_6__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__32_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__39_chanx_left_out[0:29]),
@@ -13794,7 +13794,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__39_ccff_tail));
 
 	cbx_1__1_ cbx_6__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__33_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__40_chanx_left_out[0:29]),
@@ -13820,7 +13820,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__40_ccff_tail));
 
 	cbx_1__1_ cbx_6__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__34_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__41_chanx_left_out[0:29]),
@@ -13846,7 +13846,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__41_ccff_tail));
 
 	cbx_1__1_ cbx_7__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__35_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__42_chanx_left_out[0:29]),
@@ -13872,7 +13872,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__42_ccff_tail));
 
 	cbx_1__1_ cbx_7__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__36_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__43_chanx_left_out[0:29]),
@@ -13898,7 +13898,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__43_ccff_tail));
 
 	cbx_1__1_ cbx_7__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__37_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__44_chanx_left_out[0:29]),
@@ -13924,7 +13924,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__44_ccff_tail));
 
 	cbx_1__1_ cbx_7__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__38_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__45_chanx_left_out[0:29]),
@@ -13950,7 +13950,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__45_ccff_tail));
 
 	cbx_1__1_ cbx_7__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__39_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__46_chanx_left_out[0:29]),
@@ -13976,7 +13976,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__46_ccff_tail));
 
 	cbx_1__1_ cbx_7__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__40_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__47_chanx_left_out[0:29]),
@@ -14002,7 +14002,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__47_ccff_tail));
 
 	cbx_1__1_ cbx_7__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__41_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__1__48_chanx_left_out[0:29]),
@@ -14028,7 +14028,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__48_ccff_tail));
 
 	cbx_1__1_ cbx_8__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__42_chanx_right_out[0:29]),
 		.chanx_right_in(sb_8__1__0_chanx_left_out[0:29]),
@@ -14054,7 +14054,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__49_ccff_tail));
 
 	cbx_1__1_ cbx_8__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__43_chanx_right_out[0:29]),
 		.chanx_right_in(sb_8__1__1_chanx_left_out[0:29]),
@@ -14080,7 +14080,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__50_ccff_tail));
 
 	cbx_1__1_ cbx_8__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__44_chanx_right_out[0:29]),
 		.chanx_right_in(sb_8__1__2_chanx_left_out[0:29]),
@@ -14106,7 +14106,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__51_ccff_tail));
 
 	cbx_1__1_ cbx_8__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__45_chanx_right_out[0:29]),
 		.chanx_right_in(sb_8__1__3_chanx_left_out[0:29]),
@@ -14132,7 +14132,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__52_ccff_tail));
 
 	cbx_1__1_ cbx_8__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__46_chanx_right_out[0:29]),
 		.chanx_right_in(sb_8__1__4_chanx_left_out[0:29]),
@@ -14158,7 +14158,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__53_ccff_tail));
 
 	cbx_1__1_ cbx_8__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__47_chanx_right_out[0:29]),
 		.chanx_right_in(sb_8__1__5_chanx_left_out[0:29]),
@@ -14184,7 +14184,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__54_ccff_tail));
 
 	cbx_1__1_ cbx_8__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__1__48_chanx_right_out[0:29]),
 		.chanx_right_in(sb_8__1__6_chanx_left_out[0:29]),
@@ -14210,7 +14210,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__1__55_ccff_tail));
 
 	cbx_1__8_ cbx_1__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_0__8__0_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__8__0_chanx_left_out[0:29]),
@@ -14240,7 +14240,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__8__0_ccff_tail));
 
 	cbx_1__8_ cbx_2__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__8__0_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__8__1_chanx_left_out[0:29]),
@@ -14270,7 +14270,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__8__1_ccff_tail));
 
 	cbx_1__8_ cbx_3__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__8__1_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__8__2_chanx_left_out[0:29]),
@@ -14300,7 +14300,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__8__2_ccff_tail));
 
 	cbx_1__8_ cbx_4__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__8__2_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__8__3_chanx_left_out[0:29]),
@@ -14330,7 +14330,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__8__3_ccff_tail));
 
 	cbx_1__8_ cbx_5__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__8__3_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__8__4_chanx_left_out[0:29]),
@@ -14360,7 +14360,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__8__4_ccff_tail));
 
 	cbx_1__8_ cbx_6__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__8__4_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__8__5_chanx_left_out[0:29]),
@@ -14390,7 +14390,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__8__5_ccff_tail));
 
 	cbx_1__8_ cbx_7__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__8__5_chanx_right_out[0:29]),
 		.chanx_right_in(sb_1__8__6_chanx_left_out[0:29]),
@@ -14420,7 +14420,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__8__6_ccff_tail));
 
 	cbx_1__8_ cbx_8__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chanx_left_in(sb_1__8__6_chanx_right_out[0:29]),
 		.chanx_right_in(sb_8__8__0_chanx_left_out[0:29]),
@@ -14450,7 +14450,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cbx_1__8__7_ccff_tail));
 
 	cby_0__1_ cby_0__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_0__0__0_chany_top_out[0:29]),
 		.chany_top_in(sb_0__1__0_chany_bottom_out[0:29]),
@@ -14464,7 +14464,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_0__1__0_ccff_tail));
 
 	cby_0__1_ cby_0__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_0__1__0_chany_top_out[0:29]),
 		.chany_top_in(sb_0__1__1_chany_bottom_out[0:29]),
@@ -14478,7 +14478,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_0__1__1_ccff_tail));
 
 	cby_0__1_ cby_0__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_0__1__1_chany_top_out[0:29]),
 		.chany_top_in(sb_0__1__2_chany_bottom_out[0:29]),
@@ -14492,7 +14492,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_0__1__2_ccff_tail));
 
 	cby_0__1_ cby_0__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_0__1__2_chany_top_out[0:29]),
 		.chany_top_in(sb_0__1__3_chany_bottom_out[0:29]),
@@ -14506,7 +14506,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_0__1__3_ccff_tail));
 
 	cby_0__1_ cby_0__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_0__1__3_chany_top_out[0:29]),
 		.chany_top_in(sb_0__1__4_chany_bottom_out[0:29]),
@@ -14520,7 +14520,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_0__1__4_ccff_tail));
 
 	cby_0__1_ cby_0__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_0__1__4_chany_top_out[0:29]),
 		.chany_top_in(sb_0__1__5_chany_bottom_out[0:29]),
@@ -14534,7 +14534,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_0__1__5_ccff_tail));
 
 	cby_0__1_ cby_0__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_0__1__5_chany_top_out[0:29]),
 		.chany_top_in(sb_0__1__6_chany_bottom_out[0:29]),
@@ -14548,7 +14548,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_0__1__6_ccff_tail));
 
 	cby_0__1_ cby_0__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_0__1__6_chany_top_out[0:29]),
 		.chany_top_in(sb_0__8__0_chany_bottom_out[0:29]),
@@ -14562,7 +14562,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_0__1__7_ccff_tail));
 
 	cby_1__1_ cby_1__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__0__0_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__0_chany_bottom_out[0:29]),
@@ -14588,7 +14588,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__0_ccff_tail));
 
 	cby_1__1_ cby_1__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__0_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__1_chany_bottom_out[0:29]),
@@ -14614,7 +14614,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__1_ccff_tail));
 
 	cby_1__1_ cby_1__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__1_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__2_chany_bottom_out[0:29]),
@@ -14640,7 +14640,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__2_ccff_tail));
 
 	cby_1__1_ cby_1__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__2_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__3_chany_bottom_out[0:29]),
@@ -14666,7 +14666,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__3_ccff_tail));
 
 	cby_1__1_ cby_1__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__3_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__4_chany_bottom_out[0:29]),
@@ -14692,7 +14692,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__4_ccff_tail));
 
 	cby_1__1_ cby_1__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__4_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__5_chany_bottom_out[0:29]),
@@ -14718,7 +14718,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__5_ccff_tail));
 
 	cby_1__1_ cby_1__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__5_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__6_chany_bottom_out[0:29]),
@@ -14744,7 +14744,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__6_ccff_tail));
 
 	cby_1__1_ cby_1__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__6_chany_top_out[0:29]),
 		.chany_top_in(sb_1__8__0_chany_bottom_out[0:29]),
@@ -14770,7 +14770,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__7_ccff_tail));
 
 	cby_1__1_ cby_2__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__0__1_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__7_chany_bottom_out[0:29]),
@@ -14796,7 +14796,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__8_ccff_tail));
 
 	cby_1__1_ cby_2__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__7_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__8_chany_bottom_out[0:29]),
@@ -14822,7 +14822,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__9_ccff_tail));
 
 	cby_1__1_ cby_2__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__8_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__9_chany_bottom_out[0:29]),
@@ -14848,7 +14848,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__10_ccff_tail));
 
 	cby_1__1_ cby_2__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__9_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__10_chany_bottom_out[0:29]),
@@ -14874,7 +14874,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__11_ccff_tail));
 
 	cby_1__1_ cby_2__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__10_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__11_chany_bottom_out[0:29]),
@@ -14900,7 +14900,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__12_ccff_tail));
 
 	cby_1__1_ cby_2__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__11_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__12_chany_bottom_out[0:29]),
@@ -14926,7 +14926,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__13_ccff_tail));
 
 	cby_1__1_ cby_2__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__12_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__13_chany_bottom_out[0:29]),
@@ -14952,7 +14952,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__14_ccff_tail));
 
 	cby_1__1_ cby_2__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__13_chany_top_out[0:29]),
 		.chany_top_in(sb_1__8__1_chany_bottom_out[0:29]),
@@ -14978,7 +14978,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__15_ccff_tail));
 
 	cby_1__1_ cby_3__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__0__2_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__14_chany_bottom_out[0:29]),
@@ -15004,7 +15004,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__16_ccff_tail));
 
 	cby_1__1_ cby_3__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__14_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__15_chany_bottom_out[0:29]),
@@ -15030,7 +15030,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__17_ccff_tail));
 
 	cby_1__1_ cby_3__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__15_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__16_chany_bottom_out[0:29]),
@@ -15056,7 +15056,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__18_ccff_tail));
 
 	cby_1__1_ cby_3__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__16_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__17_chany_bottom_out[0:29]),
@@ -15082,7 +15082,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__19_ccff_tail));
 
 	cby_1__1_ cby_3__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__17_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__18_chany_bottom_out[0:29]),
@@ -15108,7 +15108,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__20_ccff_tail));
 
 	cby_1__1_ cby_3__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__18_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__19_chany_bottom_out[0:29]),
@@ -15134,7 +15134,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__21_ccff_tail));
 
 	cby_1__1_ cby_3__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__19_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__20_chany_bottom_out[0:29]),
@@ -15160,7 +15160,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__22_ccff_tail));
 
 	cby_1__1_ cby_3__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__20_chany_top_out[0:29]),
 		.chany_top_in(sb_1__8__2_chany_bottom_out[0:29]),
@@ -15186,7 +15186,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__23_ccff_tail));
 
 	cby_1__1_ cby_4__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__0__3_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__21_chany_bottom_out[0:29]),
@@ -15212,7 +15212,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__24_ccff_tail));
 
 	cby_1__1_ cby_4__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__21_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__22_chany_bottom_out[0:29]),
@@ -15238,7 +15238,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__25_ccff_tail));
 
 	cby_1__1_ cby_4__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__22_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__23_chany_bottom_out[0:29]),
@@ -15264,7 +15264,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__26_ccff_tail));
 
 	cby_1__1_ cby_4__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__23_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__24_chany_bottom_out[0:29]),
@@ -15290,7 +15290,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__27_ccff_tail));
 
 	cby_1__1_ cby_4__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__24_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__25_chany_bottom_out[0:29]),
@@ -15316,7 +15316,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__28_ccff_tail));
 
 	cby_1__1_ cby_4__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__25_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__26_chany_bottom_out[0:29]),
@@ -15342,7 +15342,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__29_ccff_tail));
 
 	cby_1__1_ cby_4__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__26_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__27_chany_bottom_out[0:29]),
@@ -15368,7 +15368,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__30_ccff_tail));
 
 	cby_1__1_ cby_4__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__27_chany_top_out[0:29]),
 		.chany_top_in(sb_1__8__3_chany_bottom_out[0:29]),
@@ -15394,7 +15394,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__31_ccff_tail));
 
 	cby_1__1_ cby_5__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__0__4_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__28_chany_bottom_out[0:29]),
@@ -15420,7 +15420,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__32_ccff_tail));
 
 	cby_1__1_ cby_5__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__28_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__29_chany_bottom_out[0:29]),
@@ -15446,7 +15446,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__33_ccff_tail));
 
 	cby_1__1_ cby_5__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__29_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__30_chany_bottom_out[0:29]),
@@ -15472,7 +15472,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__34_ccff_tail));
 
 	cby_1__1_ cby_5__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__30_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__31_chany_bottom_out[0:29]),
@@ -15498,7 +15498,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__35_ccff_tail));
 
 	cby_1__1_ cby_5__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__31_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__32_chany_bottom_out[0:29]),
@@ -15524,7 +15524,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__36_ccff_tail));
 
 	cby_1__1_ cby_5__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__32_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__33_chany_bottom_out[0:29]),
@@ -15550,7 +15550,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__37_ccff_tail));
 
 	cby_1__1_ cby_5__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__33_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__34_chany_bottom_out[0:29]),
@@ -15576,7 +15576,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__38_ccff_tail));
 
 	cby_1__1_ cby_5__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__34_chany_top_out[0:29]),
 		.chany_top_in(sb_1__8__4_chany_bottom_out[0:29]),
@@ -15602,7 +15602,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__39_ccff_tail));
 
 	cby_1__1_ cby_6__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__0__5_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__35_chany_bottom_out[0:29]),
@@ -15628,7 +15628,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__40_ccff_tail));
 
 	cby_1__1_ cby_6__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__35_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__36_chany_bottom_out[0:29]),
@@ -15654,7 +15654,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__41_ccff_tail));
 
 	cby_1__1_ cby_6__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__36_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__37_chany_bottom_out[0:29]),
@@ -15680,7 +15680,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__42_ccff_tail));
 
 	cby_1__1_ cby_6__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__37_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__38_chany_bottom_out[0:29]),
@@ -15706,7 +15706,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__43_ccff_tail));
 
 	cby_1__1_ cby_6__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__38_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__39_chany_bottom_out[0:29]),
@@ -15732,7 +15732,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__44_ccff_tail));
 
 	cby_1__1_ cby_6__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__39_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__40_chany_bottom_out[0:29]),
@@ -15758,7 +15758,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__45_ccff_tail));
 
 	cby_1__1_ cby_6__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__40_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__41_chany_bottom_out[0:29]),
@@ -15784,7 +15784,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__46_ccff_tail));
 
 	cby_1__1_ cby_6__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__41_chany_top_out[0:29]),
 		.chany_top_in(sb_1__8__5_chany_bottom_out[0:29]),
@@ -15810,7 +15810,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__47_ccff_tail));
 
 	cby_1__1_ cby_7__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__0__6_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__42_chany_bottom_out[0:29]),
@@ -15836,7 +15836,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__48_ccff_tail));
 
 	cby_1__1_ cby_7__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__42_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__43_chany_bottom_out[0:29]),
@@ -15862,7 +15862,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__49_ccff_tail));
 
 	cby_1__1_ cby_7__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__43_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__44_chany_bottom_out[0:29]),
@@ -15888,7 +15888,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__50_ccff_tail));
 
 	cby_1__1_ cby_7__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__44_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__45_chany_bottom_out[0:29]),
@@ -15914,7 +15914,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__51_ccff_tail));
 
 	cby_1__1_ cby_7__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__45_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__46_chany_bottom_out[0:29]),
@@ -15940,7 +15940,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__52_ccff_tail));
 
 	cby_1__1_ cby_7__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__46_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__47_chany_bottom_out[0:29]),
@@ -15966,7 +15966,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__53_ccff_tail));
 
 	cby_1__1_ cby_7__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__47_chany_top_out[0:29]),
 		.chany_top_in(sb_1__1__48_chany_bottom_out[0:29]),
@@ -15992,7 +15992,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__54_ccff_tail));
 
 	cby_1__1_ cby_7__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_1__1__48_chany_top_out[0:29]),
 		.chany_top_in(sb_1__8__6_chany_bottom_out[0:29]),
@@ -16018,7 +16018,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_1__1__55_ccff_tail));
 
 	cby_8__1_ cby_8__1_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_8__0__0_chany_top_out[0:29]),
 		.chany_top_in(sb_8__1__0_chany_bottom_out[0:29]),
@@ -16048,7 +16048,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_8__1__0_ccff_tail));
 
 	cby_8__1_ cby_8__2_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_8__1__0_chany_top_out[0:29]),
 		.chany_top_in(sb_8__1__1_chany_bottom_out[0:29]),
@@ -16078,7 +16078,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_8__1__1_ccff_tail));
 
 	cby_8__1_ cby_8__3_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_8__1__1_chany_top_out[0:29]),
 		.chany_top_in(sb_8__1__2_chany_bottom_out[0:29]),
@@ -16108,7 +16108,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_8__1__2_ccff_tail));
 
 	cby_8__1_ cby_8__4_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_8__1__2_chany_top_out[0:29]),
 		.chany_top_in(sb_8__1__3_chany_bottom_out[0:29]),
@@ -16138,7 +16138,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_8__1__3_ccff_tail));
 
 	cby_8__1_ cby_8__5_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_8__1__3_chany_top_out[0:29]),
 		.chany_top_in(sb_8__1__4_chany_bottom_out[0:29]),
@@ -16168,7 +16168,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_8__1__4_ccff_tail));
 
 	cby_8__1_ cby_8__6_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_8__1__4_chany_top_out[0:29]),
 		.chany_top_in(sb_8__1__5_chany_bottom_out[0:29]),
@@ -16198,7 +16198,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_8__1__5_ccff_tail));
 
 	cby_8__1_ cby_8__7_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_8__1__5_chany_top_out[0:29]),
 		.chany_top_in(sb_8__1__6_chany_bottom_out[0:29]),
@@ -16228,7 +16228,7 @@ wire [0:29] sb_8__8__0_chany_bottom_out;
 		.ccff_tail(cby_8__1__6_ccff_tail));
 
 	cby_8__1_ cby_8__8_ (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.chany_bottom_in(sb_8__1__6_chany_top_out[0:29]),
 		.chany_top_in(sb_8__8__0_chany_bottom_out[0:29]),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_clb.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_clb.v
index 0c2ef08..23a0ab2 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_clb.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_clb.v
@@ -12,9 +12,9 @@
 `default_nettype none
 
 // ----- Verilog module for grid_clb -----
-module grid_clb(pReset,
+module grid_clb(prog_reset,
                 prog_clk,
-                Test_en,
+                scan_enable,
                 top_width_0_height_0_subtile_0__pin_I0_0_,
                 top_width_0_height_0_subtile_0__pin_I0_1_,
                 top_width_0_height_0_subtile_0__pin_I0i_0_,
@@ -74,11 +74,11 @@ module grid_clb(pReset,
                 bottom_width_0_height_0_subtile_0__pin_cout_0_,
                 ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- GLOBAL PORTS -----
-input [0:0] Test_en;
+input [0:0] scan_enable;
 //----- INPUT PORTS -----
 input [0:0] top_width_0_height_0_subtile_0__pin_I0_0_;
 //----- INPUT PORTS -----
@@ -211,9 +211,9 @@ output [0:0] ccff_tail;
 // ----- END Local output short connections -----
 
 	logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.clb_I0({top_width_0_height_0_subtile_0__pin_I0_0_, top_width_0_height_0_subtile_0__pin_I0_1_}),
 		.clb_I0i({top_width_0_height_0_subtile_0__pin_I0i_0_, top_width_0_height_0_subtile_0__pin_I0i_1_}),
 		.clb_I1({top_width_0_height_0_subtile_0__pin_I1_0_, top_width_0_height_0_subtile_0__pin_I1_1_}),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_bottom_bottom.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_bottom_bottom.v
index ae56398..d03dde9 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_bottom_bottom.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_bottom_bottom.v
@@ -12,12 +12,12 @@
 `default_nettype none
 
 // ----- Verilog module for grid_io_bottom_bottom -----
-module grid_io_bottom_bottom(IO_ISOL_N,
-                             pReset,
+module grid_io_bottom_bottom(isol_n,
+                             prog_reset,
                              prog_clk,
-                             gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-                             gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-                             gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+                             gfpga_pad_io_soc_in,
+                             gfpga_pad_io_soc_out,
+                             gfpga_pad_io_soc_dir,
                              top_width_0_height_0_subtile_0__pin_outpad_0_,
                              top_width_0_height_0_subtile_1__pin_outpad_0_,
                              top_width_0_height_0_subtile_2__pin_outpad_0_,
@@ -29,17 +29,17 @@ module grid_io_bottom_bottom(IO_ISOL_N,
                              top_width_0_height_0_subtile_3__pin_inpad_0_,
                              ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] IO_ISOL_N;
+input [0:0] isol_n;
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- GPIN PORTS -----
-input [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+input [0:3] gfpga_pad_io_soc_in;
 //----- GPOUT PORTS -----
-output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+output [0:3] gfpga_pad_io_soc_out;
 //----- GPOUT PORTS -----
-output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+output [0:3] gfpga_pad_io_soc_dir;
 //----- INPUT PORTS -----
 input [0:0] top_width_0_height_0_subtile_0__pin_outpad_0_;
 //----- INPUT PORTS -----
@@ -79,48 +79,48 @@ wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
 // ----- END Local output short connections -----
 
 	logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
 		.io_outpad(top_width_0_height_0_subtile_0__pin_outpad_0_),
 		.ccff_head(ccff_head),
 		.io_inpad(top_width_0_height_0_subtile_0__pin_inpad_0_),
 		.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
 
 	logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
 		.io_outpad(top_width_0_height_0_subtile_1__pin_outpad_0_),
 		.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
 		.io_inpad(top_width_0_height_0_subtile_1__pin_inpad_0_),
 		.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
 
 	logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
 		.io_outpad(top_width_0_height_0_subtile_2__pin_outpad_0_),
 		.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
 		.io_inpad(top_width_0_height_0_subtile_2__pin_inpad_0_),
 		.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
 
 	logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
 		.io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_),
 		.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
 		.io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_left_left.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_left_left.v
index aa5a5fc..b0d4ac2 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_left_left.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_left_left.v
@@ -12,12 +12,12 @@
 `default_nettype none
 
 // ----- Verilog module for grid_io_left_left -----
-module grid_io_left_left(IO_ISOL_N,
-                         pReset,
+module grid_io_left_left(isol_n,
+                         prog_reset,
                          prog_clk,
-                         gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-                         gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-                         gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+                         gfpga_pad_io_soc_in,
+                         gfpga_pad_io_soc_out,
+                         gfpga_pad_io_soc_dir,
                          right_width_0_height_0_subtile_0__pin_outpad_0_,
                          right_width_0_height_0_subtile_1__pin_outpad_0_,
                          right_width_0_height_0_subtile_2__pin_outpad_0_,
@@ -29,17 +29,17 @@ module grid_io_left_left(IO_ISOL_N,
                          right_width_0_height_0_subtile_3__pin_inpad_0_,
                          ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] IO_ISOL_N;
+input [0:0] isol_n;
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- GPIN PORTS -----
-input [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+input [0:3] gfpga_pad_io_soc_in;
 //----- GPOUT PORTS -----
-output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+output [0:3] gfpga_pad_io_soc_out;
 //----- GPOUT PORTS -----
-output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+output [0:3] gfpga_pad_io_soc_dir;
 //----- INPUT PORTS -----
 input [0:0] right_width_0_height_0_subtile_0__pin_outpad_0_;
 //----- INPUT PORTS -----
@@ -79,48 +79,48 @@ wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
 // ----- END Local output short connections -----
 
 	logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
 		.io_outpad(right_width_0_height_0_subtile_0__pin_outpad_0_),
 		.ccff_head(ccff_head),
 		.io_inpad(right_width_0_height_0_subtile_0__pin_inpad_0_),
 		.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
 
 	logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
 		.io_outpad(right_width_0_height_0_subtile_1__pin_outpad_0_),
 		.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
 		.io_inpad(right_width_0_height_0_subtile_1__pin_inpad_0_),
 		.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
 
 	logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
 		.io_outpad(right_width_0_height_0_subtile_2__pin_outpad_0_),
 		.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
 		.io_inpad(right_width_0_height_0_subtile_2__pin_inpad_0_),
 		.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
 
 	logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
 		.io_outpad(right_width_0_height_0_subtile_3__pin_outpad_0_),
 		.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
 		.io_inpad(right_width_0_height_0_subtile_3__pin_inpad_0_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_right_right.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_right_right.v
index 99419bc..b71a7c0 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_right_right.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_right_right.v
@@ -12,12 +12,12 @@
 `default_nettype none
 
 // ----- Verilog module for grid_io_right_right -----
-module grid_io_right_right(IO_ISOL_N,
-                           pReset,
+module grid_io_right_right(isol_n,
+                           prog_reset,
                            prog_clk,
-                           gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-                           gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-                           gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+                           gfpga_pad_io_soc_in,
+                           gfpga_pad_io_soc_out,
+                           gfpga_pad_io_soc_dir,
                            left_width_0_height_0_subtile_0__pin_outpad_0_,
                            left_width_0_height_0_subtile_1__pin_outpad_0_,
                            left_width_0_height_0_subtile_2__pin_outpad_0_,
@@ -29,17 +29,17 @@ module grid_io_right_right(IO_ISOL_N,
                            left_width_0_height_0_subtile_3__pin_inpad_0_,
                            ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] IO_ISOL_N;
+input [0:0] isol_n;
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- GPIN PORTS -----
-input [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+input [0:3] gfpga_pad_io_soc_in;
 //----- GPOUT PORTS -----
-output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+output [0:3] gfpga_pad_io_soc_out;
 //----- GPOUT PORTS -----
-output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+output [0:3] gfpga_pad_io_soc_dir;
 //----- INPUT PORTS -----
 input [0:0] left_width_0_height_0_subtile_0__pin_outpad_0_;
 //----- INPUT PORTS -----
@@ -79,48 +79,48 @@ wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
 // ----- END Local output short connections -----
 
 	logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
 		.io_outpad(left_width_0_height_0_subtile_0__pin_outpad_0_),
 		.ccff_head(ccff_head),
 		.io_inpad(left_width_0_height_0_subtile_0__pin_inpad_0_),
 		.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
 
 	logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
 		.io_outpad(left_width_0_height_0_subtile_1__pin_outpad_0_),
 		.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
 		.io_inpad(left_width_0_height_0_subtile_1__pin_inpad_0_),
 		.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
 
 	logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
 		.io_outpad(left_width_0_height_0_subtile_2__pin_outpad_0_),
 		.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
 		.io_inpad(left_width_0_height_0_subtile_2__pin_inpad_0_),
 		.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
 
 	logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
 		.io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_),
 		.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
 		.io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_top_top.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_top_top.v
index 72db158..0155621 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_top_top.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/grid_io_top_top.v
@@ -12,12 +12,12 @@
 `default_nettype none
 
 // ----- Verilog module for grid_io_top_top -----
-module grid_io_top_top(IO_ISOL_N,
-                       pReset,
+module grid_io_top_top(isol_n,
+                       prog_reset,
                        prog_clk,
-                       gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-                       gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-                       gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+                       gfpga_pad_io_soc_in,
+                       gfpga_pad_io_soc_out,
+                       gfpga_pad_io_soc_dir,
                        bottom_width_0_height_0_subtile_0__pin_outpad_0_,
                        bottom_width_0_height_0_subtile_1__pin_outpad_0_,
                        bottom_width_0_height_0_subtile_2__pin_outpad_0_,
@@ -29,17 +29,17 @@ module grid_io_top_top(IO_ISOL_N,
                        bottom_width_0_height_0_subtile_3__pin_inpad_0_,
                        ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] IO_ISOL_N;
+input [0:0] isol_n;
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- GPIN PORTS -----
-input [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+input [0:3] gfpga_pad_io_soc_in;
 //----- GPOUT PORTS -----
-output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+output [0:3] gfpga_pad_io_soc_out;
 //----- GPOUT PORTS -----
-output [0:3] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+output [0:3] gfpga_pad_io_soc_dir;
 //----- INPUT PORTS -----
 input [0:0] bottom_width_0_height_0_subtile_0__pin_outpad_0_;
 //----- INPUT PORTS -----
@@ -79,48 +79,48 @@ wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
 // ----- END Local output short connections -----
 
 	logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
 		.io_outpad(bottom_width_0_height_0_subtile_0__pin_outpad_0_),
 		.ccff_head(ccff_head),
 		.io_inpad(bottom_width_0_height_0_subtile_0__pin_inpad_0_),
 		.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
 
 	logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
 		.io_outpad(bottom_width_0_height_0_subtile_1__pin_outpad_0_),
 		.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
 		.io_inpad(bottom_width_0_height_0_subtile_1__pin_inpad_0_),
 		.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
 
 	logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
 		.io_outpad(bottom_width_0_height_0_subtile_2__pin_outpad_0_),
 		.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
 		.io_inpad(bottom_width_0_height_0_subtile_2__pin_inpad_0_),
 		.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
 
 	logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
 		.io_outpad(bottom_width_0_height_0_subtile_3__pin_outpad_0_),
 		.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
 		.io_inpad(bottom_width_0_height_0_subtile_3__pin_inpad_0_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_clb_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_clb_.v
index 83679b0..8372aa4 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_clb_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_clb_.v
@@ -12,9 +12,9 @@
 `default_nettype none
 
 // ----- Verilog module for logical_tile_clb_mode_clb_ -----
-module logical_tile_clb_mode_clb_(pReset,
+module logical_tile_clb_mode_clb_(prog_reset,
                                   prog_clk,
-                                  Test_en,
+                                  scan_enable,
                                   clb_I0,
                                   clb_I0i,
                                   clb_I1,
@@ -43,11 +43,11 @@ module logical_tile_clb_mode_clb_(pReset,
                                   clb_cout,
                                   ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- GLOBAL PORTS -----
-input [0:0] Test_en;
+input [0:0] scan_enable;
 //----- INPUT PORTS -----
 input [0:1] clb_I0;
 //----- INPUT PORTS -----
@@ -254,9 +254,9 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
 // ----- END Local output short connections -----
 
 	logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.fle_in({direct_interc_19_out, direct_interc_20_out, direct_interc_21_out, direct_interc_22_out}),
 		.fle_reg_in(direct_interc_23_out),
 		.fle_sc_in(direct_interc_24_out),
@@ -271,9 +271,9 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
 		.ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail));
 
 	logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.fle_in({direct_interc_28_out, direct_interc_29_out, direct_interc_30_out, direct_interc_31_out}),
 		.fle_reg_in(direct_interc_32_out),
 		.fle_sc_in(direct_interc_33_out),
@@ -288,9 +288,9 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
 		.ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail));
 
 	logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.fle_in({direct_interc_37_out, direct_interc_38_out, direct_interc_39_out, direct_interc_40_out}),
 		.fle_reg_in(direct_interc_41_out),
 		.fle_sc_in(direct_interc_42_out),
@@ -305,9 +305,9 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
 		.ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail));
 
 	logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.fle_in({direct_interc_46_out, direct_interc_47_out, direct_interc_48_out, direct_interc_49_out}),
 		.fle_reg_in(direct_interc_50_out),
 		.fle_sc_in(direct_interc_51_out),
@@ -322,9 +322,9 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
 		.ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail));
 
 	logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.fle_in({direct_interc_55_out, direct_interc_56_out, direct_interc_57_out, direct_interc_58_out}),
 		.fle_reg_in(direct_interc_59_out),
 		.fle_sc_in(direct_interc_60_out),
@@ -339,9 +339,9 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
 		.ccff_tail(logical_tile_clb_mode_default__fle_4_ccff_tail));
 
 	logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.fle_in({direct_interc_64_out, direct_interc_65_out, direct_interc_66_out, direct_interc_67_out}),
 		.fle_reg_in(direct_interc_68_out),
 		.fle_sc_in(direct_interc_69_out),
@@ -356,9 +356,9 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
 		.ccff_tail(logical_tile_clb_mode_default__fle_5_ccff_tail));
 
 	logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.fle_in({direct_interc_73_out, direct_interc_74_out, direct_interc_75_out, direct_interc_76_out}),
 		.fle_reg_in(direct_interc_77_out),
 		.fle_sc_in(direct_interc_78_out),
@@ -373,9 +373,9 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
 		.ccff_tail(logical_tile_clb_mode_default__fle_6_ccff_tail));
 
 	logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.fle_in({direct_interc_82_out, direct_interc_83_out, direct_interc_84_out, direct_interc_85_out}),
 		.fle_reg_in(direct_interc_86_out),
 		.fle_sc_in(direct_interc_87_out),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle.v
index cba4e41..a0bfaf6 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle.v
@@ -12,9 +12,9 @@
 `default_nettype none
 
 // ----- Verilog module for logical_tile_clb_mode_default__fle -----
-module logical_tile_clb_mode_default__fle(pReset,
+module logical_tile_clb_mode_default__fle(prog_reset,
                                           prog_clk,
-                                          Test_en,
+                                          scan_enable,
                                           fle_in,
                                           fle_reg_in,
                                           fle_sc_in,
@@ -28,11 +28,11 @@ module logical_tile_clb_mode_default__fle(pReset,
                                           fle_cout,
                                           ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- GLOBAL PORTS -----
-input [0:0] Test_en;
+input [0:0] scan_enable;
 //----- INPUT PORTS -----
 input [0:3] fle_in;
 //----- INPUT PORTS -----
@@ -96,9 +96,9 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_
 // ----- END Local output short connections -----
 
 	logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.fabric_in({direct_interc_5_out, direct_interc_6_out, direct_interc_7_out, direct_interc_8_out}),
 		.fabric_reg_in(direct_interc_9_out),
 		.fabric_sc_in(direct_interc_10_out),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
index c66b8ca..b9b3db8 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
@@ -12,9 +12,9 @@
 `default_nettype none
 
 // ----- Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric -----
-module logical_tile_clb_mode_default__fle_mode_physical__fabric(pReset,
+module logical_tile_clb_mode_default__fle_mode_physical__fabric(prog_reset,
                                                                 prog_clk,
-                                                                Test_en,
+                                                                scan_enable,
                                                                 fabric_in,
                                                                 fabric_reg_in,
                                                                 fabric_sc_in,
@@ -28,11 +28,11 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric(pReset,
                                                                 fabric_cout,
                                                                 ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- GLOBAL PORTS -----
-input [0:0] Test_en;
+input [0:0] scan_enable;
 //----- INPUT PORTS -----
 input [0:3] fabric_in;
 //----- INPUT PORTS -----
@@ -112,7 +112,7 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail;
 // ----- END Local output short connections -----
 
 	logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.frac_logic_in({direct_interc_3_out, direct_interc_4_out, direct_interc_5_out, direct_interc_6_out}),
 		.frac_logic_cin(direct_interc_7_out),
@@ -122,7 +122,7 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail;
 		.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail));
 
 	logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.ff_D(mux_tree_size2_2_out),
 		.ff_DI(direct_interc_8_out),
 		.ff_reset(direct_interc_9_out),
@@ -130,7 +130,7 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail;
 		.ff_clk(direct_interc_10_out));
 
 	logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
-		.Test_en(Test_en),
+		.scan_enable(scan_enable),
 		.ff_D(mux_tree_size2_3_out),
 		.ff_DI(direct_interc_11_out),
 		.ff_reset(direct_interc_12_out),
@@ -162,28 +162,28 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail;
 		.out(mux_tree_size2_3_out));
 
 	mux_tree_size2_mem mem_fabric_out_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail),
 		.ccff_tail(mux_tree_size2_mem_0_ccff_tail),
 		.mem_out(mux_tree_size2_0_sram[0:1]));
 
 	mux_tree_size2_mem mem_fabric_out_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_size2_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_size2_mem_1_ccff_tail),
 		.mem_out(mux_tree_size2_1_sram[0:1]));
 
 	mux_tree_size2_mem mem_ff_0_D_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_size2_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_size2_mem_2_ccff_tail),
 		.mem_out(mux_tree_size2_2_sram[0:1]));
 
 	mux_tree_size2_mem mem_ff_1_D_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_size2_mem_2_ccff_tail),
 		.ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v
index d6186fb..053a91b 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v
@@ -11,14 +11,14 @@
 `default_nettype none
 
 // ----- Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff -----
-module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff(Test_en,
+module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff(scan_enable,
                                                                                  ff_D,
                                                                                  ff_DI,
                                                                                  ff_reset,
                                                                                  ff_Q,
                                                                                  ff_clk);
 //----- GLOBAL PORTS -----
-input [0:0] Test_en;
+input [0:0] scan_enable;
 //----- INPUT PORTS -----
 input [0:0] ff_D;
 //----- INPUT PORTS -----
@@ -50,7 +50,7 @@ wire [0:0] ff_clk;
 // ----- END Local output short connections -----
 
 	sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ (
-		.SCE(Test_en),
+		.SCE(scan_enable),
 		.D(ff_D),
 		.SCD(ff_DI),
 		.RESET_B(ff_reset),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v
index 8ad3aa4..5e450f8 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v
@@ -12,7 +12,7 @@
 `default_nettype none
 
 // ----- Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic -----
-module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic(pReset,
+module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic(prog_reset,
                                                                                          prog_clk,
                                                                                          frac_logic_in,
                                                                                          frac_logic_cin,
@@ -21,7 +21,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
                                                                                          frac_logic_cout,
                                                                                          ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -73,7 +73,7 @@ wire [0:0] mux_tree_size2_mem_0_ccff_tail;
 // ----- END Local output short connections -----
 
 	logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.frac_lut4_in({direct_interc_2_out, direct_interc_3_out, mux_tree_size2_1_out, direct_interc_4_out}),
 		.ccff_head(ccff_head),
@@ -101,14 +101,14 @@ wire [0:0] mux_tree_size2_mem_0_ccff_tail;
 		.out(mux_tree_size2_1_out));
 
 	mux_tree_size2_mem mem_frac_logic_out_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail),
 		.ccff_tail(mux_tree_size2_mem_0_ccff_tail),
 		.mem_out(mux_tree_size2_0_sram[0:1]));
 
 	mux_tree_size2_mem mem_frac_lut4_0_in_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_size2_mem_0_ccff_tail),
 		.ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v
index e90f948..e9404e2 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v
@@ -11,7 +11,7 @@
 `default_nettype none
 
 // ----- Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 -----
-module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4(pReset,
+module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4(prog_reset,
                                                                                                                  prog_clk,
                                                                                                                  frac_lut4_in,
                                                                                                                  ccff_head,
@@ -20,7 +20,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
                                                                                                                  frac_lut4_lut4_out,
                                                                                                                  ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -69,7 +69,7 @@ wire [0:15] frac_lut4_0_sram;
 		.lut4_out(frac_lut4_lut4_out));
 
 	frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(ccff_head),
 		.ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_io_mode_io_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_io_mode_io_.v
index a2d5d55..c1a102c 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_io_mode_io_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_io_mode_io_.v
@@ -12,28 +12,28 @@
 `default_nettype none
 
 // ----- Verilog module for logical_tile_io_mode_io_ -----
-module logical_tile_io_mode_io_(IO_ISOL_N,
-                                pReset,
+module logical_tile_io_mode_io_(isol_n,
+                                prog_reset,
                                 prog_clk,
-                                gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-                                gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-                                gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+                                gfpga_pad_io_soc_in,
+                                gfpga_pad_io_soc_out,
+                                gfpga_pad_io_soc_dir,
                                 io_outpad,
                                 ccff_head,
                                 io_inpad,
                                 ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] IO_ISOL_N;
+input [0:0] isol_n;
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- GPIN PORTS -----
-input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+input [0:0] gfpga_pad_io_soc_in;
 //----- GPOUT PORTS -----
-output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+output [0:0] gfpga_pad_io_soc_out;
 //----- GPOUT PORTS -----
-output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+output [0:0] gfpga_pad_io_soc_dir;
 //----- INPUT PORTS -----
 input [0:0] io_outpad;
 //----- INPUT PORTS -----
@@ -62,12 +62,12 @@ wire [0:0] logical_tile_io_mode_physical__iopad_0_iopad_inpad;
 // ----- END Local output short connections -----
 
 	logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
-		.IO_ISOL_N(IO_ISOL_N),
-		.pReset(pReset),
+		.isol_n(isol_n),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
-		.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
+		.gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
+		.gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
+		.gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
 		.iopad_outpad(direct_interc_1_out),
 		.ccff_head(ccff_head),
 		.iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_io_mode_physical__iopad.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_io_mode_physical__iopad.v
index 400532e..b262038 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_io_mode_physical__iopad.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/lb/logical_tile_io_mode_physical__iopad.v
@@ -11,28 +11,28 @@
 `default_nettype none
 
 // ----- Verilog module for logical_tile_io_mode_physical__iopad -----
-module logical_tile_io_mode_physical__iopad(IO_ISOL_N,
-                                            pReset,
+module logical_tile_io_mode_physical__iopad(isol_n,
+                                            prog_reset,
                                             prog_clk,
-                                            gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-                                            gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-                                            gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+                                            gfpga_pad_io_soc_in,
+                                            gfpga_pad_io_soc_out,
+                                            gfpga_pad_io_soc_dir,
                                             iopad_outpad,
                                             ccff_head,
                                             iopad_inpad,
                                             ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] IO_ISOL_N;
+input [0:0] isol_n;
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- GPIN PORTS -----
-input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
+input [0:0] gfpga_pad_io_soc_in;
 //----- GPOUT PORTS -----
-output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
+output [0:0] gfpga_pad_io_soc_out;
 //----- GPOUT PORTS -----
-output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+output [0:0] gfpga_pad_io_soc_dir;
 //----- INPUT PORTS -----
 input [0:0] iopad_outpad;
 //----- INPUT PORTS -----
@@ -52,28 +52,28 @@ wire [0:0] iopad_inpad;
 //----- END Registered ports -----
 
 
-wire [0:0] EMBEDDED_IO_HD_0_en;
+wire [0:0] io_0_en;
 
 // ----- BEGIN Local short connections -----
 // ----- END Local short connections -----
 // ----- BEGIN Local output short connections -----
 // ----- END Local output short connections -----
 
-	EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
-		.IO_ISOL_N(IO_ISOL_N),
-		.SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
-		.SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
-		.SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
+	io io_0_ (
+		.IO_ISOL_N(isol_n),
+		.SOC_IN(gfpga_pad_io_soc_in),
+		.SOC_OUT(gfpga_pad_io_soc_out),
+		.SOC_DIR(gfpga_pad_io_soc_dir),
 		.FPGA_OUT(iopad_outpad),
-		.FPGA_DIR(EMBEDDED_IO_HD_0_en),
+		.FPGA_DIR(io_0_en),
 		.FPGA_IN(iopad_inpad));
 
-	EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
-		.pReset(pReset),
+	io_sky130_fd_sc_hd__dfrtp_1_mem io_sky130_fd_sc_hd__dfrtp_1_mem (
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(ccff_head),
 		.ccff_tail(ccff_tail),
-		.mem_out(EMBEDDED_IO_HD_0_en));
+		.mem_out(io_0_en));
 
 endmodule
 // ----- END Verilog module for logical_tile_io_mode_physical__iopad -----
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cbx_1__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cbx_1__0_.v
index 7b1b6b7..08132d4 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cbx_1__0_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cbx_1__0_.v
@@ -11,7 +11,7 @@
 `default_nettype none
 
 // ----- Verilog module for cbx_1__0_ -----
-module cbx_1__0_(pReset,
+module cbx_1__0_(prog_reset,
                  prog_clk,
                  chanx_left_in,
                  chanx_right_in,
@@ -24,7 +24,7 @@ module cbx_1__0_(pReset,
                  bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_,
                  ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -338,28 +338,28 @@ wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail;
 		.out(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_));
 
 	mux_tree_tapbuf_size12_mem mem_top_ipin_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(ccff_head),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_0_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_top_ipin_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_1_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_top_ipin_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_2_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_top_ipin_3 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
 		.ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cbx_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cbx_1__1_.v
index f72e28e..62bde07 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cbx_1__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cbx_1__1_.v
@@ -11,7 +11,7 @@
 `default_nettype none
 
 // ----- Verilog module for cbx_1__1_ -----
-module cbx_1__1_(pReset,
+module cbx_1__1_(prog_reset,
                  prog_clk,
                  chanx_left_in,
                  chanx_right_in,
@@ -36,7 +36,7 @@ module cbx_1__1_(pReset,
                  bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_,
                  ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -434,56 +434,56 @@ wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail;
 		.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_));
 
 	mux_tree_tapbuf_size12_mem mem_top_ipin_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(ccff_head),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_0_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_top_ipin_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_1_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_top_ipin_4 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_2_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_top_ipin_6 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_3_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_top_ipin_8 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_4_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_top_ipin_10 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_5_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_top_ipin_12 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_6_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_top_ipin_14 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
@@ -538,56 +538,56 @@ wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail;
 		.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_));
 
 	mux_tree_tapbuf_size10_mem mem_top_ipin_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_top_ipin_3 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_top_ipin_5 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_top_ipin_7 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_top_ipin_9 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_top_ipin_11 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_top_ipin_13 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_top_ipin_15 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
 		.ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cbx_1__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cbx_1__8_.v
index 5dd04ca..9d2f679 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cbx_1__8_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cbx_1__8_.v
@@ -11,7 +11,7 @@
 `default_nettype none
 
 // ----- Verilog module for cbx_1__8_ -----
-module cbx_1__8_(pReset,
+module cbx_1__8_(prog_reset,
                  prog_clk,
                  chanx_left_in,
                  chanx_right_in,
@@ -40,7 +40,7 @@ module cbx_1__8_(pReset,
                  bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_,
                  ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -482,84 +482,84 @@ wire [0:0] mux_tree_tapbuf_size12_mem_9_ccff_tail;
 		.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_0_));
 
 	mux_tree_tapbuf_size12_mem mem_bottom_ipin_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(ccff_head),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_0_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_bottom_ipin_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_1_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_bottom_ipin_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_2_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_bottom_ipin_3 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_3_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_top_ipin_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_4_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_top_ipin_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_5_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_top_ipin_4 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_6_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_top_ipin_6 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_7_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_top_ipin_8 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_8_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_top_ipin_10 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_9_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_top_ipin_12 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_10_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_top_ipin_14 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail),
@@ -614,56 +614,56 @@ wire [0:0] mux_tree_tapbuf_size12_mem_9_ccff_tail;
 		.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_));
 
 	mux_tree_tapbuf_size10_mem mem_top_ipin_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_top_ipin_3 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_top_ipin_5 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_top_ipin_7 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_top_ipin_9 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_top_ipin_11 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_top_ipin_13 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_top_ipin_15 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail),
 		.ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cby_0__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cby_0__1_.v
index 676a6aa..2b373cf 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cby_0__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cby_0__1_.v
@@ -11,7 +11,7 @@
 `default_nettype none
 
 // ----- Verilog module for cby_0__1_ -----
-module cby_0__1_(pReset,
+module cby_0__1_(prog_reset,
                  prog_clk,
                  chany_bottom_in,
                  chany_top_in,
@@ -24,7 +24,7 @@ module cby_0__1_(pReset,
                  left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_,
                  ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -338,28 +338,28 @@ wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail;
 		.out(left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_));
 
 	mux_tree_tapbuf_size12_mem mem_right_ipin_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(ccff_head),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_0_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_right_ipin_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_1_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_right_ipin_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_2_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_right_ipin_3 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
 		.ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cby_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cby_1__1_.v
index 1e53e9e..66e52f2 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cby_1__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cby_1__1_.v
@@ -11,7 +11,7 @@
 `default_nettype none
 
 // ----- Verilog module for cby_1__1_ -----
-module cby_1__1_(pReset,
+module cby_1__1_(prog_reset,
                  prog_clk,
                  chany_bottom_in,
                  chany_top_in,
@@ -36,7 +36,7 @@ module cby_1__1_(pReset,
                  left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_,
                  ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -434,56 +434,56 @@ wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail;
 		.out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_));
 
 	mux_tree_tapbuf_size12_mem mem_right_ipin_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(ccff_head),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_0_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_right_ipin_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_1_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_right_ipin_4 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_2_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_right_ipin_6 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_3_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_right_ipin_8 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_4_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_right_ipin_10 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_5_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_right_ipin_12 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_6_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_right_ipin_14 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
@@ -538,56 +538,56 @@ wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail;
 		.out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_));
 
 	mux_tree_tapbuf_size10_mem mem_right_ipin_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_right_ipin_3 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_right_ipin_5 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_right_ipin_7 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_right_ipin_9 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_right_ipin_11 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_right_ipin_13 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_right_ipin_15 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
 		.ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cby_8__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cby_8__1_.v
index 2f01006..aa72dbd 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cby_8__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/cby_8__1_.v
@@ -11,7 +11,7 @@
 `default_nettype none
 
 // ----- Verilog module for cby_8__1_ -----
-module cby_8__1_(pReset,
+module cby_8__1_(prog_reset,
                  prog_clk,
                  chany_bottom_in,
                  chany_top_in,
@@ -40,7 +40,7 @@ module cby_8__1_(pReset,
                  left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_,
                  ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -482,84 +482,84 @@ wire [0:0] mux_tree_tapbuf_size12_mem_9_ccff_tail;
 		.out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_));
 
 	mux_tree_tapbuf_size12_mem mem_left_ipin_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(ccff_head),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_0_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_left_ipin_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_1_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_left_ipin_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_2_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_left_ipin_3 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_3_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_right_ipin_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_4_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_right_ipin_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_5_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_right_ipin_4 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_6_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_right_ipin_6 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_7_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_right_ipin_8 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_8_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_right_ipin_10 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_9_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_right_ipin_12 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_10_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_right_ipin_14 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail),
@@ -614,56 +614,56 @@ wire [0:0] mux_tree_tapbuf_size12_mem_9_ccff_tail;
 		.out(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_));
 
 	mux_tree_tapbuf_size10_mem mem_right_ipin_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_right_ipin_3 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_right_ipin_5 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_right_ipin_7 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_right_ipin_9 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_right_ipin_11 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_right_ipin_13 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_right_ipin_15 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail),
 		.ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_0__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_0__0_.v
index 6b894fa..2967834 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_0__0_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_0__0_.v
@@ -11,7 +11,7 @@
 `default_nettype none
 
 // ----- Verilog module for sb_0__0_ -----
-module sb_0__0_(pReset,
+module sb_0__0_(prog_reset,
                 prog_clk,
                 chany_top_in,
                 top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
@@ -28,7 +28,7 @@ module sb_0__0_(pReset,
                 chanx_right_out,
                 ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -302,28 +302,28 @@ wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
 		.out(chanx_right_out[3]));
 
 	mux_tree_tapbuf_size3_mem mem_top_track_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(ccff_head),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_top_track_6 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_6 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@@ -522,224 +522,224 @@ wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
 		.out(chanx_right_out[25]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_4 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_8 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_10 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_12 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_14 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_16 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_18 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_28 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_8_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_30 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_9_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_32 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_10_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_34 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_11_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_44 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_12_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_46 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_13_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_48 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_14_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_50 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_15_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_16_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_4 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_17_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_8 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_18_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_10 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_19_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_12 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_20_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_14 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_21_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_16 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_22_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_18 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_23_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_28 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_24_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_30 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_25_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_32 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_26_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_34 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_27_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_44 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_28_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_28_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_46 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_28_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_29_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_29_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_48 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_29_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_30_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_30_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_50 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_30_ccff_tail),
 		.ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_0__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_0__1_.v
index 22f060a..b5f3785 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_0__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_0__1_.v
@@ -11,7 +11,7 @@
 `default_nettype none
 
 // ----- Verilog module for sb_0__1_ -----
-module sb_0__1_(pReset,
+module sb_0__1_(prog_reset,
                 prog_clk,
                 chany_top_in,
                 top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
@@ -38,7 +38,7 @@ module sb_0__1_(pReset,
                 chany_bottom_out,
                 ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -440,35 +440,35 @@ wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail;
 		.out(chany_bottom_out[5]));
 
 	mux_tree_tapbuf_size7_mem mem_top_track_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(ccff_head),
 		.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size7_0_sram[0:2]));
 
 	mux_tree_tapbuf_size7_mem mem_top_track_6 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size7_1_sram[0:2]));
 
 	mux_tree_tapbuf_size7_mem mem_top_track_10 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size7_2_sram[0:2]));
 
 	mux_tree_tapbuf_size7_mem mem_bottom_track_7 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size7_3_sram[0:2]));
 
 	mux_tree_tapbuf_size7_mem mem_bottom_track_11 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
@@ -547,84 +547,84 @@ wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail;
 		.out(chany_bottom_out[14]));
 
 	mux_tree_tapbuf_size6_mem mem_top_track_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_top_track_4 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_top_track_12 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_2_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_top_track_20 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_3_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_right_track_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_4_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_right_track_6 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_5_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_right_track_8 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_6_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_bottom_track_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_7_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_bottom_track_5 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_8_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_bottom_track_13 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_9_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_bottom_track_21 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_10_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_bottom_track_29 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail),
@@ -667,42 +667,42 @@ wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail;
 		.out(chany_bottom_out[18]));
 
 	mux_tree_tapbuf_size5_mem mem_top_track_28 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_0_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_right_track_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_1_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_right_track_4 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_2_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_right_track_10 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_3_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_bottom_track_3 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_4_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_bottom_track_37 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
@@ -769,70 +769,70 @@ wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail;
 		.out(chany_bottom_out[22]));
 
 	mux_tree_tapbuf_size4_mem mem_top_track_36 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_top_track_52 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_right_track_12 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_right_track_14 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_right_track_16 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_4_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_right_track_18 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_5_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_right_track_20 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_6_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_right_track_22 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_7_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_7_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_right_track_36 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_8_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_8_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_bottom_track_45 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_9_ccff_tail),
@@ -893,63 +893,63 @@ wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail;
 		.out(chany_bottom_out[26]));
 
 	mux_tree_tapbuf_size3_mem mem_top_track_44 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_24 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_26 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_28 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_30 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_32 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_5_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_34 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_6_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_50 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_7_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_bottom_track_53 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_9_ccff_tail),
 		.ccff_tail(ccff_tail),
@@ -1004,56 +1004,56 @@ wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail;
 		.out(chanx_right_out[28]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_38 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_8_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_40 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_44 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_46 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_48 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_52 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_54 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_56 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_0__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_0__8_.v
index 3002d9f..fb3e78f 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_0__8_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_0__8_.v
@@ -11,7 +11,7 @@
 `default_nettype none
 
 // ----- Verilog module for sb_0__8_ -----
-module sb_0__8_(pReset,
+module sb_0__8_(prog_reset,
                 prog_clk,
                 chanx_right_in,
                 right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
@@ -36,7 +36,7 @@ module sb_0__8_(pReset,
                 chany_bottom_out,
                 ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -326,42 +326,42 @@ wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail;
 		.out(chanx_right_out[5]));
 
 	mux_tree_tapbuf_size5_mem mem_right_track_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(ccff_head),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_0_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_right_track_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_1_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_right_track_4 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_2_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_right_track_6 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_3_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_right_track_8 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_4_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_right_track_10 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
@@ -446,91 +446,91 @@ wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail;
 		.out(chany_bottom_out[3]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_12 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_14 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_16 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_28 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_30 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_32 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_5_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_34 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_6_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_44 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_7_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_46 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_8_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_48 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_9_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_58 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_10_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_bottom_track_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_11_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_bottom_track_7 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail),
@@ -711,203 +711,203 @@ wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail;
 		.out(chany_bottom_out[25]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_18 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_20 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_22 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_24 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_26 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_36 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_38 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_40 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_42 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_8_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_50 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_9_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_52 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_10_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_54 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_11_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_right_track_56 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_12_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_3 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_13_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_5 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_14_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_9 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_15_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_11 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_16_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_13 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_17_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_15 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_18_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_17 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_19_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_19 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_20_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_29 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_21_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_31 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_22_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_33 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_23_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_35 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_24_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_45 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_25_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_47 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_26_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_49 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_27_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_51 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail),
 		.ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_1__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_1__0_.v
index 12f412b..1dc3264 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_1__0_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_1__0_.v
@@ -11,7 +11,7 @@
 `default_nettype none
 
 // ----- Verilog module for sb_1__0_ -----
-module sb_1__0_(pReset,
+module sb_1__0_(prog_reset,
                 prog_clk,
                 chany_top_in,
                 top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
@@ -38,7 +38,7 @@ module sb_1__0_(pReset,
                 chanx_left_out,
                 ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -446,35 +446,35 @@ wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail;
 		.out(chanx_left_out[5]));
 
 	mux_tree_tapbuf_size7_mem mem_top_track_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(ccff_head),
 		.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size7_0_sram[0:2]));
 
 	mux_tree_tapbuf_size7_mem mem_right_track_6 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size7_1_sram[0:2]));
 
 	mux_tree_tapbuf_size7_mem mem_right_track_10 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size7_2_sram[0:2]));
 
 	mux_tree_tapbuf_size7_mem mem_left_track_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size7_3_sram[0:2]));
 
 	mux_tree_tapbuf_size7_mem mem_left_track_11 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
@@ -559,91 +559,91 @@ wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail;
 		.out(chanx_left_out[14]));
 
 	mux_tree_tapbuf_size6_mem mem_top_track_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_top_track_6 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_top_track_8 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_2_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_right_track_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_3_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_right_track_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_4_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_right_track_4 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_5_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_right_track_12 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_6_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_right_track_20 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_7_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_right_track_28 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_8_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_left_track_7 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_9_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_left_track_13 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_10_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_left_track_21 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_11_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_left_track_29 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_12_ccff_tail),
@@ -686,42 +686,42 @@ wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail;
 		.out(chanx_left_out[18]));
 
 	mux_tree_tapbuf_size5_mem mem_top_track_4 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_0_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_top_track_10 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_1_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_right_track_36 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_2_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_left_track_3 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_3_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_left_track_5 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_4_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_left_track_37 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_12_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
@@ -764,42 +764,42 @@ wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail;
 		.out(chanx_left_out[26]));
 
 	mux_tree_tapbuf_size4_mem mem_top_track_12 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_top_track_14 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_top_track_16 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_top_track_18 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_left_track_45 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_4_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_left_track_53 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
 		.ccff_tail(ccff_tail),
@@ -848,49 +848,49 @@ wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail;
 		.out(chanx_right_out[26]));
 
 	mux_tree_tapbuf_size3_mem mem_top_track_20 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_top_track_22 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_top_track_24 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_top_track_26 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_top_track_36 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_44 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_5_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_right_track_52 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
@@ -963,77 +963,77 @@ wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail;
 		.out(chany_top_out[29]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_28 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_30 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_32 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_34 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_40 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_42 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_44 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_46 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_48 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_8_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_50 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_9_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_58 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_1__1_.v
index f4c49c6..6b627e2 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_1__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_1__1_.v
@@ -11,7 +11,7 @@
 `default_nettype none
 
 // ----- Verilog module for sb_1__1_ -----
-module sb_1__1_(pReset,
+module sb_1__1_(prog_reset,
                 prog_clk,
                 chany_top_in,
                 top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
@@ -56,7 +56,7 @@ module sb_1__1_(pReset,
                 chanx_left_out,
                 ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -642,56 +642,56 @@ wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail;
 		.out(chanx_left_out[1]));
 
 	mux_tree_tapbuf_size11_mem mem_top_track_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(ccff_head),
 		.ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size11_0_sram[0:3]));
 
 	mux_tree_tapbuf_size11_mem mem_top_track_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size11_1_sram[0:3]));
 
 	mux_tree_tapbuf_size11_mem mem_right_track_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size11_2_sram[0:3]));
 
 	mux_tree_tapbuf_size11_mem mem_right_track_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size11_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size11_3_sram[0:3]));
 
 	mux_tree_tapbuf_size11_mem mem_bottom_track_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size11_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size11_4_sram[0:3]));
 
 	mux_tree_tapbuf_size11_mem mem_bottom_track_3 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size11_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size11_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size11_5_sram[0:3]));
 
 	mux_tree_tapbuf_size11_mem mem_left_track_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size11_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size11_6_sram[0:3]));
 
 	mux_tree_tapbuf_size11_mem mem_left_track_3 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size11_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size11_mem_7_ccff_tail),
@@ -770,84 +770,84 @@ wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail;
 		.out(chanx_left_out[10]));
 
 	mux_tree_tapbuf_size10_mem mem_top_track_4 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_top_track_12 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_top_track_20 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_right_track_4 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size11_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_right_track_12 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_right_track_20 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_bottom_track_5 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size11_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_bottom_track_13 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_bottom_track_21 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_8_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_left_track_5 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size11_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_9_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_left_track_13 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size10_10_sram[0:3]));
 
 	mux_tree_tapbuf_size10_mem mem_left_track_21 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail),
@@ -902,56 +902,56 @@ wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail;
 		.out(chanx_left_out[5]));
 
 	mux_tree_tapbuf_size12_mem mem_top_track_6 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_0_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_top_track_10 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_1_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_right_track_6 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_2_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_right_track_10 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_3_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_bottom_track_7 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_4_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_bottom_track_11 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_5_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_left_track_7 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size12_6_sram[0:3]));
 
 	mux_tree_tapbuf_size12_mem mem_left_track_11 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
@@ -982,28 +982,28 @@ wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail;
 		.out(chanx_left_out[14]));
 
 	mux_tree_tapbuf_size9_mem mem_top_track_28 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size9_0_sram[0:3]));
 
 	mux_tree_tapbuf_size9_mem mem_right_track_28 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size9_1_sram[0:3]));
 
 	mux_tree_tapbuf_size9_mem mem_bottom_track_29 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size9_2_sram[0:3]));
 
 	mux_tree_tapbuf_size9_mem mem_left_track_29 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail),
@@ -1082,84 +1082,84 @@ wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail;
 		.out(chanx_left_out[26]));
 
 	mux_tree_tapbuf_size6_mem mem_top_track_36 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_top_track_44 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_top_track_52 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_2_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_right_track_36 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_3_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_right_track_44 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_4_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_right_track_52 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_5_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_bottom_track_37 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_6_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_bottom_track_45 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_7_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_bottom_track_53 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_8_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_left_track_37 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_9_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_left_track_45 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_10_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_left_track_53 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail),
 		.ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_1__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_1__8_.v
index 507ecfe..d50d14e 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_1__8_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_1__8_.v
@@ -11,7 +11,7 @@
 `default_nettype none
 
 // ----- Verilog module for sb_1__8_ -----
-module sb_1__8_(pReset,
+module sb_1__8_(prog_reset,
                 prog_clk,
                 chanx_right_in,
                 right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
@@ -54,7 +54,7 @@ module sb_1__8_(pReset,
                 chanx_left_out,
                 ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -482,21 +482,21 @@ wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail;
 		.out(chanx_left_out[0]));
 
 	mux_tree_tapbuf_size8_mem mem_right_track_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(ccff_head),
 		.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]));
 
 	mux_tree_tapbuf_size8_mem mem_right_track_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]));
 
 	mux_tree_tapbuf_size8_mem mem_left_track_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail),
@@ -521,21 +521,21 @@ wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail;
 		.out(chanx_left_out[2]));
 
 	mux_tree_tapbuf_size9_mem mem_right_track_4 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size9_0_sram[0:3]));
 
 	mux_tree_tapbuf_size9_mem mem_left_track_3 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size9_1_sram[0:3]));
 
 	mux_tree_tapbuf_size9_mem mem_left_track_5 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail),
@@ -566,28 +566,28 @@ wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail;
 		.out(chanx_left_out[5]));
 
 	mux_tree_tapbuf_size11_mem mem_right_track_6 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size11_0_sram[0:3]));
 
 	mux_tree_tapbuf_size11_mem mem_right_track_10 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size11_1_sram[0:3]));
 
 	mux_tree_tapbuf_size11_mem mem_left_track_7 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size11_2_sram[0:3]));
 
 	mux_tree_tapbuf_size11_mem mem_left_track_11 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size11_mem_3_ccff_tail),
@@ -630,42 +630,42 @@ wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail;
 		.out(chanx_left_out[14]));
 
 	mux_tree_tapbuf_size7_mem mem_right_track_12 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size7_0_sram[0:2]));
 
 	mux_tree_tapbuf_size7_mem mem_right_track_20 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size7_1_sram[0:2]));
 
 	mux_tree_tapbuf_size7_mem mem_right_track_28 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size7_2_sram[0:2]));
 
 	mux_tree_tapbuf_size7_mem mem_left_track_13 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size11_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size7_3_sram[0:2]));
 
 	mux_tree_tapbuf_size7_mem mem_left_track_21 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size7_4_sram[0:2]));
 
 	mux_tree_tapbuf_size7_mem mem_left_track_29 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail),
@@ -714,49 +714,49 @@ wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail;
 		.out(chanx_left_out[18]));
 
 	mux_tree_tapbuf_size6_mem mem_right_track_36 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_right_track_44 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_bottom_track_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_2_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_bottom_track_3 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_3_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_bottom_track_7 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_4_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_bottom_track_9 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_5_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_left_track_37 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
@@ -793,35 +793,35 @@ wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail;
 		.out(chanx_left_out[26]));
 
 	mux_tree_tapbuf_size5_mem mem_right_track_52 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_0_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_bottom_track_5 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_1_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_bottom_track_11 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_2_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_left_track_45 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_3_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_left_track_53 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
 		.ccff_tail(ccff_tail),
@@ -858,35 +858,35 @@ wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail;
 		.out(chany_bottom_out[18]));
 
 	mux_tree_tapbuf_size4_mem mem_bottom_track_13 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_bottom_track_15 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_bottom_track_17 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_bottom_track_19 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_bottom_track_37 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
@@ -917,28 +917,28 @@ wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail;
 		.out(chany_bottom_out[13]));
 
 	mux_tree_tapbuf_size3_mem mem_bottom_track_21 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_bottom_track_23 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_bottom_track_25 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_bottom_track_27 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@@ -1011,77 +1011,77 @@ wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail;
 		.out(chany_bottom_out[25]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_29 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_31 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_33 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_35 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_39 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_41 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_43 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_45 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_47 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_8_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_49 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_9_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_51 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_8__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_8__0_.v
index 928bfd5..0b5cece 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_8__0_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_8__0_.v
@@ -11,7 +11,7 @@
 `default_nettype none
 
 // ----- Verilog module for sb_8__0_ -----
-module sb_8__0_(pReset,
+module sb_8__0_(prog_reset,
                 prog_clk,
                 chany_top_in,
                 top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
@@ -36,7 +36,7 @@ module sb_8__0_(pReset,
                 chanx_left_out,
                 ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -330,42 +330,42 @@ wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail;
 		.out(chany_top_out[5]));
 
 	mux_tree_tapbuf_size5_mem mem_top_track_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(ccff_head),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_0_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_top_track_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_1_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_top_track_4 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_2_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_top_track_6 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_3_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_top_track_8 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_4_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_top_track_10 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
@@ -432,70 +432,70 @@ wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail;
 		.out(chanx_left_out[3]));
 
 	mux_tree_tapbuf_size3_mem mem_top_track_12 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_top_track_14 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_top_track_16 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_top_track_18 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_top_track_44 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_top_track_46 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_5_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_top_track_48 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_6_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_top_track_50 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_7_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_left_track_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_8_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_left_track_7 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
@@ -670,196 +670,196 @@ wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail;
 		.out(chanx_left_out[25]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_20 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_22 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_24 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_26 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_28 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_30 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_32 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_34 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_36 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_8_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_38 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_9_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_40 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_10_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_top_track_42 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_11_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_3 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_12_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_5 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_13_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_9 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_14_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_11 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_15_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_13 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_16_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_15 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_17_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_17 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_18_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_19 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_19_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_29 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_20_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_31 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_21_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_33 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_22_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_35 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_23_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_45 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_24_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_47 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_25_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_49 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_26_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_51 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
 		.ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_8__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_8__1_.v
index cd19ad3..5de5452 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_8__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_8__1_.v
@@ -11,7 +11,7 @@
 `default_nettype none
 
 // ----- Verilog module for sb_8__1_ -----
-module sb_8__1_(pReset,
+module sb_8__1_(prog_reset,
                 prog_clk,
                 chany_top_in,
                 top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
@@ -54,7 +54,7 @@ module sb_8__1_(pReset,
                 chanx_left_out,
                 ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -487,28 +487,28 @@ wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail;
 		.out(chany_bottom_out[2]));
 
 	mux_tree_tapbuf_size9_mem mem_top_track_0 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(ccff_head),
 		.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size9_0_sram[0:3]));
 
 	mux_tree_tapbuf_size9_mem mem_bottom_track_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size9_1_sram[0:3]));
 
 	mux_tree_tapbuf_size9_mem mem_bottom_track_3 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size9_2_sram[0:3]));
 
 	mux_tree_tapbuf_size9_mem mem_bottom_track_5 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail),
@@ -527,14 +527,14 @@ wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail;
 		.out(chany_top_out[2]));
 
 	mux_tree_tapbuf_size8_mem mem_top_track_2 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]));
 
 	mux_tree_tapbuf_size8_mem mem_top_track_4 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail),
@@ -547,7 +547,7 @@ wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail;
 		.out(chany_top_out[3]));
 
 	mux_tree_tapbuf_size10_mem mem_top_track_6 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
@@ -572,21 +572,21 @@ wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail;
 		.out(chany_bottom_out[5]));
 
 	mux_tree_tapbuf_size11_mem mem_top_track_10 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size11_0_sram[0:3]));
 
 	mux_tree_tapbuf_size11_mem mem_bottom_track_7 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size11_1_sram[0:3]));
 
 	mux_tree_tapbuf_size11_mem mem_bottom_track_11 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail),
@@ -623,35 +623,35 @@ wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail;
 		.out(chany_bottom_out[10]));
 
 	mux_tree_tapbuf_size7_mem mem_top_track_12 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size7_0_sram[0:2]));
 
 	mux_tree_tapbuf_size7_mem mem_top_track_20 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size7_1_sram[0:2]));
 
 	mux_tree_tapbuf_size7_mem mem_top_track_28 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size7_2_sram[0:2]));
 
 	mux_tree_tapbuf_size7_mem mem_bottom_track_13 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size7_3_sram[0:2]));
 
 	mux_tree_tapbuf_size7_mem mem_bottom_track_21 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
@@ -712,63 +712,63 @@ wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail;
 		.out(chanx_left_out[4]));
 
 	mux_tree_tapbuf_size6_mem mem_top_track_36 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_top_track_44 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_top_track_52 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_2_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_bottom_track_29 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_3_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_bottom_track_53 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_4_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_left_track_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_5_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_left_track_3 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_6_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_left_track_7 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size6_7_sram[0:2]));
 
 	mux_tree_tapbuf_size6_mem mem_left_track_9 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
@@ -799,28 +799,28 @@ wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail;
 		.out(chanx_left_out[5]));
 
 	mux_tree_tapbuf_size5_mem mem_bottom_track_37 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_0_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_bottom_track_45 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_1_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_left_track_5 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_2_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_left_track_11 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@@ -863,42 +863,42 @@ wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail;
 		.out(chanx_left_out[11]));
 
 	mux_tree_tapbuf_size4_mem mem_left_track_13 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_left_track_15 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_left_track_17 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_left_track_19 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_left_track_21 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size4_4_sram[0:2]));
 
 	mux_tree_tapbuf_size4_mem mem_left_track_23 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail),
@@ -953,56 +953,56 @@ wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail;
 		.out(chanx_left_out[25]));
 
 	mux_tree_tapbuf_size3_mem mem_left_track_25 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_left_track_27 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_left_track_29 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_left_track_31 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_left_track_33 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_left_track_35 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_5_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_left_track_37 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_6_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_left_track_51 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
@@ -1051,49 +1051,49 @@ wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail;
 		.out(chanx_left_out[28]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_41 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_45 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_47 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_49 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_53 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_55 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_57 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
 		.ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_8__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_8__8_.v
index a29805d..ce5a855 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_8__8_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/routing/sb_8__8_.v
@@ -11,7 +11,7 @@
 `default_nettype none
 
 // ----- Verilog module for sb_8__8_ -----
-module sb_8__8_(pReset,
+module sb_8__8_(prog_reset,
                 prog_clk,
                 chany_bottom_in,
                 bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
@@ -44,7 +44,7 @@ module sb_8__8_(pReset,
                 chanx_left_out,
                 ccff_tail);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -378,84 +378,84 @@ wire [0:0] mux_tree_tapbuf_size5_mem_9_ccff_tail;
 		.out(chanx_left_out[5]));
 
 	mux_tree_tapbuf_size5_mem mem_bottom_track_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(ccff_head),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_0_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_bottom_track_3 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_1_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_bottom_track_5 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_2_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_bottom_track_7 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_3_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_bottom_track_9 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_4_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_bottom_track_11 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_5_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_left_track_1 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_6_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_left_track_3 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_7_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_7_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_left_track_5 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_8_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_8_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_left_track_7 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_8_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_9_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_9_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_left_track_9 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_9_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_10_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size5_10_sram[0:2]));
 
 	mux_tree_tapbuf_size5_mem mem_left_track_11 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_10_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size5_mem_11_ccff_tail),
@@ -612,175 +612,175 @@ wire [0:0] mux_tree_tapbuf_size5_mem_9_ccff_tail;
 		.out(chanx_left_out[28]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_13 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_15 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_17 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_19 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_21 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_23 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_25 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_27 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_53 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_8_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_55 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_9_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_57 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_10_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_bottom_track_59 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_11_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_19 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_12_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_21 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_13_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_23 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_14_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_25 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_15_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_27 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_16_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_37 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_14_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_17_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_39 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_18_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_41 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_19_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_43 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_20_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_51 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_17_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_21_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_53 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_22_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_55 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size2_23_sram[0:1]));
 
 	mux_tree_tapbuf_size2_mem mem_left_track_57 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
@@ -901,133 +901,133 @@ wire [0:0] mux_tree_tapbuf_size5_mem_9_ccff_tail;
 		.out(chanx_left_out[29]));
 
 	mux_tree_tapbuf_size3_mem mem_bottom_track_29 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_bottom_track_31 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_bottom_track_33 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_bottom_track_35 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_bottom_track_45 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_bottom_track_47 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_5_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_bottom_track_49 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_6_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_bottom_track_51 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_7_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_left_track_13 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size5_mem_11_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_8_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_left_track_15 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_9_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_left_track_17 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_10_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_left_track_29 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_11_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_left_track_31 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_12_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_left_track_33 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_13_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_13_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_left_track_35 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_13_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_14_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_14_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_left_track_45 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_15_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_15_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_left_track_47 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_15_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_16_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_16_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_left_track_49 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size3_mem_16_ccff_tail),
 		.ccff_tail(mux_tree_tapbuf_size3_mem_17_ccff_tail),
 		.mem_out(mux_tree_tapbuf_size3_17_sram[0:1]));
 
 	mux_tree_tapbuf_size3_mem mem_left_track_59 (
-		.pReset(pReset),
+		.prog_reset(prog_reset),
 		.prog_clk(prog_clk),
 		.ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
 		.ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/memories.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/memories.v
index 06572de..6346512 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/memories.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/memories.v
@@ -11,13 +11,13 @@
 `default_nettype none
 
 // ----- Verilog module for mux_tree_tapbuf_size12_mem -----
-module mux_tree_tapbuf_size12_mem(pReset,
+module mux_tree_tapbuf_size12_mem(prog_reset,
                                   prog_clk,
                                   ccff_head,
                                   ccff_tail,
                                   mem_out);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -43,25 +43,25 @@ output [0:3] mem_out;
 // ----- END Local output short connections -----
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(ccff_head),
 		.Q(mem_out[0]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[0]),
 		.Q(mem_out[1]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[1]),
 		.Q(mem_out[2]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[2]),
 		.Q(mem_out[3]));
@@ -79,13 +79,13 @@ endmodule
 `default_nettype none
 
 // ----- Verilog module for mux_tree_tapbuf_size10_mem -----
-module mux_tree_tapbuf_size10_mem(pReset,
+module mux_tree_tapbuf_size10_mem(prog_reset,
                                   prog_clk,
                                   ccff_head,
                                   ccff_tail,
                                   mem_out);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -111,25 +111,25 @@ output [0:3] mem_out;
 // ----- END Local output short connections -----
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(ccff_head),
 		.Q(mem_out[0]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[0]),
 		.Q(mem_out[1]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[1]),
 		.Q(mem_out[2]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[2]),
 		.Q(mem_out[3]));
@@ -147,13 +147,13 @@ endmodule
 `default_nettype none
 
 // ----- Verilog module for mux_tree_tapbuf_size3_mem -----
-module mux_tree_tapbuf_size3_mem(pReset,
+module mux_tree_tapbuf_size3_mem(prog_reset,
                                  prog_clk,
                                  ccff_head,
                                  ccff_tail,
                                  mem_out);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -179,13 +179,13 @@ output [0:1] mem_out;
 // ----- END Local output short connections -----
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(ccff_head),
 		.Q(mem_out[0]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[0]),
 		.Q(mem_out[1]));
@@ -203,13 +203,13 @@ endmodule
 `default_nettype none
 
 // ----- Verilog module for mux_tree_tapbuf_size7_mem -----
-module mux_tree_tapbuf_size7_mem(pReset,
+module mux_tree_tapbuf_size7_mem(prog_reset,
                                  prog_clk,
                                  ccff_head,
                                  ccff_tail,
                                  mem_out);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -235,19 +235,19 @@ output [0:2] mem_out;
 // ----- END Local output short connections -----
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(ccff_head),
 		.Q(mem_out[0]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[0]),
 		.Q(mem_out[1]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[1]),
 		.Q(mem_out[2]));
@@ -265,13 +265,13 @@ endmodule
 `default_nettype none
 
 // ----- Verilog module for mux_tree_tapbuf_size2_mem -----
-module mux_tree_tapbuf_size2_mem(pReset,
+module mux_tree_tapbuf_size2_mem(prog_reset,
                                  prog_clk,
                                  ccff_head,
                                  ccff_tail,
                                  mem_out);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -297,13 +297,13 @@ output [0:1] mem_out;
 // ----- END Local output short connections -----
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(ccff_head),
 		.Q(mem_out[0]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[0]),
 		.Q(mem_out[1]));
@@ -321,13 +321,13 @@ endmodule
 `default_nettype none
 
 // ----- Verilog module for mux_tree_tapbuf_size5_mem -----
-module mux_tree_tapbuf_size5_mem(pReset,
+module mux_tree_tapbuf_size5_mem(prog_reset,
                                  prog_clk,
                                  ccff_head,
                                  ccff_tail,
                                  mem_out);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -353,19 +353,19 @@ output [0:2] mem_out;
 // ----- END Local output short connections -----
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(ccff_head),
 		.Q(mem_out[0]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[0]),
 		.Q(mem_out[1]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[1]),
 		.Q(mem_out[2]));
@@ -383,13 +383,13 @@ endmodule
 `default_nettype none
 
 // ----- Verilog module for mux_tree_tapbuf_size6_mem -----
-module mux_tree_tapbuf_size6_mem(pReset,
+module mux_tree_tapbuf_size6_mem(prog_reset,
                                  prog_clk,
                                  ccff_head,
                                  ccff_tail,
                                  mem_out);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -415,19 +415,19 @@ output [0:2] mem_out;
 // ----- END Local output short connections -----
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(ccff_head),
 		.Q(mem_out[0]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[0]),
 		.Q(mem_out[1]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[1]),
 		.Q(mem_out[2]));
@@ -445,13 +445,13 @@ endmodule
 `default_nettype none
 
 // ----- Verilog module for mux_tree_tapbuf_size4_mem -----
-module mux_tree_tapbuf_size4_mem(pReset,
+module mux_tree_tapbuf_size4_mem(prog_reset,
                                  prog_clk,
                                  ccff_head,
                                  ccff_tail,
                                  mem_out);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -477,19 +477,19 @@ output [0:2] mem_out;
 // ----- END Local output short connections -----
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(ccff_head),
 		.Q(mem_out[0]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[0]),
 		.Q(mem_out[1]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[1]),
 		.Q(mem_out[2]));
@@ -507,13 +507,13 @@ endmodule
 `default_nettype none
 
 // ----- Verilog module for mux_tree_tapbuf_size11_mem -----
-module mux_tree_tapbuf_size11_mem(pReset,
+module mux_tree_tapbuf_size11_mem(prog_reset,
                                   prog_clk,
                                   ccff_head,
                                   ccff_tail,
                                   mem_out);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -539,25 +539,25 @@ output [0:3] mem_out;
 // ----- END Local output short connections -----
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(ccff_head),
 		.Q(mem_out[0]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[0]),
 		.Q(mem_out[1]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[1]),
 		.Q(mem_out[2]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[2]),
 		.Q(mem_out[3]));
@@ -575,13 +575,13 @@ endmodule
 `default_nettype none
 
 // ----- Verilog module for mux_tree_tapbuf_size9_mem -----
-module mux_tree_tapbuf_size9_mem(pReset,
+module mux_tree_tapbuf_size9_mem(prog_reset,
                                  prog_clk,
                                  ccff_head,
                                  ccff_tail,
                                  mem_out);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -607,25 +607,25 @@ output [0:3] mem_out;
 // ----- END Local output short connections -----
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(ccff_head),
 		.Q(mem_out[0]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[0]),
 		.Q(mem_out[1]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[1]),
 		.Q(mem_out[2]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[2]),
 		.Q(mem_out[3]));
@@ -643,13 +643,13 @@ endmodule
 `default_nettype none
 
 // ----- Verilog module for mux_tree_tapbuf_size8_mem -----
-module mux_tree_tapbuf_size8_mem(pReset,
+module mux_tree_tapbuf_size8_mem(prog_reset,
                                  prog_clk,
                                  ccff_head,
                                  ccff_tail,
                                  mem_out);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -675,25 +675,25 @@ output [0:3] mem_out;
 // ----- END Local output short connections -----
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(ccff_head),
 		.Q(mem_out[0]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[0]),
 		.Q(mem_out[1]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[1]),
 		.Q(mem_out[2]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[2]),
 		.Q(mem_out[3]));
@@ -711,13 +711,13 @@ endmodule
 `default_nettype none
 
 // ----- Verilog module for mux_tree_size2_mem -----
-module mux_tree_size2_mem(pReset,
+module mux_tree_size2_mem(prog_reset,
                           prog_clk,
                           ccff_head,
                           ccff_tail,
                           mem_out);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -743,13 +743,13 @@ output [0:1] mem_out;
 // ----- END Local output short connections -----
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(ccff_head),
 		.Q(mem_out[0]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[0]),
 		.Q(mem_out[1]));
@@ -767,13 +767,13 @@ endmodule
 `default_nettype none
 
 // ----- Verilog module for frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem -----
-module frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem(pReset,
+module frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem(prog_reset,
                                               prog_clk,
                                               ccff_head,
                                               ccff_tail,
                                               mem_out);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -799,103 +799,103 @@ output [0:16] mem_out;
 // ----- END Local output short connections -----
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(ccff_head),
 		.Q(mem_out[0]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[0]),
 		.Q(mem_out[1]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[1]),
 		.Q(mem_out[2]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[2]),
 		.Q(mem_out[3]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[3]),
 		.Q(mem_out[4]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[4]),
 		.Q(mem_out[5]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[5]),
 		.Q(mem_out[6]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[6]),
 		.Q(mem_out[7]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[7]),
 		.Q(mem_out[8]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[8]),
 		.Q(mem_out[9]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[9]),
 		.Q(mem_out[10]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[10]),
 		.Q(mem_out[11]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[11]),
 		.Q(mem_out[12]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[12]),
 		.Q(mem_out[13]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[13]),
 		.Q(mem_out[14]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[14]),
 		.Q(mem_out[15]));
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(mem_out[15]),
 		.Q(mem_out[16]));
@@ -912,14 +912,14 @@ endmodule
 //----- Default net type -----
 `default_nettype none
 
-// ----- Verilog module for EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem -----
-module EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem(pReset,
-                                                   prog_clk,
-                                                   ccff_head,
-                                                   ccff_tail,
-                                                   mem_out);
+// ----- Verilog module for io_sky130_fd_sc_hd__dfrtp_1_mem -----
+module io_sky130_fd_sc_hd__dfrtp_1_mem(prog_reset,
+                                       prog_clk,
+                                       ccff_head,
+                                       ccff_tail,
+                                       mem_out);
 //----- GLOBAL PORTS -----
-input [0:0] pReset;
+input [0:0] prog_reset;
 //----- GLOBAL PORTS -----
 input [0:0] prog_clk;
 //----- INPUT PORTS -----
@@ -945,13 +945,13 @@ output [0:0] mem_out;
 // ----- END Local output short connections -----
 
 	sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ (
-		.RESET_B(pReset),
+		.RESET_B(prog_reset),
 		.CLK(prog_clk),
 		.D(ccff_head),
 		.Q(mem_out));
 
 endmodule
-// ----- END Verilog module for EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem -----
+// ----- END Verilog module for io_sky130_fd_sc_hd__dfrtp_1_mem -----
 
 //----- Default net type -----
 `default_nettype none
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/user_defined_templates.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/user_defined_templates.v
index 452ff30..0149ae7 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/user_defined_templates.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCOriginal/sub_module/user_defined_templates.v
@@ -274,18 +274,18 @@ endmodule
 `default_nettype none
 
 
-// ----- Template Verilog module for EMBEDDED_IO_HD -----
+// ----- Template Verilog module for io -----
 //----- Default net type -----
 `default_nettype none
 
-// ----- Verilog module for EMBEDDED_IO_HD -----
-module EMBEDDED_IO_HD(IO_ISOL_N,
-                      SOC_IN,
-                      SOC_OUT,
-                      SOC_DIR,
-                      FPGA_OUT,
-                      FPGA_DIR,
-                      FPGA_IN);
+// ----- Verilog module for io -----
+module io(IO_ISOL_N,
+          SOC_IN,
+          SOC_OUT,
+          SOC_DIR,
+          FPGA_OUT,
+          FPGA_DIR,
+          FPGA_IN);
 //----- GLOBAL PORTS -----
 input [0:0] IO_ISOL_N;
 //----- GPIN PORTS -----
@@ -313,7 +313,7 @@ output [0:0] FPGA_IN;
 
 // ----- Internal logic should end here -----
 endmodule
-// ----- END Verilog module for EMBEDDED_IO_HD -----
+// ----- END Verilog module for io -----
 
 //----- Default net type -----
 `default_nettype none
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/fpga_top.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/fpga_top.v
index 54050e1..7a2e681 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/fpga_top.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/fpga_top.v
@@ -3,39 +3,39 @@
 module fpga_top
 (
     clk,
-    Reset,
-    IO_ISOL_N,
-    pReset,
+    reset,
+    isol_n,
+    prog_reset,
     prog_clk,
-    Test_en,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    scan_enable,
+    gfpga_pad_io_soc_in,
+    gfpga_pad_io_soc_out,
+    gfpga_pad_io_soc_dir,
     ccff_head,
     ccff_tail
 );
 
     input clk;
-    input Reset;
-    input IO_ISOL_N;
-    input pReset;
+    input reset;
+    input isol_n;
+    input prog_reset;
     input prog_clk;
-    input Test_en;
-    input [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    output [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    output [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    input scan_enable;
+    input [0:127]gfpga_pad_io_soc_in;
+    output [0:127]gfpga_pad_io_soc_out;
+    output [0:127]gfpga_pad_io_soc_dir;
     input ccff_head;
     output ccff_tail;
 
     wire clk;
-    wire Reset;
-    wire IO_ISOL_N;
-    wire pReset;
+    wire reset;
+    wire isol_n;
+    wire prog_reset;
     wire prog_clk;
-    wire Test_en;
-    wire [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    wire [0:127]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire scan_enable;
+    wire [0:127]gfpga_pad_io_soc_in;
+    wire [0:127]gfpga_pad_io_soc_out;
+    wire [0:127]gfpga_pad_io_soc_dir;
     wire ccff_head;
     wire ccff_tail;
     wire cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;
@@ -4649,12 +4649,12 @@ module fpga_top
 
     grid_io_top_top grid_io_top_top_1__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:3]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0:3]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0:3]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0:3]),
         .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4668,12 +4668,12 @@ module fpga_top
     );
     grid_io_top_top grid_io_top_top_2__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4:7]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4:7]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4:7]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[4:7]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[4:7]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[4:7]),
         .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__1_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4687,12 +4687,12 @@ module fpga_top
     );
     grid_io_top_top grid_io_top_top_3__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8:11]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8:11]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8:11]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[8:11]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[8:11]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[8:11]),
         .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__2_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4706,12 +4706,12 @@ module fpga_top
     );
     grid_io_top_top grid_io_top_top_4__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12:15]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12:15]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12:15]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[12:15]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[12:15]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[12:15]),
         .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__3_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4725,12 +4725,12 @@ module fpga_top
     );
     grid_io_top_top grid_io_top_top_5__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16:19]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16:19]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16:19]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[16:19]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[16:19]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[16:19]),
         .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__4_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4744,12 +4744,12 @@ module fpga_top
     );
     grid_io_top_top grid_io_top_top_6__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20:23]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20:23]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20:23]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[20:23]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[20:23]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[20:23]),
         .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__5_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4763,12 +4763,12 @@ module fpga_top
     );
     grid_io_top_top grid_io_top_top_7__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24:27]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24:27]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24:27]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[24:27]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[24:27]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[24:27]),
         .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__6_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4782,12 +4782,12 @@ module fpga_top
     );
     grid_io_top_top grid_io_top_top_8__9_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28:31]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28:31]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[28:31]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[28:31]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[28:31]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[28:31]),
         .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
         .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__8__7_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4801,12 +4801,12 @@ module fpga_top
     );
     grid_io_right_right grid_io_right_right_9__8_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32:35]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32:35]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[32:35]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[32:35]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[32:35]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[32:35]),
         .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
         .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
         .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__7_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4820,12 +4820,12 @@ module fpga_top
     );
     grid_io_right_right grid_io_right_right_9__7_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36:39]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36:39]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[36:39]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[36:39]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[36:39]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[36:39]),
         .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
         .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
         .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__6_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4839,12 +4839,12 @@ module fpga_top
     );
     grid_io_right_right grid_io_right_right_9__6_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40:43]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40:43]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[40:43]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[40:43]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[40:43]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[40:43]),
         .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
         .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
         .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__5_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4858,12 +4858,12 @@ module fpga_top
     );
     grid_io_right_right grid_io_right_right_9__5_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44:47]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44:47]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[44:47]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[44:47]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[44:47]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[44:47]),
         .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
         .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
         .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__4_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4877,12 +4877,12 @@ module fpga_top
     );
     grid_io_right_right grid_io_right_right_9__4_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48:51]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48:51]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[48:51]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[48:51]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[48:51]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[48:51]),
         .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
         .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
         .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__3_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4896,12 +4896,12 @@ module fpga_top
     );
     grid_io_right_right grid_io_right_right_9__3_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52:55]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52:55]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[52:55]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[52:55]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[52:55]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[52:55]),
         .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
         .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
         .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__2_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4915,12 +4915,12 @@ module fpga_top
     );
     grid_io_right_right grid_io_right_right_9__2_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56:59]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56:59]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[56:59]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[56:59]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[56:59]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[56:59]),
         .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
         .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
         .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__1_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4934,12 +4934,12 @@ module fpga_top
     );
     grid_io_right_right grid_io_right_right_9__1_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60:63]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60:63]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60:63]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[60:63]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[60:63]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[60:63]),
         .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
         .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
         .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_8__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4953,12 +4953,12 @@ module fpga_top
     );
     grid_io_bottom_bottom grid_io_bottom_bottom_8__0_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64:67]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64:67]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[64:67]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[64:67]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[64:67]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[64:67]),
         .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
         .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
         .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__7_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4972,12 +4972,12 @@ module fpga_top
     );
     grid_io_bottom_bottom grid_io_bottom_bottom_7__0_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68:71]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68:71]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[68:71]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[68:71]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[68:71]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[68:71]),
         .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
         .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
         .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__6_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -4991,12 +4991,12 @@ module fpga_top
     );
     grid_io_bottom_bottom grid_io_bottom_bottom_6__0_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72:75]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72:75]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[72:75]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[72:75]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[72:75]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[72:75]),
         .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
         .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
         .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__5_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5010,12 +5010,12 @@ module fpga_top
     );
     grid_io_bottom_bottom grid_io_bottom_bottom_5__0_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76:79]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76:79]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[76:79]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[76:79]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[76:79]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[76:79]),
         .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
         .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
         .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__4_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5029,12 +5029,12 @@ module fpga_top
     );
     grid_io_bottom_bottom grid_io_bottom_bottom_4__0_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80:83]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80:83]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[80:83]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[80:83]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[80:83]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[80:83]),
         .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
         .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
         .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5048,12 +5048,12 @@ module fpga_top
     );
     grid_io_bottom_bottom grid_io_bottom_bottom_3__0_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84:87]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84:87]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[84:87]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[84:87]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[84:87]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[84:87]),
         .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
         .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
         .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5067,12 +5067,12 @@ module fpga_top
     );
     grid_io_bottom_bottom grid_io_bottom_bottom_2__0_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88:91]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88:91]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[88:91]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[88:91]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[88:91]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[88:91]),
         .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
         .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
         .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5086,12 +5086,12 @@ module fpga_top
     );
     grid_io_bottom_bottom grid_io_bottom_bottom_1__0_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92:95]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92:95]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[92:95]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[92:95]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[92:95]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[92:95]),
         .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
         .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
         .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5105,12 +5105,12 @@ module fpga_top
     );
     grid_io_left_left grid_io_left_left_0__1_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96:99]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96:99]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96:99]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[96:99]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[96:99]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[96:99]),
         .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
         .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
         .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5124,12 +5124,12 @@ module fpga_top
     );
     grid_io_left_left grid_io_left_left_0__2_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100:103]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100:103]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[100:103]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[100:103]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[100:103]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[100:103]),
         .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
         .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
         .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__1_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5143,12 +5143,12 @@ module fpga_top
     );
     grid_io_left_left grid_io_left_left_0__3_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104:107]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104:107]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[104:107]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[104:107]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[104:107]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[104:107]),
         .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
         .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
         .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__2_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5162,12 +5162,12 @@ module fpga_top
     );
     grid_io_left_left grid_io_left_left_0__4_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108:111]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108:111]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[108:111]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[108:111]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[108:111]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[108:111]),
         .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
         .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
         .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__3_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5181,12 +5181,12 @@ module fpga_top
     );
     grid_io_left_left grid_io_left_left_0__5_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112:115]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112:115]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[112:115]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[112:115]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[112:115]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[112:115]),
         .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
         .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
         .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__4_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5200,12 +5200,12 @@ module fpga_top
     );
     grid_io_left_left grid_io_left_left_0__6_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116:119]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116:119]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[116:119]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[116:119]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[116:119]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[116:119]),
         .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
         .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
         .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__5_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5219,12 +5219,12 @@ module fpga_top
     );
     grid_io_left_left grid_io_left_left_0__7_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120:123]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120:123]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[120:123]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[120:123]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[120:123]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[120:123]),
         .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
         .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
         .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__6_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5238,12 +5238,12 @@ module fpga_top
     );
     grid_io_left_left grid_io_left_left_0__8_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124:127]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124:127]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[124:127]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[124:127]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[124:127]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[124:127]),
         .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
         .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
         .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__7_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
@@ -5257,9 +5257,9 @@ module fpga_top
     );
     grid_clb grid_clb_1__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5295,7 +5295,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__0_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5321,9 +5321,9 @@ module fpga_top
     );
     grid_clb grid_clb_1__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5359,7 +5359,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__1_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5385,9 +5385,9 @@ module fpga_top
     );
     grid_clb grid_clb_1__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5423,7 +5423,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__2_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5449,9 +5449,9 @@ module fpga_top
     );
     grid_clb grid_clb_1__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5487,7 +5487,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__3_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5513,9 +5513,9 @@ module fpga_top
     );
     grid_clb grid_clb_1__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5551,7 +5551,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__4_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5577,9 +5577,9 @@ module fpga_top
     );
     grid_clb grid_clb_1__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5615,7 +5615,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__5_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5641,9 +5641,9 @@ module fpga_top
     );
     grid_clb grid_clb_1__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5679,7 +5679,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__6_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5705,9 +5705,9 @@ module fpga_top
     );
     grid_clb grid_clb_1__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5743,7 +5743,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__7_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5769,9 +5769,9 @@ module fpga_top
     );
     grid_clb grid_clb_2__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5807,7 +5807,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__8_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__8_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5833,9 +5833,9 @@ module fpga_top
     );
     grid_clb grid_clb_2__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__8_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5871,7 +5871,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__9_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__9_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5897,9 +5897,9 @@ module fpga_top
     );
     grid_clb grid_clb_2__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__9_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5935,7 +5935,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__10_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__10_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -5961,9 +5961,9 @@ module fpga_top
     );
     grid_clb grid_clb_2__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__10_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -5999,7 +5999,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__11_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__11_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6025,9 +6025,9 @@ module fpga_top
     );
     grid_clb grid_clb_2__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__11_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6063,7 +6063,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__12_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__12_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6089,9 +6089,9 @@ module fpga_top
     );
     grid_clb grid_clb_2__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__12_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6127,7 +6127,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__13_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__13_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6153,9 +6153,9 @@ module fpga_top
     );
     grid_clb grid_clb_2__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__13_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6191,7 +6191,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__14_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__14_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6217,9 +6217,9 @@ module fpga_top
     );
     grid_clb grid_clb_2__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__1_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6255,7 +6255,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__15_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__15_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6281,9 +6281,9 @@ module fpga_top
     );
     grid_clb grid_clb_3__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__14_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6319,7 +6319,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__16_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__16_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_16_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6345,9 +6345,9 @@ module fpga_top
     );
     grid_clb grid_clb_3__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__15_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6383,7 +6383,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__17_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__17_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_17_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6409,9 +6409,9 @@ module fpga_top
     );
     grid_clb grid_clb_3__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__16_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6447,7 +6447,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__18_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__18_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_18_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6473,9 +6473,9 @@ module fpga_top
     );
     grid_clb grid_clb_3__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__17_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6511,7 +6511,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__19_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__19_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_19_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6537,9 +6537,9 @@ module fpga_top
     );
     grid_clb grid_clb_3__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__18_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6575,7 +6575,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__20_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__20_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_20_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6601,9 +6601,9 @@ module fpga_top
     );
     grid_clb grid_clb_3__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__19_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6639,7 +6639,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__21_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__21_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_21_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6665,9 +6665,9 @@ module fpga_top
     );
     grid_clb grid_clb_3__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__20_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6703,7 +6703,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__22_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__22_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_22_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6729,9 +6729,9 @@ module fpga_top
     );
     grid_clb grid_clb_3__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__2_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6767,7 +6767,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__23_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__23_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_23_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6793,9 +6793,9 @@ module fpga_top
     );
     grid_clb grid_clb_4__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__21_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6831,7 +6831,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__24_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__24_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_24_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6857,9 +6857,9 @@ module fpga_top
     );
     grid_clb grid_clb_4__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__22_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6895,7 +6895,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__25_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__25_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_25_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6921,9 +6921,9 @@ module fpga_top
     );
     grid_clb grid_clb_4__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__23_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -6959,7 +6959,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__26_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__26_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_26_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -6985,9 +6985,9 @@ module fpga_top
     );
     grid_clb grid_clb_4__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__24_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7023,7 +7023,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__27_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__27_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_27_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7049,9 +7049,9 @@ module fpga_top
     );
     grid_clb grid_clb_4__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__25_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7087,7 +7087,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__28_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__28_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_28_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7113,9 +7113,9 @@ module fpga_top
     );
     grid_clb grid_clb_4__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__26_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7151,7 +7151,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__29_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__29_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_29_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7177,9 +7177,9 @@ module fpga_top
     );
     grid_clb grid_clb_4__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__27_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7215,7 +7215,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__30_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__30_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_30_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7241,9 +7241,9 @@ module fpga_top
     );
     grid_clb grid_clb_4__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__3_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7279,7 +7279,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__31_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__31_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_31_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7305,9 +7305,9 @@ module fpga_top
     );
     grid_clb grid_clb_5__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__28_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7343,7 +7343,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__32_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__32_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_32_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7369,9 +7369,9 @@ module fpga_top
     );
     grid_clb grid_clb_5__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__29_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7407,7 +7407,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__33_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__33_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_33_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7433,9 +7433,9 @@ module fpga_top
     );
     grid_clb grid_clb_5__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__30_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7471,7 +7471,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__34_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__34_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_34_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7497,9 +7497,9 @@ module fpga_top
     );
     grid_clb grid_clb_5__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__31_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7535,7 +7535,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__35_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__35_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_35_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7561,9 +7561,9 @@ module fpga_top
     );
     grid_clb grid_clb_5__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__32_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7599,7 +7599,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__36_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__36_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_36_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7625,9 +7625,9 @@ module fpga_top
     );
     grid_clb grid_clb_5__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__33_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7663,7 +7663,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__37_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__37_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_37_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7689,9 +7689,9 @@ module fpga_top
     );
     grid_clb grid_clb_5__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__34_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7727,7 +7727,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__38_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__38_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_38_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7753,9 +7753,9 @@ module fpga_top
     );
     grid_clb grid_clb_5__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__4_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7791,7 +7791,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__39_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__39_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_39_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7817,9 +7817,9 @@ module fpga_top
     );
     grid_clb grid_clb_6__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__35_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7855,7 +7855,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__40_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__40_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_40_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7881,9 +7881,9 @@ module fpga_top
     );
     grid_clb grid_clb_6__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__36_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7919,7 +7919,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__41_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__41_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_41_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -7945,9 +7945,9 @@ module fpga_top
     );
     grid_clb grid_clb_6__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__37_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -7983,7 +7983,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__42_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__42_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_42_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8009,9 +8009,9 @@ module fpga_top
     );
     grid_clb grid_clb_6__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__38_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8047,7 +8047,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__43_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__43_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_43_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8073,9 +8073,9 @@ module fpga_top
     );
     grid_clb grid_clb_6__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__39_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8111,7 +8111,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__44_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__44_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_44_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8137,9 +8137,9 @@ module fpga_top
     );
     grid_clb grid_clb_6__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__40_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8175,7 +8175,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__45_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__45_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_45_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8201,9 +8201,9 @@ module fpga_top
     );
     grid_clb grid_clb_6__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__41_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8239,7 +8239,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__46_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__46_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_46_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8265,9 +8265,9 @@ module fpga_top
     );
     grid_clb grid_clb_6__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__5_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8303,7 +8303,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__47_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__47_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_47_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8329,9 +8329,9 @@ module fpga_top
     );
     grid_clb grid_clb_7__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__42_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8367,7 +8367,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__48_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__48_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_48_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8393,9 +8393,9 @@ module fpga_top
     );
     grid_clb grid_clb_7__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__43_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8431,7 +8431,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__49_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__49_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_49_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8457,9 +8457,9 @@ module fpga_top
     );
     grid_clb grid_clb_7__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__44_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8495,7 +8495,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__50_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__50_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_50_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8521,9 +8521,9 @@ module fpga_top
     );
     grid_clb grid_clb_7__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__45_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8559,7 +8559,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__51_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__51_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_51_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8585,9 +8585,9 @@ module fpga_top
     );
     grid_clb grid_clb_7__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__46_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8623,7 +8623,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__52_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__52_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_52_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8649,9 +8649,9 @@ module fpga_top
     );
     grid_clb grid_clb_7__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__47_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8687,7 +8687,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__53_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__53_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_53_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8713,9 +8713,9 @@ module fpga_top
     );
     grid_clb grid_clb_7__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__48_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8751,7 +8751,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__54_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__54_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_54_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8777,9 +8777,9 @@ module fpga_top
     );
     grid_clb grid_clb_7__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__6_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8815,7 +8815,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_1__1__55_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_1__1__55_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_55_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8841,9 +8841,9 @@ module fpga_top
     );
     grid_clb grid_clb_8__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__49_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8879,7 +8879,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_8__1__0_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_56_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8905,9 +8905,9 @@ module fpga_top
     );
     grid_clb grid_clb_8__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__50_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -8943,7 +8943,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__1_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_8__1__1_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_57_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -8969,9 +8969,9 @@ module fpga_top
     );
     grid_clb grid_clb_8__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__51_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9007,7 +9007,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__2_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_8__1__2_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_58_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -9033,9 +9033,9 @@ module fpga_top
     );
     grid_clb grid_clb_8__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__52_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9071,7 +9071,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__3_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_8__1__3_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_59_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -9097,9 +9097,9 @@ module fpga_top
     );
     grid_clb grid_clb_8__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__53_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9135,7 +9135,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__4_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_8__1__4_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_60_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -9161,9 +9161,9 @@ module fpga_top
     );
     grid_clb grid_clb_8__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__54_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9199,7 +9199,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__5_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_8__1__5_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_61_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -9225,9 +9225,9 @@ module fpga_top
     );
     grid_clb grid_clb_8__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__1__55_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9263,7 +9263,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__6_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_8__1__6_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_62_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -9289,9 +9289,9 @@ module fpga_top
     );
     grid_clb grid_clb_8__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .top_width_0_height_0_subtile_0__pin_I0_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
         .top_width_0_height_0_subtile_0__pin_I0_1_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
         .top_width_0_height_0_subtile_0__pin_I0i_0_(cbx_1__8__7_bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_),
@@ -9327,7 +9327,7 @@ module fpga_top
         .right_width_0_height_0_subtile_0__pin_I7_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
         .right_width_0_height_0_subtile_0__pin_I7i_0_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
         .right_width_0_height_0_subtile_0__pin_I7i_1_(cby_8__1__7_left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
-        .left_width_0_height_0_subtile_0__pin_reset_0_(Reset),
+        .left_width_0_height_0_subtile_0__pin_reset_0_(reset),
         .left_width_0_height_0_subtile_0__pin_clk_0_(clk),
         .ccff_head(cby_8__1__7_ccff_tail),
         .top_width_0_height_0_subtile_0__pin_O_0_(grid_clb_63_top_width_0_height_0_subtile_0__pin_O_0_),
@@ -9353,7 +9353,7 @@ module fpga_top
     );
     sb_0__0_ sb_0__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_0__1__0_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9372,7 +9372,7 @@ module fpga_top
     );
     sb_0__1_ sb_0__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_0__1__1_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9401,7 +9401,7 @@ module fpga_top
     );
     sb_0__1_ sb_0__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_0__1__2_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9430,7 +9430,7 @@ module fpga_top
     );
     sb_0__1_ sb_0__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_0__1__3_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9459,7 +9459,7 @@ module fpga_top
     );
     sb_0__1_ sb_0__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_0__1__4_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9488,7 +9488,7 @@ module fpga_top
     );
     sb_0__1_ sb_0__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_0__1__5_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9517,7 +9517,7 @@ module fpga_top
     );
     sb_0__1_ sb_0__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_0__1__6_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9546,7 +9546,7 @@ module fpga_top
     );
     sb_0__1_ sb_0__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_0__1__7_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9575,7 +9575,7 @@ module fpga_top
     );
     sb_0__8_ sb_0__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_right_in(cbx_1__8__0_chanx_left_out),
         .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -9602,7 +9602,7 @@ module fpga_top
     );
     sb_1__0_ sb_1__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__0_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9631,7 +9631,7 @@ module fpga_top
     );
     sb_1__0_ sb_2__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__8_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_8_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9660,7 +9660,7 @@ module fpga_top
     );
     sb_1__0_ sb_3__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__16_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_16_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9689,7 +9689,7 @@ module fpga_top
     );
     sb_1__0_ sb_4__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__24_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_24_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9718,7 +9718,7 @@ module fpga_top
     );
     sb_1__0_ sb_5__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__32_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_32_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9747,7 +9747,7 @@ module fpga_top
     );
     sb_1__0_ sb_6__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__40_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_40_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9776,7 +9776,7 @@ module fpga_top
     );
     sb_1__0_ sb_7__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__48_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_48_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9805,7 +9805,7 @@ module fpga_top
     );
     sb_1__1_ sb_1__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__1_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_1_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9852,7 +9852,7 @@ module fpga_top
     );
     sb_1__1_ sb_1__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__2_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_2_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9899,7 +9899,7 @@ module fpga_top
     );
     sb_1__1_ sb_1__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__3_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_3_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9946,7 +9946,7 @@ module fpga_top
     );
     sb_1__1_ sb_1__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__4_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_4_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -9993,7 +9993,7 @@ module fpga_top
     );
     sb_1__1_ sb_1__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__5_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_5_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10040,7 +10040,7 @@ module fpga_top
     );
     sb_1__1_ sb_1__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__6_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_6_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10087,7 +10087,7 @@ module fpga_top
     );
     sb_1__1_ sb_1__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__7_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_7_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10134,7 +10134,7 @@ module fpga_top
     );
     sb_1__1_ sb_2__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__9_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_9_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10181,7 +10181,7 @@ module fpga_top
     );
     sb_1__1_ sb_2__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__10_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_10_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10228,7 +10228,7 @@ module fpga_top
     );
     sb_1__1_ sb_2__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__11_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_11_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10275,7 +10275,7 @@ module fpga_top
     );
     sb_1__1_ sb_2__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__12_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_12_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10322,7 +10322,7 @@ module fpga_top
     );
     sb_1__1_ sb_2__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__13_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_13_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10369,7 +10369,7 @@ module fpga_top
     );
     sb_1__1_ sb_2__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__14_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_14_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10416,7 +10416,7 @@ module fpga_top
     );
     sb_1__1_ sb_2__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__15_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_15_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10463,7 +10463,7 @@ module fpga_top
     );
     sb_1__1_ sb_3__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__17_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_17_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10510,7 +10510,7 @@ module fpga_top
     );
     sb_1__1_ sb_3__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__18_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_18_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10557,7 +10557,7 @@ module fpga_top
     );
     sb_1__1_ sb_3__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__19_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_19_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10604,7 +10604,7 @@ module fpga_top
     );
     sb_1__1_ sb_3__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__20_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_20_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10651,7 +10651,7 @@ module fpga_top
     );
     sb_1__1_ sb_3__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__21_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_21_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10698,7 +10698,7 @@ module fpga_top
     );
     sb_1__1_ sb_3__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__22_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_22_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10745,7 +10745,7 @@ module fpga_top
     );
     sb_1__1_ sb_3__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__23_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_23_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10792,7 +10792,7 @@ module fpga_top
     );
     sb_1__1_ sb_4__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__25_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_25_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10839,7 +10839,7 @@ module fpga_top
     );
     sb_1__1_ sb_4__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__26_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_26_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10886,7 +10886,7 @@ module fpga_top
     );
     sb_1__1_ sb_4__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__27_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_27_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10933,7 +10933,7 @@ module fpga_top
     );
     sb_1__1_ sb_4__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__28_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_28_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -10980,7 +10980,7 @@ module fpga_top
     );
     sb_1__1_ sb_4__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__29_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_29_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11027,7 +11027,7 @@ module fpga_top
     );
     sb_1__1_ sb_4__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__30_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_30_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11074,7 +11074,7 @@ module fpga_top
     );
     sb_1__1_ sb_4__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__31_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_31_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11121,7 +11121,7 @@ module fpga_top
     );
     sb_1__1_ sb_5__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__33_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_33_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11168,7 +11168,7 @@ module fpga_top
     );
     sb_1__1_ sb_5__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__34_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_34_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11215,7 +11215,7 @@ module fpga_top
     );
     sb_1__1_ sb_5__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__35_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_35_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11262,7 +11262,7 @@ module fpga_top
     );
     sb_1__1_ sb_5__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__36_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_36_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11309,7 +11309,7 @@ module fpga_top
     );
     sb_1__1_ sb_5__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__37_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_37_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11356,7 +11356,7 @@ module fpga_top
     );
     sb_1__1_ sb_5__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__38_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_38_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11403,7 +11403,7 @@ module fpga_top
     );
     sb_1__1_ sb_5__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__39_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_39_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11450,7 +11450,7 @@ module fpga_top
     );
     sb_1__1_ sb_6__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__41_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_41_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11497,7 +11497,7 @@ module fpga_top
     );
     sb_1__1_ sb_6__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__42_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_42_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11544,7 +11544,7 @@ module fpga_top
     );
     sb_1__1_ sb_6__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__43_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_43_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11591,7 +11591,7 @@ module fpga_top
     );
     sb_1__1_ sb_6__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__44_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_44_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11638,7 +11638,7 @@ module fpga_top
     );
     sb_1__1_ sb_6__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__45_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_45_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11685,7 +11685,7 @@ module fpga_top
     );
     sb_1__1_ sb_6__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__46_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_46_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11732,7 +11732,7 @@ module fpga_top
     );
     sb_1__1_ sb_6__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__47_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_47_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11779,7 +11779,7 @@ module fpga_top
     );
     sb_1__1_ sb_7__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__49_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_49_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11826,7 +11826,7 @@ module fpga_top
     );
     sb_1__1_ sb_7__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__50_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_50_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11873,7 +11873,7 @@ module fpga_top
     );
     sb_1__1_ sb_7__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__51_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_51_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11920,7 +11920,7 @@ module fpga_top
     );
     sb_1__1_ sb_7__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__52_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_52_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -11967,7 +11967,7 @@ module fpga_top
     );
     sb_1__1_ sb_7__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__53_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_53_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12014,7 +12014,7 @@ module fpga_top
     );
     sb_1__1_ sb_7__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__54_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_54_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12061,7 +12061,7 @@ module fpga_top
     );
     sb_1__1_ sb_7__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_1__1__55_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_55_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12108,7 +12108,7 @@ module fpga_top
     );
     sb_1__8_ sb_1__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_right_in(cbx_1__8__1_chanx_left_out),
         .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12153,7 +12153,7 @@ module fpga_top
     );
     sb_1__8_ sb_2__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_right_in(cbx_1__8__2_chanx_left_out),
         .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12198,7 +12198,7 @@ module fpga_top
     );
     sb_1__8_ sb_3__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_right_in(cbx_1__8__3_chanx_left_out),
         .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12243,7 +12243,7 @@ module fpga_top
     );
     sb_1__8_ sb_4__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_right_in(cbx_1__8__4_chanx_left_out),
         .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_4_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12288,7 +12288,7 @@ module fpga_top
     );
     sb_1__8_ sb_5__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_right_in(cbx_1__8__5_chanx_left_out),
         .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_5_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12333,7 +12333,7 @@ module fpga_top
     );
     sb_1__8_ sb_6__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_right_in(cbx_1__8__6_chanx_left_out),
         .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_6_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12378,7 +12378,7 @@ module fpga_top
     );
     sb_1__8_ sb_7__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_right_in(cbx_1__8__7_chanx_left_out),
         .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_top_7_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12423,7 +12423,7 @@ module fpga_top
     );
     sb_8__0_ sb_8__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_8__1__0_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_56_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12450,7 +12450,7 @@ module fpga_top
     );
     sb_8__1_ sb_8__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_8__1__1_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_57_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12495,7 +12495,7 @@ module fpga_top
     );
     sb_8__1_ sb_8__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_8__1__2_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_58_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12540,7 +12540,7 @@ module fpga_top
     );
     sb_8__1_ sb_8__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_8__1__3_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_59_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12585,7 +12585,7 @@ module fpga_top
     );
     sb_8__1_ sb_8__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_8__1__4_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_60_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12630,7 +12630,7 @@ module fpga_top
     );
     sb_8__1_ sb_8__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_8__1__5_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_61_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12675,7 +12675,7 @@ module fpga_top
     );
     sb_8__1_ sb_8__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_8__1__6_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_62_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12720,7 +12720,7 @@ module fpga_top
     );
     sb_8__1_ sb_8__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_top_in(cby_8__1__7_chany_bottom_out),
         .top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_(grid_clb_63_right_width_0_height_0_subtile_0__pin_O_8_),
@@ -12765,7 +12765,7 @@ module fpga_top
     );
     sb_8__8_ sb_8__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(cby_8__1__7_chany_top_out),
         .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -12800,7 +12800,7 @@ module fpga_top
     );
     cbx_1__0_ cbx_1__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_0__0__0_chanx_right_out),
         .chanx_right_in(sb_1__0__0_chanx_left_out),
@@ -12815,7 +12815,7 @@ module fpga_top
     );
     cbx_1__0_ cbx_2__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__0__0_chanx_right_out),
         .chanx_right_in(sb_1__0__1_chanx_left_out),
@@ -12830,7 +12830,7 @@ module fpga_top
     );
     cbx_1__0_ cbx_3__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__0__1_chanx_right_out),
         .chanx_right_in(sb_1__0__2_chanx_left_out),
@@ -12845,7 +12845,7 @@ module fpga_top
     );
     cbx_1__0_ cbx_4__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__0__2_chanx_right_out),
         .chanx_right_in(sb_1__0__3_chanx_left_out),
@@ -12860,7 +12860,7 @@ module fpga_top
     );
     cbx_1__0_ cbx_5__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__0__3_chanx_right_out),
         .chanx_right_in(sb_1__0__4_chanx_left_out),
@@ -12875,7 +12875,7 @@ module fpga_top
     );
     cbx_1__0_ cbx_6__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__0__4_chanx_right_out),
         .chanx_right_in(sb_1__0__5_chanx_left_out),
@@ -12890,7 +12890,7 @@ module fpga_top
     );
     cbx_1__0_ cbx_7__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__0__5_chanx_right_out),
         .chanx_right_in(sb_1__0__6_chanx_left_out),
@@ -12905,7 +12905,7 @@ module fpga_top
     );
     cbx_1__0_ cbx_8__0_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__0__6_chanx_right_out),
         .chanx_right_in(sb_8__0__0_chanx_left_out),
@@ -12920,7 +12920,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_1__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_0__1__0_chanx_right_out),
         .chanx_right_in(sb_1__1__0_chanx_left_out),
@@ -12947,7 +12947,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_1__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_0__1__1_chanx_right_out),
         .chanx_right_in(sb_1__1__1_chanx_left_out),
@@ -12974,7 +12974,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_1__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_0__1__2_chanx_right_out),
         .chanx_right_in(sb_1__1__2_chanx_left_out),
@@ -13001,7 +13001,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_1__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_0__1__3_chanx_right_out),
         .chanx_right_in(sb_1__1__3_chanx_left_out),
@@ -13028,7 +13028,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_1__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_0__1__4_chanx_right_out),
         .chanx_right_in(sb_1__1__4_chanx_left_out),
@@ -13055,7 +13055,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_1__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_0__1__5_chanx_right_out),
         .chanx_right_in(sb_1__1__5_chanx_left_out),
@@ -13082,7 +13082,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_1__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_0__1__6_chanx_right_out),
         .chanx_right_in(sb_1__1__6_chanx_left_out),
@@ -13109,7 +13109,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_2__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__0_chanx_right_out),
         .chanx_right_in(sb_1__1__7_chanx_left_out),
@@ -13136,7 +13136,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_2__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__1_chanx_right_out),
         .chanx_right_in(sb_1__1__8_chanx_left_out),
@@ -13163,7 +13163,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_2__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__2_chanx_right_out),
         .chanx_right_in(sb_1__1__9_chanx_left_out),
@@ -13190,7 +13190,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_2__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__3_chanx_right_out),
         .chanx_right_in(sb_1__1__10_chanx_left_out),
@@ -13217,7 +13217,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_2__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__4_chanx_right_out),
         .chanx_right_in(sb_1__1__11_chanx_left_out),
@@ -13244,7 +13244,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_2__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__5_chanx_right_out),
         .chanx_right_in(sb_1__1__12_chanx_left_out),
@@ -13271,7 +13271,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_2__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__6_chanx_right_out),
         .chanx_right_in(sb_1__1__13_chanx_left_out),
@@ -13298,7 +13298,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_3__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__7_chanx_right_out),
         .chanx_right_in(sb_1__1__14_chanx_left_out),
@@ -13325,7 +13325,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_3__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__8_chanx_right_out),
         .chanx_right_in(sb_1__1__15_chanx_left_out),
@@ -13352,7 +13352,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_3__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__9_chanx_right_out),
         .chanx_right_in(sb_1__1__16_chanx_left_out),
@@ -13379,7 +13379,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_3__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__10_chanx_right_out),
         .chanx_right_in(sb_1__1__17_chanx_left_out),
@@ -13406,7 +13406,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_3__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__11_chanx_right_out),
         .chanx_right_in(sb_1__1__18_chanx_left_out),
@@ -13433,7 +13433,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_3__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__12_chanx_right_out),
         .chanx_right_in(sb_1__1__19_chanx_left_out),
@@ -13460,7 +13460,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_3__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__13_chanx_right_out),
         .chanx_right_in(sb_1__1__20_chanx_left_out),
@@ -13487,7 +13487,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_4__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__14_chanx_right_out),
         .chanx_right_in(sb_1__1__21_chanx_left_out),
@@ -13514,7 +13514,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_4__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__15_chanx_right_out),
         .chanx_right_in(sb_1__1__22_chanx_left_out),
@@ -13541,7 +13541,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_4__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__16_chanx_right_out),
         .chanx_right_in(sb_1__1__23_chanx_left_out),
@@ -13568,7 +13568,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_4__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__17_chanx_right_out),
         .chanx_right_in(sb_1__1__24_chanx_left_out),
@@ -13595,7 +13595,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_4__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__18_chanx_right_out),
         .chanx_right_in(sb_1__1__25_chanx_left_out),
@@ -13622,7 +13622,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_4__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__19_chanx_right_out),
         .chanx_right_in(sb_1__1__26_chanx_left_out),
@@ -13649,7 +13649,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_4__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__20_chanx_right_out),
         .chanx_right_in(sb_1__1__27_chanx_left_out),
@@ -13676,7 +13676,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_5__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__21_chanx_right_out),
         .chanx_right_in(sb_1__1__28_chanx_left_out),
@@ -13703,7 +13703,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_5__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__22_chanx_right_out),
         .chanx_right_in(sb_1__1__29_chanx_left_out),
@@ -13730,7 +13730,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_5__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__23_chanx_right_out),
         .chanx_right_in(sb_1__1__30_chanx_left_out),
@@ -13757,7 +13757,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_5__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__24_chanx_right_out),
         .chanx_right_in(sb_1__1__31_chanx_left_out),
@@ -13784,7 +13784,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_5__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__25_chanx_right_out),
         .chanx_right_in(sb_1__1__32_chanx_left_out),
@@ -13811,7 +13811,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_5__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__26_chanx_right_out),
         .chanx_right_in(sb_1__1__33_chanx_left_out),
@@ -13838,7 +13838,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_5__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__27_chanx_right_out),
         .chanx_right_in(sb_1__1__34_chanx_left_out),
@@ -13865,7 +13865,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_6__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__28_chanx_right_out),
         .chanx_right_in(sb_1__1__35_chanx_left_out),
@@ -13892,7 +13892,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_6__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__29_chanx_right_out),
         .chanx_right_in(sb_1__1__36_chanx_left_out),
@@ -13919,7 +13919,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_6__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__30_chanx_right_out),
         .chanx_right_in(sb_1__1__37_chanx_left_out),
@@ -13946,7 +13946,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_6__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__31_chanx_right_out),
         .chanx_right_in(sb_1__1__38_chanx_left_out),
@@ -13973,7 +13973,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_6__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__32_chanx_right_out),
         .chanx_right_in(sb_1__1__39_chanx_left_out),
@@ -14000,7 +14000,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_6__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__33_chanx_right_out),
         .chanx_right_in(sb_1__1__40_chanx_left_out),
@@ -14027,7 +14027,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_6__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__34_chanx_right_out),
         .chanx_right_in(sb_1__1__41_chanx_left_out),
@@ -14054,7 +14054,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_7__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__35_chanx_right_out),
         .chanx_right_in(sb_1__1__42_chanx_left_out),
@@ -14081,7 +14081,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_7__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__36_chanx_right_out),
         .chanx_right_in(sb_1__1__43_chanx_left_out),
@@ -14108,7 +14108,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_7__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__37_chanx_right_out),
         .chanx_right_in(sb_1__1__44_chanx_left_out),
@@ -14135,7 +14135,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_7__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__38_chanx_right_out),
         .chanx_right_in(sb_1__1__45_chanx_left_out),
@@ -14162,7 +14162,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_7__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__39_chanx_right_out),
         .chanx_right_in(sb_1__1__46_chanx_left_out),
@@ -14189,7 +14189,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_7__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__40_chanx_right_out),
         .chanx_right_in(sb_1__1__47_chanx_left_out),
@@ -14216,7 +14216,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_7__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__41_chanx_right_out),
         .chanx_right_in(sb_1__1__48_chanx_left_out),
@@ -14243,7 +14243,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_8__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__42_chanx_right_out),
         .chanx_right_in(sb_8__1__0_chanx_left_out),
@@ -14270,7 +14270,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_8__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__43_chanx_right_out),
         .chanx_right_in(sb_8__1__1_chanx_left_out),
@@ -14297,7 +14297,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_8__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__44_chanx_right_out),
         .chanx_right_in(sb_8__1__2_chanx_left_out),
@@ -14324,7 +14324,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_8__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__45_chanx_right_out),
         .chanx_right_in(sb_8__1__3_chanx_left_out),
@@ -14351,7 +14351,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_8__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__46_chanx_right_out),
         .chanx_right_in(sb_8__1__4_chanx_left_out),
@@ -14378,7 +14378,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_8__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__47_chanx_right_out),
         .chanx_right_in(sb_8__1__5_chanx_left_out),
@@ -14405,7 +14405,7 @@ module fpga_top
     );
     cbx_1__1_ cbx_8__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__1__48_chanx_right_out),
         .chanx_right_in(sb_8__1__6_chanx_left_out),
@@ -14432,7 +14432,7 @@ module fpga_top
     );
     cbx_1__8_ cbx_1__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_0__8__0_chanx_right_out),
         .chanx_right_in(sb_1__8__0_chanx_left_out),
@@ -14463,7 +14463,7 @@ module fpga_top
     );
     cbx_1__8_ cbx_2__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__8__0_chanx_right_out),
         .chanx_right_in(sb_1__8__1_chanx_left_out),
@@ -14494,7 +14494,7 @@ module fpga_top
     );
     cbx_1__8_ cbx_3__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__8__1_chanx_right_out),
         .chanx_right_in(sb_1__8__2_chanx_left_out),
@@ -14525,7 +14525,7 @@ module fpga_top
     );
     cbx_1__8_ cbx_4__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__8__2_chanx_right_out),
         .chanx_right_in(sb_1__8__3_chanx_left_out),
@@ -14556,7 +14556,7 @@ module fpga_top
     );
     cbx_1__8_ cbx_5__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__8__3_chanx_right_out),
         .chanx_right_in(sb_1__8__4_chanx_left_out),
@@ -14587,7 +14587,7 @@ module fpga_top
     );
     cbx_1__8_ cbx_6__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__8__4_chanx_right_out),
         .chanx_right_in(sb_1__8__5_chanx_left_out),
@@ -14618,7 +14618,7 @@ module fpga_top
     );
     cbx_1__8_ cbx_7__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__8__5_chanx_right_out),
         .chanx_right_in(sb_1__8__6_chanx_left_out),
@@ -14649,7 +14649,7 @@ module fpga_top
     );
     cbx_1__8_ cbx_8__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chanx_left_in(sb_1__8__6_chanx_right_out),
         .chanx_right_in(sb_8__8__0_chanx_left_out),
@@ -14680,7 +14680,7 @@ module fpga_top
     );
     cby_0__1_ cby_0__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_0__0__0_chany_top_out),
         .chany_top_in(sb_0__1__0_chany_bottom_out),
@@ -14695,7 +14695,7 @@ module fpga_top
     );
     cby_0__1_ cby_0__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_0__1__0_chany_top_out),
         .chany_top_in(sb_0__1__1_chany_bottom_out),
@@ -14710,7 +14710,7 @@ module fpga_top
     );
     cby_0__1_ cby_0__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_0__1__1_chany_top_out),
         .chany_top_in(sb_0__1__2_chany_bottom_out),
@@ -14725,7 +14725,7 @@ module fpga_top
     );
     cby_0__1_ cby_0__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_0__1__2_chany_top_out),
         .chany_top_in(sb_0__1__3_chany_bottom_out),
@@ -14740,7 +14740,7 @@ module fpga_top
     );
     cby_0__1_ cby_0__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_0__1__3_chany_top_out),
         .chany_top_in(sb_0__1__4_chany_bottom_out),
@@ -14755,7 +14755,7 @@ module fpga_top
     );
     cby_0__1_ cby_0__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_0__1__4_chany_top_out),
         .chany_top_in(sb_0__1__5_chany_bottom_out),
@@ -14770,7 +14770,7 @@ module fpga_top
     );
     cby_0__1_ cby_0__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_0__1__5_chany_top_out),
         .chany_top_in(sb_0__1__6_chany_bottom_out),
@@ -14785,7 +14785,7 @@ module fpga_top
     );
     cby_0__1_ cby_0__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_0__1__6_chany_top_out),
         .chany_top_in(sb_0__8__0_chany_bottom_out),
@@ -14800,7 +14800,7 @@ module fpga_top
     );
     cby_1__1_ cby_1__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__0__0_chany_top_out),
         .chany_top_in(sb_1__1__0_chany_bottom_out),
@@ -14827,7 +14827,7 @@ module fpga_top
     );
     cby_1__1_ cby_1__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__0_chany_top_out),
         .chany_top_in(sb_1__1__1_chany_bottom_out),
@@ -14854,7 +14854,7 @@ module fpga_top
     );
     cby_1__1_ cby_1__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__1_chany_top_out),
         .chany_top_in(sb_1__1__2_chany_bottom_out),
@@ -14881,7 +14881,7 @@ module fpga_top
     );
     cby_1__1_ cby_1__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__2_chany_top_out),
         .chany_top_in(sb_1__1__3_chany_bottom_out),
@@ -14908,7 +14908,7 @@ module fpga_top
     );
     cby_1__1_ cby_1__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__3_chany_top_out),
         .chany_top_in(sb_1__1__4_chany_bottom_out),
@@ -14935,7 +14935,7 @@ module fpga_top
     );
     cby_1__1_ cby_1__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__4_chany_top_out),
         .chany_top_in(sb_1__1__5_chany_bottom_out),
@@ -14962,7 +14962,7 @@ module fpga_top
     );
     cby_1__1_ cby_1__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__5_chany_top_out),
         .chany_top_in(sb_1__1__6_chany_bottom_out),
@@ -14989,7 +14989,7 @@ module fpga_top
     );
     cby_1__1_ cby_1__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__6_chany_top_out),
         .chany_top_in(sb_1__8__0_chany_bottom_out),
@@ -15016,7 +15016,7 @@ module fpga_top
     );
     cby_1__1_ cby_2__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__0__1_chany_top_out),
         .chany_top_in(sb_1__1__7_chany_bottom_out),
@@ -15043,7 +15043,7 @@ module fpga_top
     );
     cby_1__1_ cby_2__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__7_chany_top_out),
         .chany_top_in(sb_1__1__8_chany_bottom_out),
@@ -15070,7 +15070,7 @@ module fpga_top
     );
     cby_1__1_ cby_2__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__8_chany_top_out),
         .chany_top_in(sb_1__1__9_chany_bottom_out),
@@ -15097,7 +15097,7 @@ module fpga_top
     );
     cby_1__1_ cby_2__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__9_chany_top_out),
         .chany_top_in(sb_1__1__10_chany_bottom_out),
@@ -15124,7 +15124,7 @@ module fpga_top
     );
     cby_1__1_ cby_2__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__10_chany_top_out),
         .chany_top_in(sb_1__1__11_chany_bottom_out),
@@ -15151,7 +15151,7 @@ module fpga_top
     );
     cby_1__1_ cby_2__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__11_chany_top_out),
         .chany_top_in(sb_1__1__12_chany_bottom_out),
@@ -15178,7 +15178,7 @@ module fpga_top
     );
     cby_1__1_ cby_2__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__12_chany_top_out),
         .chany_top_in(sb_1__1__13_chany_bottom_out),
@@ -15205,7 +15205,7 @@ module fpga_top
     );
     cby_1__1_ cby_2__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__13_chany_top_out),
         .chany_top_in(sb_1__8__1_chany_bottom_out),
@@ -15232,7 +15232,7 @@ module fpga_top
     );
     cby_1__1_ cby_3__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__0__2_chany_top_out),
         .chany_top_in(sb_1__1__14_chany_bottom_out),
@@ -15259,7 +15259,7 @@ module fpga_top
     );
     cby_1__1_ cby_3__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__14_chany_top_out),
         .chany_top_in(sb_1__1__15_chany_bottom_out),
@@ -15286,7 +15286,7 @@ module fpga_top
     );
     cby_1__1_ cby_3__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__15_chany_top_out),
         .chany_top_in(sb_1__1__16_chany_bottom_out),
@@ -15313,7 +15313,7 @@ module fpga_top
     );
     cby_1__1_ cby_3__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__16_chany_top_out),
         .chany_top_in(sb_1__1__17_chany_bottom_out),
@@ -15340,7 +15340,7 @@ module fpga_top
     );
     cby_1__1_ cby_3__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__17_chany_top_out),
         .chany_top_in(sb_1__1__18_chany_bottom_out),
@@ -15367,7 +15367,7 @@ module fpga_top
     );
     cby_1__1_ cby_3__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__18_chany_top_out),
         .chany_top_in(sb_1__1__19_chany_bottom_out),
@@ -15394,7 +15394,7 @@ module fpga_top
     );
     cby_1__1_ cby_3__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__19_chany_top_out),
         .chany_top_in(sb_1__1__20_chany_bottom_out),
@@ -15421,7 +15421,7 @@ module fpga_top
     );
     cby_1__1_ cby_3__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__20_chany_top_out),
         .chany_top_in(sb_1__8__2_chany_bottom_out),
@@ -15448,7 +15448,7 @@ module fpga_top
     );
     cby_1__1_ cby_4__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__0__3_chany_top_out),
         .chany_top_in(sb_1__1__21_chany_bottom_out),
@@ -15475,7 +15475,7 @@ module fpga_top
     );
     cby_1__1_ cby_4__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__21_chany_top_out),
         .chany_top_in(sb_1__1__22_chany_bottom_out),
@@ -15502,7 +15502,7 @@ module fpga_top
     );
     cby_1__1_ cby_4__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__22_chany_top_out),
         .chany_top_in(sb_1__1__23_chany_bottom_out),
@@ -15529,7 +15529,7 @@ module fpga_top
     );
     cby_1__1_ cby_4__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__23_chany_top_out),
         .chany_top_in(sb_1__1__24_chany_bottom_out),
@@ -15556,7 +15556,7 @@ module fpga_top
     );
     cby_1__1_ cby_4__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__24_chany_top_out),
         .chany_top_in(sb_1__1__25_chany_bottom_out),
@@ -15583,7 +15583,7 @@ module fpga_top
     );
     cby_1__1_ cby_4__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__25_chany_top_out),
         .chany_top_in(sb_1__1__26_chany_bottom_out),
@@ -15610,7 +15610,7 @@ module fpga_top
     );
     cby_1__1_ cby_4__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__26_chany_top_out),
         .chany_top_in(sb_1__1__27_chany_bottom_out),
@@ -15637,7 +15637,7 @@ module fpga_top
     );
     cby_1__1_ cby_4__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__27_chany_top_out),
         .chany_top_in(sb_1__8__3_chany_bottom_out),
@@ -15664,7 +15664,7 @@ module fpga_top
     );
     cby_1__1_ cby_5__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__0__4_chany_top_out),
         .chany_top_in(sb_1__1__28_chany_bottom_out),
@@ -15691,7 +15691,7 @@ module fpga_top
     );
     cby_1__1_ cby_5__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__28_chany_top_out),
         .chany_top_in(sb_1__1__29_chany_bottom_out),
@@ -15718,7 +15718,7 @@ module fpga_top
     );
     cby_1__1_ cby_5__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__29_chany_top_out),
         .chany_top_in(sb_1__1__30_chany_bottom_out),
@@ -15745,7 +15745,7 @@ module fpga_top
     );
     cby_1__1_ cby_5__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__30_chany_top_out),
         .chany_top_in(sb_1__1__31_chany_bottom_out),
@@ -15772,7 +15772,7 @@ module fpga_top
     );
     cby_1__1_ cby_5__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__31_chany_top_out),
         .chany_top_in(sb_1__1__32_chany_bottom_out),
@@ -15799,7 +15799,7 @@ module fpga_top
     );
     cby_1__1_ cby_5__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__32_chany_top_out),
         .chany_top_in(sb_1__1__33_chany_bottom_out),
@@ -15826,7 +15826,7 @@ module fpga_top
     );
     cby_1__1_ cby_5__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__33_chany_top_out),
         .chany_top_in(sb_1__1__34_chany_bottom_out),
@@ -15853,7 +15853,7 @@ module fpga_top
     );
     cby_1__1_ cby_5__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__34_chany_top_out),
         .chany_top_in(sb_1__8__4_chany_bottom_out),
@@ -15880,7 +15880,7 @@ module fpga_top
     );
     cby_1__1_ cby_6__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__0__5_chany_top_out),
         .chany_top_in(sb_1__1__35_chany_bottom_out),
@@ -15907,7 +15907,7 @@ module fpga_top
     );
     cby_1__1_ cby_6__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__35_chany_top_out),
         .chany_top_in(sb_1__1__36_chany_bottom_out),
@@ -15934,7 +15934,7 @@ module fpga_top
     );
     cby_1__1_ cby_6__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__36_chany_top_out),
         .chany_top_in(sb_1__1__37_chany_bottom_out),
@@ -15961,7 +15961,7 @@ module fpga_top
     );
     cby_1__1_ cby_6__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__37_chany_top_out),
         .chany_top_in(sb_1__1__38_chany_bottom_out),
@@ -15988,7 +15988,7 @@ module fpga_top
     );
     cby_1__1_ cby_6__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__38_chany_top_out),
         .chany_top_in(sb_1__1__39_chany_bottom_out),
@@ -16015,7 +16015,7 @@ module fpga_top
     );
     cby_1__1_ cby_6__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__39_chany_top_out),
         .chany_top_in(sb_1__1__40_chany_bottom_out),
@@ -16042,7 +16042,7 @@ module fpga_top
     );
     cby_1__1_ cby_6__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__40_chany_top_out),
         .chany_top_in(sb_1__1__41_chany_bottom_out),
@@ -16069,7 +16069,7 @@ module fpga_top
     );
     cby_1__1_ cby_6__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__41_chany_top_out),
         .chany_top_in(sb_1__8__5_chany_bottom_out),
@@ -16096,7 +16096,7 @@ module fpga_top
     );
     cby_1__1_ cby_7__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__0__6_chany_top_out),
         .chany_top_in(sb_1__1__42_chany_bottom_out),
@@ -16123,7 +16123,7 @@ module fpga_top
     );
     cby_1__1_ cby_7__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__42_chany_top_out),
         .chany_top_in(sb_1__1__43_chany_bottom_out),
@@ -16150,7 +16150,7 @@ module fpga_top
     );
     cby_1__1_ cby_7__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__43_chany_top_out),
         .chany_top_in(sb_1__1__44_chany_bottom_out),
@@ -16177,7 +16177,7 @@ module fpga_top
     );
     cby_1__1_ cby_7__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__44_chany_top_out),
         .chany_top_in(sb_1__1__45_chany_bottom_out),
@@ -16204,7 +16204,7 @@ module fpga_top
     );
     cby_1__1_ cby_7__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__45_chany_top_out),
         .chany_top_in(sb_1__1__46_chany_bottom_out),
@@ -16231,7 +16231,7 @@ module fpga_top
     );
     cby_1__1_ cby_7__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__46_chany_top_out),
         .chany_top_in(sb_1__1__47_chany_bottom_out),
@@ -16258,7 +16258,7 @@ module fpga_top
     );
     cby_1__1_ cby_7__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__47_chany_top_out),
         .chany_top_in(sb_1__1__48_chany_bottom_out),
@@ -16285,7 +16285,7 @@ module fpga_top
     );
     cby_1__1_ cby_7__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_1__1__48_chany_top_out),
         .chany_top_in(sb_1__8__6_chany_bottom_out),
@@ -16312,7 +16312,7 @@ module fpga_top
     );
     cby_8__1_ cby_8__1_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_8__0__0_chany_top_out),
         .chany_top_in(sb_8__1__0_chany_bottom_out),
@@ -16343,7 +16343,7 @@ module fpga_top
     );
     cby_8__1_ cby_8__2_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_8__1__0_chany_top_out),
         .chany_top_in(sb_8__1__1_chany_bottom_out),
@@ -16374,7 +16374,7 @@ module fpga_top
     );
     cby_8__1_ cby_8__3_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_8__1__1_chany_top_out),
         .chany_top_in(sb_8__1__2_chany_bottom_out),
@@ -16405,7 +16405,7 @@ module fpga_top
     );
     cby_8__1_ cby_8__4_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_8__1__2_chany_top_out),
         .chany_top_in(sb_8__1__3_chany_bottom_out),
@@ -16436,7 +16436,7 @@ module fpga_top
     );
     cby_8__1_ cby_8__5_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_8__1__3_chany_top_out),
         .chany_top_in(sb_8__1__4_chany_bottom_out),
@@ -16467,7 +16467,7 @@ module fpga_top
     );
     cby_8__1_ cby_8__6_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_8__1__4_chany_top_out),
         .chany_top_in(sb_8__1__5_chany_bottom_out),
@@ -16498,7 +16498,7 @@ module fpga_top
     );
     cby_8__1_ cby_8__7_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_8__1__5_chany_top_out),
         .chany_top_in(sb_8__1__6_chany_bottom_out),
@@ -16529,7 +16529,7 @@ module fpga_top
     );
     cby_8__1_ cby_8__8_
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .chany_bottom_in(sb_8__1__6_chany_top_out),
         .chany_top_in(sb_8__8__0_chany_bottom_out),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_clb.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_clb.v
index cde4367..abe7b72 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_clb.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_clb.v
@@ -2,9 +2,9 @@
 //netlist name: FPGA88_SOFA_A
 module grid_clb
 (
-    pReset,
+    prog_reset,
     prog_clk,
-    Test_en,
+    scan_enable,
     top_width_0_height_0_subtile_0__pin_I0_0_,
     top_width_0_height_0_subtile_0__pin_I0_1_,
     top_width_0_height_0_subtile_0__pin_I0i_0_,
@@ -65,9 +65,9 @@ module grid_clb
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
-    input Test_en;
+    input scan_enable;
     input top_width_0_height_0_subtile_0__pin_I0_0_;
     input top_width_0_height_0_subtile_0__pin_I0_1_;
     input top_width_0_height_0_subtile_0__pin_I0i_0_;
@@ -127,9 +127,9 @@ module grid_clb
     output bottom_width_0_height_0_subtile_0__pin_cout_0_;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
-    wire Test_en;
+    wire scan_enable;
     wire top_width_0_height_0_subtile_0__pin_I0_0_;
     wire top_width_0_height_0_subtile_0__pin_I0_1_;
     wire top_width_0_height_0_subtile_0__pin_I0i_0_;
@@ -191,9 +191,9 @@ module grid_clb
 
     logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .clb_I0({top_width_0_height_0_subtile_0__pin_I0_0_, top_width_0_height_0_subtile_0__pin_I0_1_}),
         .clb_I0i({top_width_0_height_0_subtile_0__pin_I0i_0_, top_width_0_height_0_subtile_0__pin_I0i_1_}),
         .clb_I1({top_width_0_height_0_subtile_0__pin_I1_0_, top_width_0_height_0_subtile_0__pin_I1_1_}),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_bottom_bottom.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_bottom_bottom.v
index 053e8b5..184ee0d 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_bottom_bottom.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_bottom_bottom.v
@@ -2,12 +2,12 @@
 //netlist name: FPGA88_SOFA_A
 module grid_io_bottom_bottom
 (
-    IO_ISOL_N,
-    pReset,
+    isol_n,
+    prog_reset,
     prog_clk,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_io_soc_in,
+    gfpga_pad_io_soc_out,
+    gfpga_pad_io_soc_dir,
     top_width_0_height_0_subtile_0__pin_outpad_0_,
     top_width_0_height_0_subtile_1__pin_outpad_0_,
     top_width_0_height_0_subtile_2__pin_outpad_0_,
@@ -20,12 +20,12 @@ module grid_io_bottom_bottom
     ccff_tail
 );
 
-    input IO_ISOL_N;
-    input pReset;
+    input isol_n;
+    input prog_reset;
     input prog_clk;
-    input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    input [0:3]gfpga_pad_io_soc_in;
+    output [0:3]gfpga_pad_io_soc_out;
+    output [0:3]gfpga_pad_io_soc_dir;
     input top_width_0_height_0_subtile_0__pin_outpad_0_;
     input top_width_0_height_0_subtile_1__pin_outpad_0_;
     input top_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -37,12 +37,12 @@ module grid_io_bottom_bottom
     output top_width_0_height_0_subtile_3__pin_inpad_0_;
     output ccff_tail;
 
-    wire IO_ISOL_N;
-    wire pReset;
+    wire isol_n;
+    wire prog_reset;
     wire prog_clk;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire [0:3]gfpga_pad_io_soc_in;
+    wire [0:3]gfpga_pad_io_soc_out;
+    wire [0:3]gfpga_pad_io_soc_dir;
     wire top_width_0_height_0_subtile_0__pin_outpad_0_;
     wire top_width_0_height_0_subtile_1__pin_outpad_0_;
     wire top_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -59,12 +59,12 @@ module grid_io_bottom_bottom
 
     logical_tile_io_mode_io_ logical_tile_io_mode_io__0
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
         .io_outpad(top_width_0_height_0_subtile_0__pin_outpad_0_),
         .ccff_head(ccff_head),
         .io_inpad(top_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -72,12 +72,12 @@ module grid_io_bottom_bottom
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__1
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
         .io_outpad(top_width_0_height_0_subtile_1__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__0_ccff_tail),
         .io_inpad(top_width_0_height_0_subtile_1__pin_inpad_0_),
@@ -85,12 +85,12 @@ module grid_io_bottom_bottom
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__2
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
         .io_outpad(top_width_0_height_0_subtile_2__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__1_ccff_tail),
         .io_inpad(top_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -98,12 +98,12 @@ module grid_io_bottom_bottom
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__3
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
         .io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__2_ccff_tail),
         .io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_left_left.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_left_left.v
index 5d235de..65d713a 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_left_left.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_left_left.v
@@ -2,12 +2,12 @@
 //netlist name: FPGA88_SOFA_A
 module grid_io_left_left
 (
-    IO_ISOL_N,
-    pReset,
+    isol_n,
+    prog_reset,
     prog_clk,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_io_soc_in,
+    gfpga_pad_io_soc_out,
+    gfpga_pad_io_soc_dir,
     right_width_0_height_0_subtile_0__pin_outpad_0_,
     right_width_0_height_0_subtile_1__pin_outpad_0_,
     right_width_0_height_0_subtile_2__pin_outpad_0_,
@@ -20,12 +20,12 @@ module grid_io_left_left
     ccff_tail
 );
 
-    input IO_ISOL_N;
-    input pReset;
+    input isol_n;
+    input prog_reset;
     input prog_clk;
-    input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    input [0:3]gfpga_pad_io_soc_in;
+    output [0:3]gfpga_pad_io_soc_out;
+    output [0:3]gfpga_pad_io_soc_dir;
     input right_width_0_height_0_subtile_0__pin_outpad_0_;
     input right_width_0_height_0_subtile_1__pin_outpad_0_;
     input right_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -37,12 +37,12 @@ module grid_io_left_left
     output right_width_0_height_0_subtile_3__pin_inpad_0_;
     output ccff_tail;
 
-    wire IO_ISOL_N;
-    wire pReset;
+    wire isol_n;
+    wire prog_reset;
     wire prog_clk;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire [0:3]gfpga_pad_io_soc_in;
+    wire [0:3]gfpga_pad_io_soc_out;
+    wire [0:3]gfpga_pad_io_soc_dir;
     wire right_width_0_height_0_subtile_0__pin_outpad_0_;
     wire right_width_0_height_0_subtile_1__pin_outpad_0_;
     wire right_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -59,12 +59,12 @@ module grid_io_left_left
 
     logical_tile_io_mode_io_ logical_tile_io_mode_io__0
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
         .io_outpad(right_width_0_height_0_subtile_0__pin_outpad_0_),
         .ccff_head(ccff_head),
         .io_inpad(right_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -72,12 +72,12 @@ module grid_io_left_left
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__1
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
         .io_outpad(right_width_0_height_0_subtile_1__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__0_ccff_tail),
         .io_inpad(right_width_0_height_0_subtile_1__pin_inpad_0_),
@@ -85,12 +85,12 @@ module grid_io_left_left
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__2
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
         .io_outpad(right_width_0_height_0_subtile_2__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__1_ccff_tail),
         .io_inpad(right_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -98,12 +98,12 @@ module grid_io_left_left
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__3
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
         .io_outpad(right_width_0_height_0_subtile_3__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__2_ccff_tail),
         .io_inpad(right_width_0_height_0_subtile_3__pin_inpad_0_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_right_right.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_right_right.v
index 42d3271..0e9d97d 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_right_right.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_right_right.v
@@ -2,12 +2,12 @@
 //netlist name: FPGA88_SOFA_A
 module grid_io_right_right
 (
-    IO_ISOL_N,
-    pReset,
+    isol_n,
+    prog_reset,
     prog_clk,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_io_soc_in,
+    gfpga_pad_io_soc_out,
+    gfpga_pad_io_soc_dir,
     left_width_0_height_0_subtile_0__pin_outpad_0_,
     left_width_0_height_0_subtile_1__pin_outpad_0_,
     left_width_0_height_0_subtile_2__pin_outpad_0_,
@@ -20,12 +20,12 @@ module grid_io_right_right
     ccff_tail
 );
 
-    input IO_ISOL_N;
-    input pReset;
+    input isol_n;
+    input prog_reset;
     input prog_clk;
-    input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    input [0:3]gfpga_pad_io_soc_in;
+    output [0:3]gfpga_pad_io_soc_out;
+    output [0:3]gfpga_pad_io_soc_dir;
     input left_width_0_height_0_subtile_0__pin_outpad_0_;
     input left_width_0_height_0_subtile_1__pin_outpad_0_;
     input left_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -37,12 +37,12 @@ module grid_io_right_right
     output left_width_0_height_0_subtile_3__pin_inpad_0_;
     output ccff_tail;
 
-    wire IO_ISOL_N;
-    wire pReset;
+    wire isol_n;
+    wire prog_reset;
     wire prog_clk;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire [0:3]gfpga_pad_io_soc_in;
+    wire [0:3]gfpga_pad_io_soc_out;
+    wire [0:3]gfpga_pad_io_soc_dir;
     wire left_width_0_height_0_subtile_0__pin_outpad_0_;
     wire left_width_0_height_0_subtile_1__pin_outpad_0_;
     wire left_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -59,12 +59,12 @@ module grid_io_right_right
 
     logical_tile_io_mode_io_ logical_tile_io_mode_io__0
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
         .io_outpad(left_width_0_height_0_subtile_0__pin_outpad_0_),
         .ccff_head(ccff_head),
         .io_inpad(left_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -72,12 +72,12 @@ module grid_io_right_right
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__1
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
         .io_outpad(left_width_0_height_0_subtile_1__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__0_ccff_tail),
         .io_inpad(left_width_0_height_0_subtile_1__pin_inpad_0_),
@@ -85,12 +85,12 @@ module grid_io_right_right
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__2
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
         .io_outpad(left_width_0_height_0_subtile_2__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__1_ccff_tail),
         .io_inpad(left_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -98,12 +98,12 @@ module grid_io_right_right
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__3
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
         .io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__2_ccff_tail),
         .io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_top_top.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_top_top.v
index b2f5320..d5ab728 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_top_top.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/grid_io_top_top.v
@@ -2,12 +2,12 @@
 //netlist name: FPGA88_SOFA_A
 module grid_io_top_top
 (
-    IO_ISOL_N,
-    pReset,
+    isol_n,
+    prog_reset,
     prog_clk,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_io_soc_in,
+    gfpga_pad_io_soc_out,
+    gfpga_pad_io_soc_dir,
     bottom_width_0_height_0_subtile_0__pin_outpad_0_,
     bottom_width_0_height_0_subtile_1__pin_outpad_0_,
     bottom_width_0_height_0_subtile_2__pin_outpad_0_,
@@ -20,12 +20,12 @@ module grid_io_top_top
     ccff_tail
 );
 
-    input IO_ISOL_N;
-    input pReset;
+    input isol_n;
+    input prog_reset;
     input prog_clk;
-    input [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    output [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    input [0:3]gfpga_pad_io_soc_in;
+    output [0:3]gfpga_pad_io_soc_out;
+    output [0:3]gfpga_pad_io_soc_dir;
     input bottom_width_0_height_0_subtile_0__pin_outpad_0_;
     input bottom_width_0_height_0_subtile_1__pin_outpad_0_;
     input bottom_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -37,12 +37,12 @@ module grid_io_top_top
     output bottom_width_0_height_0_subtile_3__pin_inpad_0_;
     output ccff_tail;
 
-    wire IO_ISOL_N;
-    wire pReset;
+    wire isol_n;
+    wire prog_reset;
     wire prog_clk;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    wire [0:3]gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire [0:3]gfpga_pad_io_soc_in;
+    wire [0:3]gfpga_pad_io_soc_out;
+    wire [0:3]gfpga_pad_io_soc_dir;
     wire bottom_width_0_height_0_subtile_0__pin_outpad_0_;
     wire bottom_width_0_height_0_subtile_1__pin_outpad_0_;
     wire bottom_width_0_height_0_subtile_2__pin_outpad_0_;
@@ -59,12 +59,12 @@ module grid_io_top_top
 
     logical_tile_io_mode_io_ logical_tile_io_mode_io__0
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[0]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[0]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[0]),
         .io_outpad(bottom_width_0_height_0_subtile_0__pin_outpad_0_),
         .ccff_head(ccff_head),
         .io_inpad(bottom_width_0_height_0_subtile_0__pin_inpad_0_),
@@ -72,12 +72,12 @@ module grid_io_top_top
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__1
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[1]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[1]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[1]),
         .io_outpad(bottom_width_0_height_0_subtile_1__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__0_ccff_tail),
         .io_inpad(bottom_width_0_height_0_subtile_1__pin_inpad_0_),
@@ -85,12 +85,12 @@ module grid_io_top_top
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__2
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[2]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[2]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[2]),
         .io_outpad(bottom_width_0_height_0_subtile_2__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__1_ccff_tail),
         .io_inpad(bottom_width_0_height_0_subtile_2__pin_inpad_0_),
@@ -98,12 +98,12 @@ module grid_io_top_top
     );
     logical_tile_io_mode_io_ logical_tile_io_mode_io__3
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in[3]),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out[3]),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir[3]),
         .io_outpad(bottom_width_0_height_0_subtile_3__pin_outpad_0_),
         .ccff_head(logical_tile_io_mode_io__2_ccff_tail),
         .io_inpad(bottom_width_0_height_0_subtile_3__pin_inpad_0_),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_clb_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_clb_.v
index 8b2da1e..473f444 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_clb_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_clb_.v
@@ -2,9 +2,9 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_clb_mode_clb_
 (
-    pReset,
+    prog_reset,
     prog_clk,
-    Test_en,
+    scan_enable,
     clb_I0,
     clb_I0i,
     clb_I1,
@@ -34,9 +34,9 @@ module logical_tile_clb_mode_clb_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
-    input Test_en;
+    input scan_enable;
     input [0:1]clb_I0;
     input [0:1]clb_I0i;
     input [0:1]clb_I1;
@@ -65,9 +65,9 @@ module logical_tile_clb_mode_clb_
     output clb_cout;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
-    wire Test_en;
+    wire scan_enable;
     wire [0:1]clb_I0;
     wire [0:1]clb_I0i;
     wire [0:1]clb_I1;
@@ -209,9 +209,9 @@ module logical_tile_clb_mode_clb_
 
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .fle_in({direct_interc_19_out, direct_interc_20_out, direct_interc_21_out, direct_interc_22_out}),
         .fle_reg_in(direct_interc_23_out),
         .fle_sc_in(direct_interc_24_out),
@@ -227,9 +227,9 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .fle_in({direct_interc_28_out, direct_interc_29_out, direct_interc_30_out, direct_interc_31_out}),
         .fle_reg_in(direct_interc_32_out),
         .fle_sc_in(direct_interc_33_out),
@@ -245,9 +245,9 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .fle_in({direct_interc_37_out, direct_interc_38_out, direct_interc_39_out, direct_interc_40_out}),
         .fle_reg_in(direct_interc_41_out),
         .fle_sc_in(direct_interc_42_out),
@@ -263,9 +263,9 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .fle_in({direct_interc_46_out, direct_interc_47_out, direct_interc_48_out, direct_interc_49_out}),
         .fle_reg_in(direct_interc_50_out),
         .fle_sc_in(direct_interc_51_out),
@@ -281,9 +281,9 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .fle_in({direct_interc_55_out, direct_interc_56_out, direct_interc_57_out, direct_interc_58_out}),
         .fle_reg_in(direct_interc_59_out),
         .fle_sc_in(direct_interc_60_out),
@@ -299,9 +299,9 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .fle_in({direct_interc_64_out, direct_interc_65_out, direct_interc_66_out, direct_interc_67_out}),
         .fle_reg_in(direct_interc_68_out),
         .fle_sc_in(direct_interc_69_out),
@@ -317,9 +317,9 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .fle_in({direct_interc_73_out, direct_interc_74_out, direct_interc_75_out, direct_interc_76_out}),
         .fle_reg_in(direct_interc_77_out),
         .fle_sc_in(direct_interc_78_out),
@@ -335,9 +335,9 @@ module logical_tile_clb_mode_clb_
     );
     logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .fle_in({direct_interc_82_out, direct_interc_83_out, direct_interc_84_out, direct_interc_85_out}),
         .fle_reg_in(direct_interc_86_out),
         .fle_sc_in(direct_interc_87_out),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle.v
index b19563a..45091c4 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle.v
@@ -2,9 +2,9 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_clb_mode_default__fle
 (
-    pReset,
+    prog_reset,
     prog_clk,
-    Test_en,
+    scan_enable,
     fle_in,
     fle_reg_in,
     fle_sc_in,
@@ -19,9 +19,9 @@ module logical_tile_clb_mode_default__fle
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
-    input Test_en;
+    input scan_enable;
     input [0:3]fle_in;
     input fle_reg_in;
     input fle_sc_in;
@@ -35,9 +35,9 @@ module logical_tile_clb_mode_default__fle
     output fle_cout;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
-    wire Test_en;
+    wire scan_enable;
     wire [0:3]fle_in;
     wire fle_reg_in;
     wire fle_sc_in;
@@ -66,9 +66,9 @@ module logical_tile_clb_mode_default__fle
 
     logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .fabric_in({direct_interc_5_out, direct_interc_6_out, direct_interc_7_out, direct_interc_8_out}),
         .fabric_reg_in(direct_interc_9_out),
         .fabric_sc_in(direct_interc_10_out),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
index 817e939..a28b131 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
@@ -2,9 +2,9 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_clb_mode_default__fle_mode_physical__fabric
 (
-    pReset,
+    prog_reset,
     prog_clk,
-    Test_en,
+    scan_enable,
     fabric_in,
     fabric_reg_in,
     fabric_sc_in,
@@ -19,9 +19,9 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
-    input Test_en;
+    input scan_enable;
     input [0:3]fabric_in;
     input fabric_reg_in;
     input fabric_sc_in;
@@ -35,9 +35,9 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     output fabric_cout;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
-    wire Test_en;
+    wire scan_enable;
     wire [0:3]fabric_in;
     wire fabric_reg_in;
     wire fabric_sc_in;
@@ -82,7 +82,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
 
     logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .frac_logic_in({direct_interc_3_out, direct_interc_4_out, direct_interc_5_out, direct_interc_6_out}),
         .frac_logic_cin(direct_interc_7_out),
@@ -93,7 +93,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     );
     logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0
     (
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .ff_D(mux_tree_size2_2_out),
         .ff_DI(direct_interc_8_out),
         .ff_reset(direct_interc_9_out),
@@ -102,7 +102,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     );
     logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1
     (
-        .Test_en(Test_en),
+        .scan_enable(scan_enable),
         .ff_D(mux_tree_size2_3_out),
         .ff_DI(direct_interc_11_out),
         .ff_reset(direct_interc_12_out),
@@ -139,7 +139,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     );
     mux_tree_size2_mem mem_fabric_out_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail),
         .ccff_tail(mux_tree_size2_mem_0_ccff_tail),
@@ -147,7 +147,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     );
     mux_tree_size2_mem mem_fabric_out_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_size2_mem_0_ccff_tail),
         .ccff_tail(mux_tree_size2_mem_1_ccff_tail),
@@ -155,7 +155,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     );
     mux_tree_size2_mem mem_ff_0_D_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_size2_mem_1_ccff_tail),
         .ccff_tail(mux_tree_size2_mem_2_ccff_tail),
@@ -163,7 +163,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric
     );
     mux_tree_size2_mem mem_ff_1_D_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_size2_mem_2_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v
index 72a652c..eb2974e 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
 (
-    Test_en,
+    scan_enable,
     ff_D,
     ff_DI,
     ff_reset,
@@ -10,14 +10,14 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
     ff_clk
 );
 
-    input Test_en;
+    input scan_enable;
     input ff_D;
     input ff_DI;
     input ff_reset;
     output ff_Q;
     input ff_clk;
 
-    wire Test_en;
+    wire scan_enable;
     wire ff_D;
     wire ff_DI;
     wire ff_reset;
@@ -26,7 +26,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff
 
     sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_
     (
-        .SCE(Test_en),
+        .SCE(scan_enable),
         .D(ff_D),
         .SCD(ff_DI),
         .RESET_B(ff_reset),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v
index 87e59c3..86236b0 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic
 (
-    pReset,
+    prog_reset,
     prog_clk,
     frac_logic_in,
     frac_logic_cin,
@@ -12,7 +12,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:3]frac_logic_in;
     input frac_logic_cin;
@@ -21,7 +21,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
     output frac_logic_cout;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:3]frac_logic_in;
     wire frac_logic_cin;
@@ -49,7 +49,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
 
     logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .frac_lut4_in({direct_interc_2_out, direct_interc_3_out, mux_tree_size2_1_out, direct_interc_4_out}),
         .ccff_head(ccff_head),
@@ -81,7 +81,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
     );
     mux_tree_size2_mem mem_frac_logic_out_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail),
         .ccff_tail(mux_tree_size2_mem_0_ccff_tail),
@@ -89,7 +89,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
     );
     mux_tree_size2_mem mem_frac_lut4_0_in_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_size2_mem_0_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v
index 03b1192..cd58b06 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4
 (
-    pReset,
+    prog_reset,
     prog_clk,
     frac_lut4_in,
     ccff_head,
@@ -12,7 +12,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:3]frac_lut4_in;
     input ccff_head;
@@ -21,7 +21,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
     output frac_lut4_lut4_out;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:3]frac_lut4_in;
     wire ccff_head;
@@ -47,7 +47,7 @@ module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__fr
     );
     frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_io_mode_io_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_io_mode_io_.v
index 73136e0..dbb1895 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_io_mode_io_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_io_mode_io_.v
@@ -2,35 +2,35 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_io_mode_io_
 (
-    IO_ISOL_N,
-    pReset,
+    isol_n,
+    prog_reset,
     prog_clk,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_io_soc_in,
+    gfpga_pad_io_soc_out,
+    gfpga_pad_io_soc_dir,
     io_outpad,
     ccff_head,
     io_inpad,
     ccff_tail
 );
 
-    input IO_ISOL_N;
-    input pReset;
+    input isol_n;
+    input prog_reset;
     input prog_clk;
-    input gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    output gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    output gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    input gfpga_pad_io_soc_in;
+    output gfpga_pad_io_soc_out;
+    output gfpga_pad_io_soc_dir;
     input io_outpad;
     input ccff_head;
     output io_inpad;
     output ccff_tail;
 
-    wire IO_ISOL_N;
-    wire pReset;
+    wire isol_n;
+    wire prog_reset;
     wire prog_clk;
-    wire gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    wire gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire gfpga_pad_io_soc_in;
+    wire gfpga_pad_io_soc_out;
+    wire gfpga_pad_io_soc_dir;
     wire io_outpad;
     wire ccff_head;
     wire io_inpad;
@@ -40,12 +40,12 @@ module logical_tile_io_mode_io_
 
     logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .pReset(pReset),
+        .isol_n(isol_n),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
-        .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
+        .gfpga_pad_io_soc_in(gfpga_pad_io_soc_in),
+        .gfpga_pad_io_soc_out(gfpga_pad_io_soc_out),
+        .gfpga_pad_io_soc_dir(gfpga_pad_io_soc_dir),
         .iopad_outpad(direct_interc_1_out),
         .ccff_head(ccff_head),
         .iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_io_mode_physical__iopad.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_io_mode_physical__iopad.v
index 3b88cdc..08f0023 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_io_mode_physical__iopad.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/lb/logical_tile_io_mode_physical__iopad.v
@@ -2,58 +2,58 @@
 //netlist name: FPGA88_SOFA_A
 module logical_tile_io_mode_physical__iopad
 (
-    IO_ISOL_N,
-    pReset,
+    isol_n,
+    prog_reset,
     prog_clk,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
-    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
+    gfpga_pad_io_soc_in,
+    gfpga_pad_io_soc_out,
+    gfpga_pad_io_soc_dir,
     iopad_outpad,
     ccff_head,
     iopad_inpad,
     ccff_tail
 );
 
-    input IO_ISOL_N;
-    input pReset;
+    input isol_n;
+    input prog_reset;
     input prog_clk;
-    input gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    output gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    output gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    input gfpga_pad_io_soc_in;
+    output gfpga_pad_io_soc_out;
+    output gfpga_pad_io_soc_dir;
     input iopad_outpad;
     input ccff_head;
     output iopad_inpad;
     output ccff_tail;
 
-    wire IO_ISOL_N;
-    wire pReset;
+    wire isol_n;
+    wire prog_reset;
     wire prog_clk;
-    wire gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
-    wire gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
-    wire gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
+    wire gfpga_pad_io_soc_in;
+    wire gfpga_pad_io_soc_out;
+    wire gfpga_pad_io_soc_dir;
     wire iopad_outpad;
     wire ccff_head;
     wire iopad_inpad;
     wire ccff_tail;
-    wire EMBEDDED_IO_HD_0_en;
+    wire io_0_en;
 
-    EMBEDDED_IO_HD EMBEDDED_IO_HD_0_
+    io io_0_
     (
-        .IO_ISOL_N(IO_ISOL_N),
-        .SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
-        .SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
-        .SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
+        .IO_ISOL_N(isol_n),
+        .SOC_IN(gfpga_pad_io_soc_in),
+        .SOC_OUT(gfpga_pad_io_soc_out),
+        .SOC_DIR(gfpga_pad_io_soc_dir),
         .FPGA_OUT(iopad_outpad),
-        .FPGA_DIR(EMBEDDED_IO_HD_0_en),
+        .FPGA_DIR(io_0_en),
         .FPGA_IN(iopad_inpad)
     );
-    EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem
+    io_sky130_fd_sc_hd__dfrtp_1_mem io_sky130_fd_sc_hd__dfrtp_1_mem
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(ccff_tail),
-        .mem_out(EMBEDDED_IO_HD_0_en)
+        .mem_out(io_0_en)
     );
 endmodule
 
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cbx_1__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cbx_1__0_.v
index 44990ca..872e897 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cbx_1__0_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cbx_1__0_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module cbx_1__0_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chanx_left_in,
     chanx_right_in,
@@ -16,7 +16,7 @@ module cbx_1__0_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chanx_left_in;
     input [0:29]chanx_right_in;
@@ -29,7 +29,7 @@ module cbx_1__0_
     output bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chanx_left_in;
     wire [0:29]chanx_right_in;
@@ -143,7 +143,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
@@ -151,7 +151,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
@@ -159,7 +159,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
@@ -167,7 +167,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cbx_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cbx_1__1_.v
index b218cae..49ef1ce 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cbx_1__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cbx_1__1_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module cbx_1__1_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chanx_left_in,
     chanx_right_in,
@@ -28,7 +28,7 @@ module cbx_1__1_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chanx_left_in;
     input [0:29]chanx_right_in;
@@ -53,7 +53,7 @@ module cbx_1__1_
     output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chanx_left_in;
     wire [0:29]chanx_right_in;
@@ -243,7 +243,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
@@ -251,7 +251,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
@@ -259,7 +259,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
@@ -267,7 +267,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
@@ -275,7 +275,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_8
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
@@ -283,7 +283,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
@@ -291,7 +291,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
@@ -299,7 +299,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_14
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
@@ -363,7 +363,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
@@ -371,7 +371,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
@@ -379,7 +379,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
@@ -387,7 +387,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
@@ -395,7 +395,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_9
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
@@ -403,7 +403,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
@@ -411,7 +411,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
@@ -419,7 +419,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_15
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cbx_1__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cbx_1__8_.v
index 11749f0..61b52dd 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cbx_1__8_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cbx_1__8_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module cbx_1__8_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chanx_left_in,
     chanx_right_in,
@@ -32,7 +32,7 @@ module cbx_1__8_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chanx_left_in;
     input [0:29]chanx_right_in;
@@ -61,7 +61,7 @@ module cbx_1__8_
     output bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chanx_left_in;
     wire [0:29]chanx_right_in;
@@ -295,7 +295,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_bottom_ipin_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
@@ -303,7 +303,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_bottom_ipin_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
@@ -311,7 +311,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_bottom_ipin_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
@@ -319,7 +319,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_bottom_ipin_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
@@ -327,7 +327,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
@@ -335,7 +335,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
@@ -343,7 +343,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
@@ -351,7 +351,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
@@ -359,7 +359,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_8
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail),
@@ -367,7 +367,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail),
@@ -375,7 +375,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail),
@@ -383,7 +383,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_top_ipin_14
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail),
@@ -447,7 +447,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
@@ -455,7 +455,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
@@ -463,7 +463,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
@@ -471,7 +471,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
@@ -479,7 +479,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_9
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
@@ -487,7 +487,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
@@ -495,7 +495,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
@@ -503,7 +503,7 @@ assign chanx_left_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_top_ipin_15
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cby_0__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cby_0__1_.v
index b25d4b1..bd7d02a 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cby_0__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cby_0__1_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module cby_0__1_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chany_bottom_in,
     chany_top_in,
@@ -16,7 +16,7 @@ module cby_0__1_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chany_bottom_in;
     input [0:29]chany_top_in;
@@ -29,7 +29,7 @@ module cby_0__1_
     output left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chany_bottom_in;
     wire [0:29]chany_top_in;
@@ -143,7 +143,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
@@ -151,7 +151,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
@@ -159,7 +159,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
@@ -167,7 +167,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cby_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cby_1__1_.v
index e07ffde..6f6be57 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cby_1__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cby_1__1_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module cby_1__1_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chany_bottom_in,
     chany_top_in,
@@ -28,7 +28,7 @@ module cby_1__1_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chany_bottom_in;
     input [0:29]chany_top_in;
@@ -53,7 +53,7 @@ module cby_1__1_
     output left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chany_bottom_in;
     wire [0:29]chany_top_in;
@@ -243,7 +243,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
@@ -251,7 +251,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
@@ -259,7 +259,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
@@ -267,7 +267,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
@@ -275,7 +275,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_8
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
@@ -283,7 +283,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
@@ -291,7 +291,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
@@ -299,7 +299,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_14
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
@@ -363,7 +363,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
@@ -371,7 +371,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
@@ -379,7 +379,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
@@ -387,7 +387,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
@@ -395,7 +395,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_9
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
@@ -403,7 +403,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
@@ -411,7 +411,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
@@ -419,7 +419,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_15
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cby_8__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cby_8__1_.v
index 3400642..fa7c84d 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cby_8__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/cby_8__1_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module cby_8__1_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chany_bottom_in,
     chany_top_in,
@@ -32,7 +32,7 @@ module cby_8__1_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chany_bottom_in;
     input [0:29]chany_top_in;
@@ -61,7 +61,7 @@ module cby_8__1_
     output left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chany_bottom_in;
     wire [0:29]chany_top_in;
@@ -295,7 +295,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_left_ipin_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
@@ -303,7 +303,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_left_ipin_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
@@ -311,7 +311,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_left_ipin_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
@@ -319,7 +319,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_left_ipin_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
@@ -327,7 +327,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
@@ -335,7 +335,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
@@ -343,7 +343,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
@@ -351,7 +351,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
@@ -359,7 +359,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_8
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_8_ccff_tail),
@@ -367,7 +367,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_9_ccff_tail),
@@ -375,7 +375,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_10_ccff_tail),
@@ -383,7 +383,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size12_mem mem_right_ipin_14
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_11_ccff_tail),
@@ -447,7 +447,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
@@ -455,7 +455,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
@@ -463,7 +463,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
@@ -471,7 +471,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
@@ -479,7 +479,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_9
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
@@ -487,7 +487,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
@@ -495,7 +495,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
@@ -503,7 +503,7 @@ assign chany_bottom_out[29] = chany_top_in[29];
     );
     mux_tree_tapbuf_size10_mem mem_right_ipin_15
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_11_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_0__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_0__0_.v
index cbaa50a..9951895 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_0__0_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_0__0_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module sb_0__0_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chany_top_in,
     top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
@@ -20,7 +20,7 @@ module sb_0__0_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chany_top_in;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
@@ -37,7 +37,7 @@ module sb_0__0_
     output [0:29]chanx_right_out;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chany_top_in;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
@@ -215,7 +215,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@@ -223,7 +223,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@@ -231,7 +231,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@@ -239,7 +239,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@@ -471,7 +471,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@@ -479,7 +479,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@@ -487,7 +487,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_8
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@@ -495,7 +495,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@@ -503,7 +503,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@@ -511,7 +511,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_14
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@@ -519,7 +519,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_16
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
@@ -527,7 +527,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_18
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
@@ -535,7 +535,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
@@ -543,7 +543,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_30
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
@@ -551,7 +551,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_32
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
@@ -559,7 +559,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_34
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
@@ -567,7 +567,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
@@ -575,7 +575,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_46
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
@@ -583,7 +583,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_48
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
@@ -591,7 +591,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_50
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
@@ -599,7 +599,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
@@ -607,7 +607,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
@@ -615,7 +615,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_8
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
@@ -623,7 +623,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
@@ -631,7 +631,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
@@ -639,7 +639,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_14
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
@@ -647,7 +647,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_16
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
@@ -655,7 +655,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_18
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
@@ -663,7 +663,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
@@ -671,7 +671,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_30
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
@@ -679,7 +679,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_32
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
@@ -687,7 +687,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_34
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail),
@@ -695,7 +695,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_28_ccff_tail),
@@ -703,7 +703,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_46
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_28_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_29_ccff_tail),
@@ -711,7 +711,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_48
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_29_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_30_ccff_tail),
@@ -719,7 +719,7 @@ assign chany_top_out[28] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_50
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_30_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_0__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_0__1_.v
index d28f361..9e83a5c 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_0__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_0__1_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module sb_0__1_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chany_top_in,
     top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
@@ -30,7 +30,7 @@ module sb_0__1_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chany_top_in;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
@@ -57,7 +57,7 @@ module sb_0__1_
     output [0:29]chany_bottom_out;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chany_top_in;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
@@ -309,7 +309,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_top_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
@@ -317,7 +317,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_top_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
@@ -325,7 +325,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_top_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
@@ -333,7 +333,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_bottom_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
@@ -341,7 +341,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_bottom_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
@@ -433,7 +433,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_top_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
@@ -441,7 +441,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_top_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
@@ -449,7 +449,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_top_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
@@ -457,7 +457,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_top_track_20
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
@@ -465,7 +465,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
@@ -473,7 +473,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
@@ -481,7 +481,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_8
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
@@ -489,7 +489,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
@@ -497,7 +497,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
@@ -505,7 +505,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
@@ -513,7 +513,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_21
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail),
@@ -521,7 +521,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail),
@@ -571,7 +571,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_top_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
@@ -579,7 +579,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
@@ -587,7 +587,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
@@ -595,7 +595,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@@ -603,7 +603,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
@@ -611,7 +611,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_37
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
@@ -689,7 +689,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_top_track_36
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
@@ -697,7 +697,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_top_track_52
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
@@ -705,7 +705,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_right_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
@@ -713,7 +713,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_right_track_14
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
@@ -721,7 +721,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_right_track_16
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
@@ -729,7 +729,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_right_track_18
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail),
@@ -737,7 +737,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_right_track_20
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail),
@@ -745,7 +745,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_right_track_22
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_7_ccff_tail),
@@ -753,7 +753,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_right_track_36
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_8_ccff_tail),
@@ -761,7 +761,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_bottom_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_9_ccff_tail),
@@ -832,7 +832,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@@ -840,7 +840,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_24
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@@ -848,7 +848,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_26
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@@ -856,7 +856,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@@ -864,7 +864,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_30
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
@@ -872,7 +872,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_32
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
@@ -880,7 +880,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_34
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
@@ -888,7 +888,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_50
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
@@ -896,7 +896,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_53
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_9_ccff_tail),
         .ccff_tail(ccff_tail),
@@ -960,7 +960,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_38
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@@ -968,7 +968,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_40
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@@ -976,7 +976,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@@ -984,7 +984,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_46
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@@ -992,7 +992,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_48
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@@ -1000,7 +1000,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_52
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@@ -1008,7 +1008,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_54
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
@@ -1016,7 +1016,7 @@ assign chany_top_out[29] = chany_bottom_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_56
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_0__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_0__8_.v
index a9fc3df..e154d41 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_0__8_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_0__8_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module sb_0__8_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chanx_right_in,
     right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
@@ -28,7 +28,7 @@ module sb_0__8_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chanx_right_in;
     input right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
@@ -53,7 +53,7 @@ module sb_0__8_
     output [0:29]chany_bottom_out;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chanx_right_in;
     wire right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
@@ -277,7 +277,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
@@ -285,7 +285,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
@@ -293,7 +293,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
@@ -301,7 +301,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@@ -309,7 +309,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_8
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
@@ -317,7 +317,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
@@ -416,7 +416,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@@ -424,7 +424,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_14
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@@ -432,7 +432,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_16
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@@ -440,7 +440,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@@ -448,7 +448,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_30
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
@@ -456,7 +456,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_32
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
@@ -464,7 +464,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_34
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
@@ -472,7 +472,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
@@ -480,7 +480,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_46
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
@@ -488,7 +488,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_48
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
@@ -496,7 +496,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_58
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
@@ -504,7 +504,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail),
@@ -512,7 +512,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail),
@@ -723,7 +723,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_18
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@@ -731,7 +731,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_20
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@@ -739,7 +739,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_22
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@@ -747,7 +747,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_24
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@@ -755,7 +755,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_26
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@@ -763,7 +763,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_36
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@@ -771,7 +771,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_38
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
@@ -779,7 +779,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_40
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
@@ -787,7 +787,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_42
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
@@ -795,7 +795,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_50
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
@@ -803,7 +803,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_52
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
@@ -811,7 +811,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_54
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
@@ -819,7 +819,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_right_track_56
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
@@ -827,7 +827,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
@@ -835,7 +835,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
@@ -843,7 +843,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_9
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
@@ -851,7 +851,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
@@ -859,7 +859,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
@@ -867,7 +867,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_15
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
@@ -875,7 +875,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_17
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
@@ -883,7 +883,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_19
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
@@ -891,7 +891,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
@@ -899,7 +899,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_31
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
@@ -907,7 +907,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_33
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
@@ -915,7 +915,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_35
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
@@ -923,7 +923,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
@@ -931,7 +931,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_47
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
@@ -939,7 +939,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_49
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_27_ccff_tail),
@@ -947,7 +947,7 @@ assign chany_bottom_out[29] = chanx_right_in[29];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_51
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_27_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_1__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_1__0_.v
index 8e5fb2d..8c735e6 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_1__0_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_1__0_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module sb_1__0_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chany_top_in,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
@@ -30,7 +30,7 @@ module sb_1__0_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chany_top_in;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@@ -57,7 +57,7 @@ module sb_1__0_
     output [0:29]chanx_left_out;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chany_top_in;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@@ -306,7 +306,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_top_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
@@ -314,7 +314,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_right_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
@@ -322,7 +322,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_right_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
@@ -330,7 +330,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_left_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
@@ -338,7 +338,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_left_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
@@ -437,7 +437,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_top_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
@@ -445,7 +445,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_top_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
@@ -453,7 +453,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_top_track_8
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
@@ -461,7 +461,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
@@ -469,7 +469,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
@@ -477,7 +477,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
@@ -485,7 +485,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
@@ -493,7 +493,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_20
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
@@ -501,7 +501,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
@@ -509,7 +509,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_left_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
@@ -517,7 +517,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_left_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail),
@@ -525,7 +525,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_left_track_21
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_11_ccff_tail),
@@ -533,7 +533,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_left_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_11_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_12_ccff_tail),
@@ -583,7 +583,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_top_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
@@ -591,7 +591,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_top_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
@@ -599,7 +599,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_36
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
@@ -607,7 +607,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@@ -615,7 +615,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
@@ -623,7 +623,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_37
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_12_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
@@ -673,7 +673,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_top_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
@@ -681,7 +681,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_top_track_14
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
@@ -689,7 +689,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_top_track_16
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
@@ -697,7 +697,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_top_track_18
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
@@ -705,7 +705,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_left_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
@@ -713,7 +713,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_left_track_53
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
         .ccff_tail(ccff_tail),
@@ -770,7 +770,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_20
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@@ -778,7 +778,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_22
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@@ -786,7 +786,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_24
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@@ -794,7 +794,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_26
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@@ -802,7 +802,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_36
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
@@ -810,7 +810,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
@@ -818,7 +818,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_right_track_52
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
@@ -903,7 +903,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@@ -911,7 +911,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_30
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@@ -919,7 +919,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_32
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@@ -927,7 +927,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_34
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@@ -935,7 +935,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_40
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@@ -943,7 +943,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_42
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@@ -951,7 +951,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
@@ -959,7 +959,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_46
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
@@ -967,7 +967,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_48
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
@@ -975,7 +975,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_50
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
@@ -983,7 +983,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_58
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_1__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_1__1_.v
index 834c68d..87b0f60 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_1__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_1__1_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module sb_1__1_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chany_top_in,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
@@ -48,7 +48,7 @@ module sb_1__1_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chany_top_in;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@@ -93,7 +93,7 @@ module sb_1__1_
     output [0:29]chanx_left_out;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chany_top_in;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@@ -403,7 +403,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_top_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail),
@@ -411,7 +411,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_top_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail),
@@ -419,7 +419,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_right_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail),
@@ -427,7 +427,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_right_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_3_ccff_tail),
@@ -435,7 +435,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_bottom_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_4_ccff_tail),
@@ -443,7 +443,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_bottom_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_5_ccff_tail),
@@ -451,7 +451,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_left_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_6_ccff_tail),
@@ -459,7 +459,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_left_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_7_ccff_tail),
@@ -551,7 +551,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_top_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
@@ -559,7 +559,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_top_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
@@ -567,7 +567,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_top_track_20
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
@@ -575,7 +575,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_right_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
@@ -583,7 +583,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_right_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail),
@@ -591,7 +591,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_right_track_20
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail),
@@ -599,7 +599,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_bottom_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail),
@@ -607,7 +607,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_bottom_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail),
@@ -615,7 +615,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_bottom_track_21
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail),
@@ -623,7 +623,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_left_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail),
@@ -631,7 +631,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_left_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail),
@@ -639,7 +639,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size10_mem mem_left_track_21
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail),
@@ -703,7 +703,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size12_mem mem_top_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail),
@@ -711,7 +711,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size12_mem mem_top_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail),
@@ -719,7 +719,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size12_mem mem_right_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail),
@@ -727,7 +727,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size12_mem mem_right_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail),
@@ -735,7 +735,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size12_mem mem_bottom_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail),
@@ -743,7 +743,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size12_mem mem_bottom_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail),
@@ -751,7 +751,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size12_mem mem_left_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail),
@@ -759,7 +759,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size12_mem mem_left_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail),
@@ -795,7 +795,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size9_mem mem_top_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
@@ -803,7 +803,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size9_mem mem_right_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
@@ -811,7 +811,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size9_mem mem_bottom_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail),
@@ -819,7 +819,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size9_mem mem_left_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail),
@@ -911,7 +911,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_top_track_36
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
@@ -919,7 +919,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_top_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
@@ -927,7 +927,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_top_track_52
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
@@ -935,7 +935,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_36
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
@@ -943,7 +943,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
@@ -951,7 +951,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_52
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
@@ -959,7 +959,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_37
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
@@ -967,7 +967,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
@@ -975,7 +975,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_53
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
@@ -983,7 +983,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_left_track_37
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
@@ -991,7 +991,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_left_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_10_ccff_tail),
@@ -999,7 +999,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_left_track_53
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_10_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_1__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_1__8_.v
index 0d620a7..7ab0304 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_1__8_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_1__8_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module sb_1__8_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chanx_right_in,
     right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
@@ -46,7 +46,7 @@ module sb_1__8_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chanx_right_in;
     input right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
@@ -89,7 +89,7 @@ module sb_1__8_
     output [0:29]chanx_left_out;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chanx_right_in;
     wire right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
@@ -340,7 +340,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size8_mem mem_right_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail),
@@ -348,7 +348,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size8_mem mem_right_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail),
@@ -356,7 +356,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size8_mem mem_left_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail),
@@ -385,7 +385,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size9_mem mem_right_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
@@ -393,7 +393,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size9_mem mem_left_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
@@ -401,7 +401,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size9_mem mem_left_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail),
@@ -437,7 +437,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_right_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail),
@@ -445,7 +445,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_right_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail),
@@ -453,7 +453,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_left_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail),
@@ -461,7 +461,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size11_mem mem_left_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_3_ccff_tail),
@@ -511,7 +511,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_right_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
@@ -519,7 +519,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_right_track_20
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
@@ -527,7 +527,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_right_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
@@ -535,7 +535,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_left_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
@@ -543,7 +543,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_left_track_21
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
@@ -551,7 +551,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size7_mem mem_left_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail),
@@ -608,7 +608,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_36
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
@@ -616,7 +616,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_right_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
@@ -624,7 +624,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
@@ -632,7 +632,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
@@ -640,7 +640,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
@@ -648,7 +648,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_9
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
@@ -656,7 +656,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size6_mem mem_left_track_37
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
@@ -699,7 +699,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_right_track_52
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
@@ -707,7 +707,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
@@ -715,7 +715,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
@@ -723,7 +723,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@@ -731,7 +731,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_53
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
         .ccff_tail(ccff_tail),
@@ -774,7 +774,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_bottom_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
@@ -782,7 +782,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_bottom_track_15
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
@@ -790,7 +790,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_bottom_track_17
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
@@ -798,7 +798,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_bottom_track_19
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
@@ -806,7 +806,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size4_mem mem_bottom_track_37
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
@@ -842,7 +842,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_21
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@@ -850,7 +850,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_23
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@@ -858,7 +858,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_25
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@@ -866,7 +866,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_27
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@@ -951,7 +951,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@@ -959,7 +959,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_31
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@@ -967,7 +967,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_33
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@@ -975,7 +975,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_35
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@@ -983,7 +983,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_39
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@@ -991,7 +991,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_41
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@@ -999,7 +999,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_43
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
@@ -1007,7 +1007,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
@@ -1015,7 +1015,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_47
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
@@ -1023,7 +1023,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_49
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
@@ -1031,7 +1031,7 @@ assign chanx_right_out[29] = chanx_left_in[28];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_51
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_8__0_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_8__0_.v
index 51920ee..a2f5e54 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_8__0_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_8__0_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module sb_8__0_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chany_top_in,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
@@ -28,7 +28,7 @@ module sb_8__0_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chany_top_in;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@@ -53,7 +53,7 @@ module sb_8__0_
     output [0:29]chanx_left_out;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chany_top_in;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@@ -269,7 +269,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size5_mem mem_top_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
@@ -277,7 +277,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size5_mem mem_top_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
@@ -285,7 +285,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size5_mem mem_top_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
@@ -293,7 +293,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size5_mem mem_top_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@@ -301,7 +301,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size5_mem mem_top_track_8
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
@@ -309,7 +309,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size5_mem mem_top_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
@@ -387,7 +387,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@@ -395,7 +395,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_14
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@@ -403,7 +403,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_16
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@@ -411,7 +411,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_18
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@@ -419,7 +419,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
@@ -427,7 +427,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_46
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
@@ -435,7 +435,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_48
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
@@ -443,7 +443,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size3_mem mem_top_track_50
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
@@ -451,7 +451,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
@@ -459,7 +459,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
@@ -663,7 +663,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_20
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@@ -671,7 +671,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_22
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@@ -679,7 +679,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_24
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@@ -687,7 +687,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_26
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@@ -695,7 +695,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@@ -703,7 +703,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_30
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@@ -711,7 +711,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_32
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
@@ -719,7 +719,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_34
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
@@ -727,7 +727,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_36
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
@@ -735,7 +735,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_38
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
@@ -743,7 +743,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_40
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
@@ -751,7 +751,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_top_track_42
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
@@ -759,7 +759,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
@@ -767,7 +767,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
@@ -775,7 +775,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_9
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
@@ -783,7 +783,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
@@ -791,7 +791,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
@@ -799,7 +799,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_15
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
@@ -807,7 +807,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_17
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
@@ -815,7 +815,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_19
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
@@ -823,7 +823,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
@@ -831,7 +831,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_31
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
@@ -839,7 +839,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_33
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
@@ -847,7 +847,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_35
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
@@ -855,7 +855,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
@@ -863,7 +863,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_47
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_25_ccff_tail),
@@ -871,7 +871,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_49
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_25_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_26_ccff_tail),
@@ -879,7 +879,7 @@ assign chany_top_out[26] = chanx_left_in[4];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_51
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_26_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_8__1_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_8__1_.v
index bdabe6b..b0b256a 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_8__1_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_8__1_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module sb_8__1_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chany_top_in,
     top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_,
@@ -46,7 +46,7 @@ module sb_8__1_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chany_top_in;
     input top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@@ -89,7 +89,7 @@ module sb_8__1_
     output [0:29]chanx_left_out;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chany_top_in;
     wire top_left_grid_right_width_0_height_0_subtile_0__pin_O_8_;
@@ -349,7 +349,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size9_mem mem_top_track_0
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
@@ -357,7 +357,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size9_mem mem_bottom_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
@@ -365,7 +365,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size9_mem mem_bottom_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail),
@@ -373,7 +373,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size9_mem mem_bottom_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail),
@@ -395,7 +395,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size8_mem mem_top_track_2
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail),
@@ -403,7 +403,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size8_mem mem_top_track_4
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail),
@@ -418,7 +418,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size10_mem mem_top_track_6
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
@@ -447,7 +447,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size11_mem mem_top_track_10
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail),
@@ -455,7 +455,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size11_mem mem_bottom_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail),
@@ -463,7 +463,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size11_mem mem_bottom_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail),
@@ -506,7 +506,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size7_mem mem_top_track_12
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail),
@@ -514,7 +514,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size7_mem mem_top_track_20
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail),
@@ -522,7 +522,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size7_mem mem_top_track_28
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail),
@@ -530,7 +530,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size7_mem mem_bottom_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail),
@@ -538,7 +538,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size7_mem mem_bottom_track_21
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail),
@@ -609,7 +609,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size6_mem mem_top_track_36
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
@@ -617,7 +617,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size6_mem mem_top_track_44
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
@@ -625,7 +625,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size6_mem mem_top_track_52
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
@@ -633,7 +633,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
@@ -641,7 +641,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size6_mem mem_bottom_track_53
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
@@ -649,7 +649,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size6_mem mem_left_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
@@ -657,7 +657,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size6_mem mem_left_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
@@ -665,7 +665,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size6_mem mem_left_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
@@ -673,7 +673,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size6_mem mem_left_track_9
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
@@ -709,7 +709,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_37
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
@@ -717,7 +717,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
@@ -725,7 +725,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size5_mem mem_left_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
@@ -733,7 +733,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size5_mem mem_left_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@@ -783,7 +783,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size4_mem mem_left_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
@@ -791,7 +791,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size4_mem mem_left_track_15
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
@@ -799,7 +799,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size4_mem mem_left_track_17
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
@@ -807,7 +807,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size4_mem mem_left_track_19
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
@@ -815,7 +815,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size4_mem mem_left_track_21
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
@@ -823,7 +823,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size4_mem mem_left_track_23
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail),
@@ -887,7 +887,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size3_mem mem_left_track_25
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@@ -895,7 +895,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size3_mem mem_left_track_27
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@@ -903,7 +903,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size3_mem mem_left_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@@ -911,7 +911,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size3_mem mem_left_track_31
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@@ -919,7 +919,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size3_mem mem_left_track_33
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
@@ -927,7 +927,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size3_mem mem_left_track_35
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
@@ -935,7 +935,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size3_mem mem_left_track_37
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
@@ -943,7 +943,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size3_mem mem_left_track_51
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
@@ -1000,7 +1000,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size2_mem mem_left_track_41
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@@ -1008,7 +1008,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size2_mem mem_left_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@@ -1016,7 +1016,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size2_mem mem_left_track_47
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@@ -1024,7 +1024,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size2_mem mem_left_track_49
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@@ -1032,7 +1032,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size2_mem mem_left_track_53
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@@ -1040,7 +1040,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size2_mem mem_left_track_55
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@@ -1048,7 +1048,7 @@ assign chanx_left_out[19] = left_bottom_grid_top_width_0_height_0_subtile_0__pin
     );
     mux_tree_tapbuf_size2_mem mem_left_track_57
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_8__8_.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_8__8_.v
index 79a9f96..071801a 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_8__8_.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/routing/sb_8__8_.v
@@ -2,7 +2,7 @@
 //netlist name: FPGA88_SOFA_A
 module sb_8__8_
 (
-    pReset,
+    prog_reset,
     prog_clk,
     chany_bottom_in,
     bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
@@ -36,7 +36,7 @@ module sb_8__8_
     ccff_tail
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input [0:29]chany_bottom_in;
     input bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
@@ -69,7 +69,7 @@ module sb_8__8_
     output [0:29]chanx_left_out;
     output ccff_tail;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire [0:29]chany_bottom_in;
     wire bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
@@ -359,7 +359,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(ccff_head),
         .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
@@ -367,7 +367,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail),
@@ -375,7 +375,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail),
@@ -383,7 +383,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail),
@@ -391,7 +391,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_9
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail),
@@ -399,7 +399,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_bottom_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_5_ccff_tail),
@@ -407,7 +407,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_1
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_6_ccff_tail),
@@ -415,7 +415,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_3
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_7_ccff_tail),
@@ -423,7 +423,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_5
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_8_ccff_tail),
@@ -431,7 +431,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_7
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_9_ccff_tail),
@@ -439,7 +439,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_9
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_10_ccff_tail),
@@ -447,7 +447,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size5_mem mem_left_track_11
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size5_mem_11_ccff_tail),
@@ -630,7 +630,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
@@ -638,7 +638,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_15
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
@@ -646,7 +646,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_17
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
@@ -654,7 +654,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_19
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
@@ -662,7 +662,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_21
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
@@ -670,7 +670,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_23
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
@@ -678,7 +678,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_25
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
@@ -686,7 +686,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_27
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
@@ -694,7 +694,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_53
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
@@ -702,7 +702,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_55
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
@@ -710,7 +710,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_57
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
@@ -718,7 +718,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_bottom_track_59
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
@@ -726,7 +726,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_19
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
@@ -734,7 +734,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_21
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
@@ -742,7 +742,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_23
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
@@ -750,7 +750,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_25
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
@@ -758,7 +758,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_27
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
@@ -766,7 +766,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_37
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_14_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail),
@@ -774,7 +774,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_39
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail),
@@ -782,7 +782,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_41
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail),
@@ -790,7 +790,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_43
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail),
@@ -798,7 +798,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_51
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_17_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail),
@@ -806,7 +806,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_53
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail),
@@ -814,7 +814,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_55
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_23_ccff_tail),
@@ -822,7 +822,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size2_mem mem_left_track_57
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_23_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size2_mem_24_ccff_tail),
@@ -963,7 +963,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
@@ -971,7 +971,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_31
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
@@ -979,7 +979,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_33
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
@@ -987,7 +987,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_35
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
@@ -995,7 +995,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
@@ -1003,7 +1003,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_47
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
@@ -1011,7 +1011,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_49
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
@@ -1019,7 +1019,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_bottom_track_51
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
@@ -1027,7 +1027,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_13
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size5_mem_11_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
@@ -1035,7 +1035,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_15
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
@@ -1043,7 +1043,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_17
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
@@ -1051,7 +1051,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_29
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail),
@@ -1059,7 +1059,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_31
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail),
@@ -1067,7 +1067,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_33
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_13_ccff_tail),
@@ -1075,7 +1075,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_35
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_13_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_14_ccff_tail),
@@ -1083,7 +1083,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_45
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_15_ccff_tail),
@@ -1091,7 +1091,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_47
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_15_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_16_ccff_tail),
@@ -1099,7 +1099,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_49
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size3_mem_16_ccff_tail),
         .ccff_tail(mux_tree_tapbuf_size3_mem_17_ccff_tail),
@@ -1107,7 +1107,7 @@ assign chany_bottom_out[21] = chanx_left_in[22];
     );
     mux_tree_tapbuf_size3_mem mem_left_track_59
     (
-        .pReset(pReset),
+        .prog_reset(prog_reset),
         .prog_clk(prog_clk),
         .ccff_head(mux_tree_tapbuf_size2_mem_24_ccff_tail),
         .ccff_tail(ccff_tail),
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/memories.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/memories.v
index 7c86232..ac63aaa 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/memories.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/memories.v
@@ -2,20 +2,20 @@
 //netlist name: FPGA88_SOFA_A
 module mux_tree_tapbuf_size12_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:3]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -24,28 +24,28 @@ module mux_tree_tapbuf_size12_mem
 assign ccff_tail = mem_out[3];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[1]),
         .Q(mem_out[2])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[2]),
         .Q(mem_out[3])
@@ -54,20 +54,20 @@ endmodule
 
 module mux_tree_tapbuf_size10_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:3]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -76,28 +76,28 @@ module mux_tree_tapbuf_size10_mem
 assign ccff_tail = mem_out[3];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[1]),
         .Q(mem_out[2])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[2]),
         .Q(mem_out[3])
@@ -106,20 +106,20 @@ endmodule
 
 module mux_tree_tapbuf_size3_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:1]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -128,14 +128,14 @@ module mux_tree_tapbuf_size3_mem
 assign ccff_tail = mem_out[1];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
@@ -144,20 +144,20 @@ endmodule
 
 module mux_tree_tapbuf_size7_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:2]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -166,21 +166,21 @@ module mux_tree_tapbuf_size7_mem
 assign ccff_tail = mem_out[2];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[1]),
         .Q(mem_out[2])
@@ -189,20 +189,20 @@ endmodule
 
 module mux_tree_tapbuf_size2_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:1]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -211,14 +211,14 @@ module mux_tree_tapbuf_size2_mem
 assign ccff_tail = mem_out[1];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
@@ -227,20 +227,20 @@ endmodule
 
 module mux_tree_tapbuf_size5_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:2]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -249,21 +249,21 @@ module mux_tree_tapbuf_size5_mem
 assign ccff_tail = mem_out[2];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[1]),
         .Q(mem_out[2])
@@ -272,20 +272,20 @@ endmodule
 
 module mux_tree_tapbuf_size6_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:2]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -294,21 +294,21 @@ module mux_tree_tapbuf_size6_mem
 assign ccff_tail = mem_out[2];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[1]),
         .Q(mem_out[2])
@@ -317,20 +317,20 @@ endmodule
 
 module mux_tree_tapbuf_size4_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:2]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -339,21 +339,21 @@ module mux_tree_tapbuf_size4_mem
 assign ccff_tail = mem_out[2];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[1]),
         .Q(mem_out[2])
@@ -362,20 +362,20 @@ endmodule
 
 module mux_tree_tapbuf_size11_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:3]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -384,28 +384,28 @@ module mux_tree_tapbuf_size11_mem
 assign ccff_tail = mem_out[3];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[1]),
         .Q(mem_out[2])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[2]),
         .Q(mem_out[3])
@@ -414,20 +414,20 @@ endmodule
 
 module mux_tree_tapbuf_size9_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:3]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -436,28 +436,28 @@ module mux_tree_tapbuf_size9_mem
 assign ccff_tail = mem_out[3];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[1]),
         .Q(mem_out[2])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[2]),
         .Q(mem_out[3])
@@ -466,20 +466,20 @@ endmodule
 
 module mux_tree_tapbuf_size8_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:3]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -488,28 +488,28 @@ module mux_tree_tapbuf_size8_mem
 assign ccff_tail = mem_out[3];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[1]),
         .Q(mem_out[2])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[2]),
         .Q(mem_out[3])
@@ -518,20 +518,20 @@ endmodule
 
 module mux_tree_size2_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:1]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -540,14 +540,14 @@ module mux_tree_size2_mem
 assign ccff_tail = mem_out[1];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
@@ -556,20 +556,20 @@ endmodule
 
 module frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output [0:16]mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -578,141 +578,141 @@ module frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem
 assign ccff_tail = mem_out[16];
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out[0])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[0]),
         .Q(mem_out[1])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[1]),
         .Q(mem_out[2])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[2]),
         .Q(mem_out[3])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[3]),
         .Q(mem_out[4])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[4]),
         .Q(mem_out[5])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[5]),
         .Q(mem_out[6])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[6]),
         .Q(mem_out[7])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[7]),
         .Q(mem_out[8])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[8]),
         .Q(mem_out[9])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[9]),
         .Q(mem_out[10])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[10]),
         .Q(mem_out[11])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[11]),
         .Q(mem_out[12])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[12]),
         .Q(mem_out[13])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[13]),
         .Q(mem_out[14])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[14]),
         .Q(mem_out[15])
     );
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(mem_out[15]),
         .Q(mem_out[16])
     );
 endmodule
 
-module EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem
+module io_sky130_fd_sc_hd__dfrtp_1_mem
 (
-    pReset,
+    prog_reset,
     prog_clk,
     ccff_head,
     ccff_tail,
     mem_out
 );
 
-    input pReset;
+    input prog_reset;
     input prog_clk;
     input ccff_head;
     output ccff_tail;
     output mem_out;
 
-    wire pReset;
+    wire prog_reset;
     wire prog_clk;
     wire ccff_head;
     wire ccff_tail;
@@ -721,7 +721,7 @@ module EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem
 assign ccff_tail = mem_out;
     sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_
     (
-        .RESET_B(pReset),
+        .RESET_B(prog_reset),
         .CLK(prog_clk),
         .D(ccff_head),
         .Q(mem_out)
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/user_defined_templates.v b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/user_defined_templates.v
index 6647581..2498fb3 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/user_defined_templates.v
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/SRCSynth/sub_module/user_defined_templates.v
@@ -139,7 +139,7 @@ module sky130_fd_sc_hd__dfrtp_1
 
 endmodule
 
-module EMBEDDED_IO_HD
+module io
 (
     IO_ISOL_N,
     SOC_IN,
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/XML/fabric_independent_bitstream.xml b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/XML/fabric_independent_bitstream.xml
index aeda3a2..ff0c5f5 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/XML/fabric_independent_bitstream.xml
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/XML/fabric_independent_bitstream.xml
@@ -73488,13 +73488,13 @@
   <bitstream_block name="grid_io_top_top_1__9_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_1__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73504,13 +73504,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_1__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73520,13 +73520,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_1__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73536,13 +73536,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_1__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73554,13 +73554,13 @@
   <bitstream_block name="grid_io_top_top_2__9_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_2__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73570,13 +73570,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_2__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73586,13 +73586,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_2__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73602,13 +73602,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_2__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73620,13 +73620,13 @@
   <bitstream_block name="grid_io_top_top_3__9_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_3__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73636,13 +73636,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_3__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73652,13 +73652,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_3__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73668,13 +73668,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_3__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73686,13 +73686,13 @@
   <bitstream_block name="grid_io_top_top_4__9_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_4__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73702,13 +73702,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_4__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73718,13 +73718,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_4__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73734,13 +73734,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_4__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73752,13 +73752,13 @@
   <bitstream_block name="grid_io_top_top_5__9_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_5__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="0"/>
@@ -73768,13 +73768,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_5__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73784,13 +73784,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_5__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73800,13 +73800,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_5__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73818,13 +73818,13 @@
   <bitstream_block name="grid_io_top_top_6__9_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_6__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73834,13 +73834,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_6__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73850,13 +73850,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_6__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73866,13 +73866,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_6__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73884,13 +73884,13 @@
   <bitstream_block name="grid_io_top_top_7__9_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_7__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73900,13 +73900,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_7__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73916,13 +73916,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_7__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73932,13 +73932,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_7__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73950,13 +73950,13 @@
   <bitstream_block name="grid_io_top_top_8__9_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_8__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73966,13 +73966,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_8__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73982,13 +73982,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_8__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -73998,13 +73998,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_top_top_8__9_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74016,13 +74016,13 @@
   <bitstream_block name="grid_io_right_right_9__8_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__8_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74032,13 +74032,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__8_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74048,13 +74048,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__8_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74064,13 +74064,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__8_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74082,13 +74082,13 @@
   <bitstream_block name="grid_io_right_right_9__7_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__7_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74098,13 +74098,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__7_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74114,13 +74114,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__7_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74130,13 +74130,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__7_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74148,13 +74148,13 @@
   <bitstream_block name="grid_io_right_right_9__6_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__6_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74164,13 +74164,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__6_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74180,13 +74180,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__6_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74196,13 +74196,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__6_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74214,13 +74214,13 @@
   <bitstream_block name="grid_io_right_right_9__5_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__5_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74230,13 +74230,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__5_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74246,13 +74246,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__5_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74262,13 +74262,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__5_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74280,13 +74280,13 @@
   <bitstream_block name="grid_io_right_right_9__4_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__4_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74296,13 +74296,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__4_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74312,13 +74312,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__4_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74328,13 +74328,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__4_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74346,13 +74346,13 @@
   <bitstream_block name="grid_io_right_right_9__3_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__3_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74362,13 +74362,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__3_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74378,13 +74378,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__3_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74394,13 +74394,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__3_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74412,13 +74412,13 @@
   <bitstream_block name="grid_io_right_right_9__2_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__2_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74428,13 +74428,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__2_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74444,13 +74444,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__2_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74460,13 +74460,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__2_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74478,13 +74478,13 @@
   <bitstream_block name="grid_io_right_right_9__1_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__1_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74494,13 +74494,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__1_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74510,13 +74510,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__1_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74526,13 +74526,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_right_right_9__1_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74544,13 +74544,13 @@
   <bitstream_block name="grid_io_bottom_bottom_8__0_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_8__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74560,13 +74560,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_8__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74576,13 +74576,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_8__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74592,13 +74592,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_8__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74610,13 +74610,13 @@
   <bitstream_block name="grid_io_bottom_bottom_7__0_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_7__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74626,13 +74626,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_7__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74642,13 +74642,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_7__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74658,13 +74658,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_7__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74676,13 +74676,13 @@
   <bitstream_block name="grid_io_bottom_bottom_6__0_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_6__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74692,13 +74692,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_6__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74708,13 +74708,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_6__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74724,13 +74724,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_6__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74742,13 +74742,13 @@
   <bitstream_block name="grid_io_bottom_bottom_5__0_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_5__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74758,13 +74758,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_5__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74774,13 +74774,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_5__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74790,13 +74790,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_5__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74808,13 +74808,13 @@
   <bitstream_block name="grid_io_bottom_bottom_4__0_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_4__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74824,13 +74824,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_4__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74840,13 +74840,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_4__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74856,13 +74856,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_4__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74874,13 +74874,13 @@
   <bitstream_block name="grid_io_bottom_bottom_3__0_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_3__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74890,13 +74890,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_3__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74906,13 +74906,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_3__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74922,13 +74922,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_3__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74940,13 +74940,13 @@
   <bitstream_block name="grid_io_bottom_bottom_2__0_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_2__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74956,13 +74956,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_2__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74972,13 +74972,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_2__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -74988,13 +74988,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_2__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75006,13 +75006,13 @@
   <bitstream_block name="grid_io_bottom_bottom_1__0_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_1__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75022,13 +75022,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_1__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75038,13 +75038,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_1__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75054,13 +75054,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_bottom_bottom_1__0_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75072,13 +75072,13 @@
   <bitstream_block name="grid_io_left_left_0__1_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__1_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75088,13 +75088,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__1_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75104,13 +75104,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__1_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75120,13 +75120,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__1_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75138,13 +75138,13 @@
   <bitstream_block name="grid_io_left_left_0__2_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__2_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75154,13 +75154,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__2_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75170,13 +75170,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__2_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75186,13 +75186,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__2_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75204,13 +75204,13 @@
   <bitstream_block name="grid_io_left_left_0__3_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__3_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75220,13 +75220,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__3_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75236,13 +75236,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__3_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75252,13 +75252,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__3_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75270,13 +75270,13 @@
   <bitstream_block name="grid_io_left_left_0__4_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__4_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75286,13 +75286,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__4_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75302,13 +75302,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__4_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75318,13 +75318,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__4_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75336,13 +75336,13 @@
   <bitstream_block name="grid_io_left_left_0__5_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__5_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75352,13 +75352,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__5_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75368,13 +75368,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__5_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75384,13 +75384,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__5_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75402,13 +75402,13 @@
   <bitstream_block name="grid_io_left_left_0__6_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__6_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75418,13 +75418,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__6_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75434,13 +75434,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__6_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75450,13 +75450,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__6_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75468,13 +75468,13 @@
   <bitstream_block name="grid_io_left_left_0__7_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__7_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75484,13 +75484,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__7_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75500,13 +75500,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__7_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75516,13 +75516,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__7_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75534,13 +75534,13 @@
   <bitstream_block name="grid_io_left_left_0__8_" hierarchy_level="1">
     <bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__8_"/>
             <instance level="2" name="logical_tile_io_mode_io__0"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75550,13 +75550,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__8_"/>
             <instance level="2" name="logical_tile_io_mode_io__1"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75566,13 +75566,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__8_"/>
             <instance level="2" name="logical_tile_io_mode_io__2"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
@@ -75582,13 +75582,13 @@
     </bitstream_block>
     <bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
       <bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-        <bitstream_block name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
+        <bitstream_block name="io_sky130_fd_sc_hd__dfrtp_1_mem" hierarchy_level="4">
           <hierarchy>
             <instance level="0" name="fpga_top"/>
             <instance level="1" name="grid_io_left_left_0__8_"/>
             <instance level="2" name="logical_tile_io_mode_io__3"/>
             <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-            <instance level="4" name="EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem"/>
+            <instance level="4" name="io_sky130_fd_sc_hd__dfrtp_1_mem"/>
           </hierarchy>
           <bitstream>
             <bit memory_port="mem_out[0]" value="1"/>
diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/openfpgashell.log b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/openfpgashell.log
index 68bb7a9..1d30316 100644
--- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/openfpgashell.log
+++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_verilog/openfpgashell.log
@@ -268,11 +268,11 @@ Logic Element (fle) detailed count:
   LEs used for logic only             : 1
   LEs used for registers only         : 0
 
-Incr Slack updates 1 in 2.246e-06 sec
-Full Max Req/Worst Slack updates 1 in 1.637e-06 sec
+Incr Slack updates 1 in 2.584e-06 sec
+Full Max Req/Worst Slack updates 1 in 1.735e-06 sec
 Incr Max Req/Worst Slack updates 0 in 0 sec
 Incr Criticality updates 0 in 0 sec
-Full Criticality updates 1 in 1.825e-06 sec
+Full Criticality updates 1 in 1.882e-06 sec
 Warning 27: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
 Warning 28: Ambiguous block type specification at grid location (0,9). Existing block type 'io_top' at (0,9) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
 Warning 29: Ambiguous block type specification at grid location (9,0). Existing block type 'io_bottom' at (9,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
@@ -507,11 +507,11 @@ Iter   Time    pres  BBs    Heap  Re-Rtd  Re-Rtd Overused RR Nodes      Wireleng
       (sec)     fac Updt    push    Nets   Conns                                       (ns)       (ns)       (ns)       (ns)       (ns)     Iter
 ---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- --------
    1    0.0     0.0    0     226       3       3       0 ( 0.000%)      27 ( 0.3%)   13.980     -13.98    -13.980      0.000      0.000      N/A
-Incr Slack updates 4 in 1.4576e-05 sec
-Full Max Req/Worst Slack updates 1 in 1.984e-06 sec
-Incr Max Req/Worst Slack updates 3 in 8.537e-06 sec
-Incr Criticality updates 3 in 7.854e-06 sec
-Full Criticality updates 1 in 1.766e-06 sec
+Incr Slack updates 4 in 1.2947e-05 sec
+Full Max Req/Worst Slack updates 1 in 3.948e-06 sec
+Incr Max Req/Worst Slack updates 3 in 6.005e-06 sec
+Incr Criticality updates 3 in 6.601e-06 sec
+Full Criticality updates 1 in 2.382e-06 sec
 Restoring best routing
 Critical path: 13.98 ns
 Successfully routed after 1 routing iterations.
@@ -658,11 +658,11 @@ Final setup slack histogram:
 Final geomean non-virtual intra-domain period: nan ns (nan MHz)
 Final fanout-weighted geomean non-virtual intra-domain period: nan ns (nan MHz)
 
-Incr Slack updates 1 in 1.9716e-05 sec
-Full Max Req/Worst Slack updates 1 in 3.349e-06 sec
+Incr Slack updates 1 in 6.046e-06 sec
+Full Max Req/Worst Slack updates 1 in 4.007e-06 sec
 Incr Max Req/Worst Slack updates 0 in 0 sec
 Incr Criticality updates 0 in 0 sec
-Full Criticality updates 1 in 3.35e-06 sec
+Full Criticality updates 1 in 3.533e-06 sec
 --line removed--
 VPR suceeded
 --line removed--
@@ -992,11 +992,11 @@ Building annotation for post-routing and clustering synchornization results...Do
 Building annotation for mapped blocks on grid locations...Done
 User specified the operating clock frequency to use VPR results
 Use VPR critical path delay 1.6776e-17 [ns] with a 20 [%] slack in OpenFPGA.
-Incr Slack updates 1 in 6.449e-06 sec
-Full Max Req/Worst Slack updates 1 in 3.564e-06 sec
+Incr Slack updates 1 in 6.177e-06 sec
+Full Max Req/Worst Slack updates 1 in 5.086e-06 sec
 Incr Max Req/Worst Slack updates 0 in 0 sec
 Incr Criticality updates 0 in 0 sec
-Full Criticality updates 1 in 4.624e-06 sec
+Full Criticality updates 1 in 5.057e-06 sec
 Will apply operating clock frequency 59.609 [MHz] to simulations
 User specified the number of operating clock cycles to be inferred from signal activities
 Average net density: 0.42
@@ -1314,9 +1314,9 @@ Finish execution with 0 errors
 --line removed--
 
 Thank you for using OpenFPGA!
-Incr Slack updates 2 in 1.4547e-05 sec
-Full Max Req/Worst Slack updates 1 in 3.044e-06 sec
-Incr Max Req/Worst Slack updates 1 in 5.177e-06 sec
+Incr Slack updates 2 in 2.3068e-05 sec
+Full Max Req/Worst Slack updates 1 in 4.469e-06 sec
+Incr Max Req/Worst Slack updates 1 in 5.627e-06 sec
 Incr Criticality updates 0 in 0 sec
-Full Criticality updates 2 in 8.542e-06 sec
+Full Criticality updates 2 in 1.1276e-05 sec
 0
\ No newline at end of file
diff --git a/SOFA_A/FPGA88_SOFA_A/release/post_synth/top_instances_ports.txt b/SOFA_A/FPGA88_SOFA_A/release/post_synth/top_instances_ports.txt
index a4a2127..32ddf05 100644
--- a/SOFA_A/FPGA88_SOFA_A/release/post_synth/top_instances_ports.txt
+++ b/SOFA_A/FPGA88_SOFA_A/release/post_synth/top_instances_ports.txt
@@ -25,8 +25,8 @@
         "0001_Direction.IN,left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_",
         "0001_Direction.IN,left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_",
         "0001_Direction.IN,left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_",
-        "0001_Direction.IN,pReset",
         "0001_Direction.IN,prog_clk",
+        "0001_Direction.IN,prog_reset",
         "0001_Direction.OUT,ccff_tail",
         "0030_Direction.IN,chanx_left_in",
         "0030_Direction.IN,chany_bottom_in",
@@ -55,8 +55,8 @@
         "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_",
         "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_",
         "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_",
-        "0001_Direction.IN,pReset",
         "0001_Direction.IN,prog_clk",
+        "0001_Direction.IN,prog_reset",
         "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_",
         "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_",
         "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_",
@@ -83,8 +83,8 @@
         "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_",
         "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_",
         "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_",
-        "0001_Direction.IN,pReset",
         "0001_Direction.IN,prog_clk",
+        "0001_Direction.IN,prog_reset",
         "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_10_",
         "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_11_",
         "0001_Direction.IN,top_left_grid_right_width_0_height_0_subtile_0__pin_O_12_",
@@ -125,8 +125,8 @@
         "0001_Direction.IN,left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_",
         "0001_Direction.IN,left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_",
         "0001_Direction.IN,left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_",
-        "0001_Direction.IN,pReset",
         "0001_Direction.IN,prog_clk",
+        "0001_Direction.IN,prog_reset",
         "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_",
         "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_",
         "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_",
@@ -165,8 +165,8 @@
         "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_",
         "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_",
         "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_",
-        "0001_Direction.IN,pReset",
         "0001_Direction.IN,prog_clk",
+        "0001_Direction.IN,prog_reset",
         "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_",
         "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_",
         "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_",
@@ -199,8 +199,8 @@
         "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_",
         "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_",
         "0001_Direction.IN,left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_",
-        "0001_Direction.IN,pReset",
         "0001_Direction.IN,prog_clk",
+        "0001_Direction.IN,prog_reset",
         "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_",
         "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_",
         "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_",
@@ -227,8 +227,8 @@
         "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_",
         "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_",
         "0001_Direction.IN,ccff_head",
-        "0001_Direction.IN,pReset",
         "0001_Direction.IN,prog_clk",
+        "0001_Direction.IN,prog_reset",
         "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_",
         "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_",
         "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_",
@@ -253,8 +253,8 @@
         "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_",
         "0001_Direction.IN,bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_",
         "0001_Direction.IN,ccff_head",
-        "0001_Direction.IN,pReset",
         "0001_Direction.IN,prog_clk",
+        "0001_Direction.IN,prog_reset",
         "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_0_",
         "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_1_",
         "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_",
@@ -277,8 +277,8 @@
     ],
     "sb_0__0_": [
         "0001_Direction.IN,ccff_head",
-        "0001_Direction.IN,pReset",
         "0001_Direction.IN,prog_clk",
+        "0001_Direction.IN,prog_reset",
         "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_",
         "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_",
         "0001_Direction.IN,right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_",
@@ -294,46 +294,46 @@
         "0030_Direction.OUT,chany_top_out"
     ],
     "grid_io_top_top": [
-        "0001_Direction.IN,IO_ISOL_N",
         "0001_Direction.IN,bottom_width_0_height_0_subtile_0__pin_outpad_0_",
         "0001_Direction.IN,bottom_width_0_height_0_subtile_1__pin_outpad_0_",
         "0001_Direction.IN,bottom_width_0_height_0_subtile_2__pin_outpad_0_",
         "0001_Direction.IN,bottom_width_0_height_0_subtile_3__pin_outpad_0_",
         "0001_Direction.IN,ccff_head",
-        "0001_Direction.IN,pReset",
+        "0001_Direction.IN,isol_n",
         "0001_Direction.IN,prog_clk",
+        "0001_Direction.IN,prog_reset",
         "0001_Direction.OUT,bottom_width_0_height_0_subtile_0__pin_inpad_0_",
         "0001_Direction.OUT,bottom_width_0_height_0_subtile_1__pin_inpad_0_",
         "0001_Direction.OUT,bottom_width_0_height_0_subtile_2__pin_inpad_0_",
         "0001_Direction.OUT,bottom_width_0_height_0_subtile_3__pin_inpad_0_",
         "0001_Direction.OUT,ccff_tail",
-        "0004_Direction.IN,gfpga_pad_EMBEDDED_IO_HD_SOC_IN",
-        "0004_Direction.OUT,gfpga_pad_EMBEDDED_IO_HD_SOC_DIR",
-        "0004_Direction.OUT,gfpga_pad_EMBEDDED_IO_HD_SOC_OUT"
+        "0004_Direction.IN,gfpga_pad_io_soc_in",
+        "0004_Direction.OUT,gfpga_pad_io_soc_dir",
+        "0004_Direction.OUT,gfpga_pad_io_soc_out"
     ],
     "grid_io_right_right": [
-        "0001_Direction.IN,IO_ISOL_N",
         "0001_Direction.IN,ccff_head",
+        "0001_Direction.IN,isol_n",
         "0001_Direction.IN,left_width_0_height_0_subtile_0__pin_outpad_0_",
         "0001_Direction.IN,left_width_0_height_0_subtile_1__pin_outpad_0_",
         "0001_Direction.IN,left_width_0_height_0_subtile_2__pin_outpad_0_",
         "0001_Direction.IN,left_width_0_height_0_subtile_3__pin_outpad_0_",
-        "0001_Direction.IN,pReset",
         "0001_Direction.IN,prog_clk",
+        "0001_Direction.IN,prog_reset",
         "0001_Direction.OUT,ccff_tail",
         "0001_Direction.OUT,left_width_0_height_0_subtile_0__pin_inpad_0_",
         "0001_Direction.OUT,left_width_0_height_0_subtile_1__pin_inpad_0_",
         "0001_Direction.OUT,left_width_0_height_0_subtile_2__pin_inpad_0_",
         "0001_Direction.OUT,left_width_0_height_0_subtile_3__pin_inpad_0_",
-        "0004_Direction.IN,gfpga_pad_EMBEDDED_IO_HD_SOC_IN",
-        "0004_Direction.OUT,gfpga_pad_EMBEDDED_IO_HD_SOC_DIR",
-        "0004_Direction.OUT,gfpga_pad_EMBEDDED_IO_HD_SOC_OUT"
+        "0004_Direction.IN,gfpga_pad_io_soc_in",
+        "0004_Direction.OUT,gfpga_pad_io_soc_dir",
+        "0004_Direction.OUT,gfpga_pad_io_soc_out"
     ],
     "grid_io_left_left": [
-        "0001_Direction.IN,IO_ISOL_N",
         "0001_Direction.IN,ccff_head",
-        "0001_Direction.IN,pReset",
+        "0001_Direction.IN,isol_n",
         "0001_Direction.IN,prog_clk",
+        "0001_Direction.IN,prog_reset",
         "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_outpad_0_",
         "0001_Direction.IN,right_width_0_height_0_subtile_1__pin_outpad_0_",
         "0001_Direction.IN,right_width_0_height_0_subtile_2__pin_outpad_0_",
@@ -343,15 +343,15 @@
         "0001_Direction.OUT,right_width_0_height_0_subtile_1__pin_inpad_0_",
         "0001_Direction.OUT,right_width_0_height_0_subtile_2__pin_inpad_0_",
         "0001_Direction.OUT,right_width_0_height_0_subtile_3__pin_inpad_0_",
-        "0004_Direction.IN,gfpga_pad_EMBEDDED_IO_HD_SOC_IN",
-        "0004_Direction.OUT,gfpga_pad_EMBEDDED_IO_HD_SOC_DIR",
-        "0004_Direction.OUT,gfpga_pad_EMBEDDED_IO_HD_SOC_OUT"
+        "0004_Direction.IN,gfpga_pad_io_soc_in",
+        "0004_Direction.OUT,gfpga_pad_io_soc_dir",
+        "0004_Direction.OUT,gfpga_pad_io_soc_out"
     ],
     "grid_io_bottom_bottom": [
-        "0001_Direction.IN,IO_ISOL_N",
         "0001_Direction.IN,ccff_head",
-        "0001_Direction.IN,pReset",
+        "0001_Direction.IN,isol_n",
         "0001_Direction.IN,prog_clk",
+        "0001_Direction.IN,prog_reset",
         "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_outpad_0_",
         "0001_Direction.IN,top_width_0_height_0_subtile_1__pin_outpad_0_",
         "0001_Direction.IN,top_width_0_height_0_subtile_2__pin_outpad_0_",
@@ -361,17 +361,16 @@
         "0001_Direction.OUT,top_width_0_height_0_subtile_1__pin_inpad_0_",
         "0001_Direction.OUT,top_width_0_height_0_subtile_2__pin_inpad_0_",
         "0001_Direction.OUT,top_width_0_height_0_subtile_3__pin_inpad_0_",
-        "0004_Direction.IN,gfpga_pad_EMBEDDED_IO_HD_SOC_IN",
-        "0004_Direction.OUT,gfpga_pad_EMBEDDED_IO_HD_SOC_DIR",
-        "0004_Direction.OUT,gfpga_pad_EMBEDDED_IO_HD_SOC_OUT"
+        "0004_Direction.IN,gfpga_pad_io_soc_in",
+        "0004_Direction.OUT,gfpga_pad_io_soc_dir",
+        "0004_Direction.OUT,gfpga_pad_io_soc_out"
     ],
     "grid_clb": [
-        "0001_Direction.IN,Test_en",
         "0001_Direction.IN,ccff_head",
         "0001_Direction.IN,left_width_0_height_0_subtile_0__pin_clk_0_",
         "0001_Direction.IN,left_width_0_height_0_subtile_0__pin_reset_0_",
-        "0001_Direction.IN,pReset",
         "0001_Direction.IN,prog_clk",
+        "0001_Direction.IN,prog_reset",
         "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I4_0_",
         "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I4_1_",
         "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I4i_0_",
@@ -388,6 +387,7 @@
         "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I7_1_",
         "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I7i_0_",
         "0001_Direction.IN,right_width_0_height_0_subtile_0__pin_I7i_1_",
+        "0001_Direction.IN,scan_enable",
         "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I0_0_",
         "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I0_1_",
         "0001_Direction.IN,top_width_0_height_0_subtile_0__pin_I0i_0_",
@@ -434,8 +434,8 @@
     ],
     "cby_8__1_": [
         "0001_Direction.IN,ccff_head",
-        "0001_Direction.IN,pReset",
         "0001_Direction.IN,prog_clk",
+        "0001_Direction.IN,prog_reset",
         "0001_Direction.OUT,ccff_tail",
         "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I4_0_",
         "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I4_1_",
@@ -464,8 +464,8 @@
     ],
     "cby_1__1_": [
         "0001_Direction.IN,ccff_head",
-        "0001_Direction.IN,pReset",
         "0001_Direction.IN,prog_clk",
+        "0001_Direction.IN,prog_reset",
         "0001_Direction.OUT,ccff_tail",
         "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I4_0_",
         "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_I4_1_",
@@ -490,8 +490,8 @@
     ],
     "cby_0__1_": [
         "0001_Direction.IN,ccff_head",
-        "0001_Direction.IN,pReset",
         "0001_Direction.IN,prog_clk",
+        "0001_Direction.IN,prog_reset",
         "0001_Direction.OUT,ccff_tail",
         "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_",
         "0001_Direction.OUT,left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_",
@@ -504,8 +504,8 @@
     ],
     "cbx_1__8_": [
         "0001_Direction.IN,ccff_head",
-        "0001_Direction.IN,pReset",
         "0001_Direction.IN,prog_clk",
+        "0001_Direction.IN,prog_reset",
         "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_",
         "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_",
         "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_",
@@ -534,8 +534,8 @@
     ],
     "cbx_1__1_": [
         "0001_Direction.IN,ccff_head",
-        "0001_Direction.IN,pReset",
         "0001_Direction.IN,prog_clk",
+        "0001_Direction.IN,prog_reset",
         "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_",
         "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_",
         "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_I0i_0_",
@@ -560,8 +560,8 @@
     ],
     "cbx_1__0_": [
         "0001_Direction.IN,ccff_head",
-        "0001_Direction.IN,pReset",
         "0001_Direction.IN,prog_clk",
+        "0001_Direction.IN,prog_reset",
         "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_",
         "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_",
         "0001_Direction.OUT,bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_",
diff --git a/SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/reset_ports.txt b/SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/reset_ports.txt
new file mode 100644
index 0000000..d57c0c7
--- /dev/null
+++ b/SOFA_A/FPGA88_SOFA_A/release/rpts/pre_pnr/reset_ports.txt
@@ -0,0 +1,7 @@
+= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+Module                    |       In        |       Out      
+Module                    |   L   R   T   B |   L   R   T   B
+= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+cbx_1__8_                 |   -   -   -   7 |   -   -   -   -
+cby_1__1_                 |   -   7  28  14 |   6   -  21  28
+cby_8__1_                 |   -   1   4   3 |   1   -   3   4
\ No newline at end of file
diff --git a/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_CCFF_Chain.svg b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_CCFF_Chain.svg
index b49648b..60fb642 100644
--- a/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_CCFF_Chain.svg
+++ b/SOFA_A/FPGA88_SOFA_A/release/svg/FPGA88_SOFA_A_CCFF_Chain.svg
@@ -282,14 +282,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;}
     <g id="main" transform="scale(1,-1)">
         <rect class="boundary" height="138" id="core_boundary" width="138" x="0" y="0"/>
         <g id="main_shapes">
-            <use id="io_left_0__1_" x="0.0" xlink:href="#io_left" y="14.0"/>
-            <use id="io_left_0__2_" x="0.0" xlink:href="#io_left" y="28.0"/>
-            <use id="io_left_0__3_" x="0.0" xlink:href="#io_left" y="42.0"/>
-            <use id="io_left_0__4_" x="0.0" xlink:href="#io_left" y="56.0"/>
-            <use id="io_left_0__5_" x="0.0" xlink:href="#io_left" y="70.0"/>
-            <use id="io_left_0__6_" x="0.0" xlink:href="#io_left" y="84.0"/>
-            <use id="io_left_0__7_" x="0.0" xlink:href="#io_left" y="98.0"/>
-            <use id="io_left_0__8_" x="0.0" xlink:href="#io_left" y="112.0"/>
             <use id="sb_0__0_" x="10" xlink:href="#sb01" y="10"/>
             <use id="cby_0__1_" x="10" xlink:href="#cby" y="14.0"/>
             <use id="sb_0__1_" x="10" xlink:href="#sb02" y="24"/>
@@ -307,7 +299,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;}
             <use id="sb_0__7_" x="10" xlink:href="#sb02" y="108"/>
             <use id="cby_0__8_" x="10" xlink:href="#cby" y="112.0"/>
             <use id="sb_0__8_" x="10" xlink:href="#sb03" y="122"/>
-            <use id="io_bottom_1__0_" x="14.0" xlink:href="#io_bottom" y="0.0"/>
             <use id="cbx_1__0_" x="14.0" xlink:href="#cbx" y="10"/>
             <use id="clb_1__1_" x="14.0" xlink:href="#clb" y="14.0"/>
             <use id="cbx_1__1_" x="14.0" xlink:href="#cbx" y="24"/>
@@ -325,7 +316,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;}
             <use id="cbx_1__7_" x="14.0" xlink:href="#cbx" y="108"/>
             <use id="clb_1__8_" x="14.0" xlink:href="#clb" y="112.0"/>
             <use id="cbx_1__8_" x="14.0" xlink:href="#cbx" y="122"/>
-            <use id="io_top_1__9_" x="14.0" xlink:href="#io_top" y="126.0"/>
             <use id="sb_1__0_" x="24" xlink:href="#sb08" y="10"/>
             <use id="cby_1__1_" x="24" xlink:href="#cby" y="14.0"/>
             <use id="sb_1__1_" x="24" xlink:href="#sb00" y="24"/>
@@ -343,7 +333,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;}
             <use id="sb_1__7_" x="24" xlink:href="#sb00" y="108"/>
             <use id="cby_1__8_" x="24" xlink:href="#cby" y="112.0"/>
             <use id="sb_1__8_" x="24" xlink:href="#sb04" y="122"/>
-            <use id="io_bottom_2__0_" x="28.0" xlink:href="#io_bottom" y="0.0"/>
             <use id="cbx_2__0_" x="28.0" xlink:href="#cbx" y="10"/>
             <use id="clb_2__1_" x="28.0" xlink:href="#clb" y="14.0"/>
             <use id="cbx_2__1_" x="28.0" xlink:href="#cbx" y="24"/>
@@ -361,7 +350,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;}
             <use id="cbx_2__7_" x="28.0" xlink:href="#cbx" y="108"/>
             <use id="clb_2__8_" x="28.0" xlink:href="#clb" y="112.0"/>
             <use id="cbx_2__8_" x="28.0" xlink:href="#cbx" y="122"/>
-            <use id="io_top_2__9_" x="28.0" xlink:href="#io_top" y="126.0"/>
             <use id="sb_2__0_" x="38" xlink:href="#sb08" y="10"/>
             <use id="cby_2__1_" x="38" xlink:href="#cby" y="14.0"/>
             <use id="sb_2__1_" x="38" xlink:href="#sb00" y="24"/>
@@ -379,7 +367,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;}
             <use id="sb_2__7_" x="38" xlink:href="#sb00" y="108"/>
             <use id="cby_2__8_" x="38" xlink:href="#cby" y="112.0"/>
             <use id="sb_2__8_" x="38" xlink:href="#sb04" y="122"/>
-            <use id="io_bottom_3__0_" x="42.0" xlink:href="#io_bottom" y="0.0"/>
             <use id="cbx_3__0_" x="42.0" xlink:href="#cbx" y="10"/>
             <use id="clb_3__1_" x="42.0" xlink:href="#clb" y="14.0"/>
             <use id="cbx_3__1_" x="42.0" xlink:href="#cbx" y="24"/>
@@ -397,7 +384,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;}
             <use id="cbx_3__7_" x="42.0" xlink:href="#cbx" y="108"/>
             <use id="clb_3__8_" x="42.0" xlink:href="#clb" y="112.0"/>
             <use id="cbx_3__8_" x="42.0" xlink:href="#cbx" y="122"/>
-            <use id="io_top_3__9_" x="42.0" xlink:href="#io_top" y="126.0"/>
             <use id="sb_3__0_" x="52" xlink:href="#sb08" y="10"/>
             <use id="cby_3__1_" x="52" xlink:href="#cby" y="14.0"/>
             <use id="sb_3__1_" x="52" xlink:href="#sb00" y="24"/>
@@ -415,7 +401,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;}
             <use id="sb_3__7_" x="52" xlink:href="#sb00" y="108"/>
             <use id="cby_3__8_" x="52" xlink:href="#cby" y="112.0"/>
             <use id="sb_3__8_" x="52" xlink:href="#sb04" y="122"/>
-            <use id="io_bottom_4__0_" x="56.0" xlink:href="#io_bottom" y="0.0"/>
             <use id="cbx_4__0_" x="56.0" xlink:href="#cbx" y="10"/>
             <use id="clb_4__1_" x="56.0" xlink:href="#clb" y="14.0"/>
             <use id="cbx_4__1_" x="56.0" xlink:href="#cbx" y="24"/>
@@ -433,7 +418,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;}
             <use id="cbx_4__7_" x="56.0" xlink:href="#cbx" y="108"/>
             <use id="clb_4__8_" x="56.0" xlink:href="#clb" y="112.0"/>
             <use id="cbx_4__8_" x="56.0" xlink:href="#cbx" y="122"/>
-            <use id="io_top_4__9_" x="56.0" xlink:href="#io_top" y="126.0"/>
             <use id="sb_4__0_" x="66" xlink:href="#sb08" y="10"/>
             <use id="cby_4__1_" x="66" xlink:href="#cby" y="14.0"/>
             <use id="sb_4__1_" x="66" xlink:href="#sb00" y="24"/>
@@ -451,7 +435,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;}
             <use id="sb_4__7_" x="66" xlink:href="#sb00" y="108"/>
             <use id="cby_4__8_" x="66" xlink:href="#cby" y="112.0"/>
             <use id="sb_4__8_" x="66" xlink:href="#sb04" y="122"/>
-            <use id="io_bottom_5__0_" x="70.0" xlink:href="#io_bottom" y="0.0"/>
             <use id="cbx_5__0_" x="70.0" xlink:href="#cbx" y="10"/>
             <use id="clb_5__1_" x="70.0" xlink:href="#clb" y="14.0"/>
             <use id="cbx_5__1_" x="70.0" xlink:href="#cbx" y="24"/>
@@ -469,7 +452,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;}
             <use id="cbx_5__7_" x="70.0" xlink:href="#cbx" y="108"/>
             <use id="clb_5__8_" x="70.0" xlink:href="#clb" y="112.0"/>
             <use id="cbx_5__8_" x="70.0" xlink:href="#cbx" y="122"/>
-            <use id="io_top_5__9_" x="70.0" xlink:href="#io_top" y="126.0"/>
             <use id="sb_5__0_" x="80" xlink:href="#sb08" y="10"/>
             <use id="cby_5__1_" x="80" xlink:href="#cby" y="14.0"/>
             <use id="sb_5__1_" x="80" xlink:href="#sb00" y="24"/>
@@ -487,7 +469,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;}
             <use id="sb_5__7_" x="80" xlink:href="#sb00" y="108"/>
             <use id="cby_5__8_" x="80" xlink:href="#cby" y="112.0"/>
             <use id="sb_5__8_" x="80" xlink:href="#sb04" y="122"/>
-            <use id="io_bottom_6__0_" x="84.0" xlink:href="#io_bottom" y="0.0"/>
             <use id="cbx_6__0_" x="84.0" xlink:href="#cbx" y="10"/>
             <use id="clb_6__1_" x="84.0" xlink:href="#clb" y="14.0"/>
             <use id="cbx_6__1_" x="84.0" xlink:href="#cbx" y="24"/>
@@ -505,7 +486,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;}
             <use id="cbx_6__7_" x="84.0" xlink:href="#cbx" y="108"/>
             <use id="clb_6__8_" x="84.0" xlink:href="#clb" y="112.0"/>
             <use id="cbx_6__8_" x="84.0" xlink:href="#cbx" y="122"/>
-            <use id="io_top_6__9_" x="84.0" xlink:href="#io_top" y="126.0"/>
             <use id="sb_6__0_" x="94" xlink:href="#sb08" y="10"/>
             <use id="cby_6__1_" x="94" xlink:href="#cby" y="14.0"/>
             <use id="sb_6__1_" x="94" xlink:href="#sb00" y="24"/>
@@ -523,7 +503,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;}
             <use id="sb_6__7_" x="94" xlink:href="#sb00" y="108"/>
             <use id="cby_6__8_" x="94" xlink:href="#cby" y="112.0"/>
             <use id="sb_6__8_" x="94" xlink:href="#sb04" y="122"/>
-            <use id="io_bottom_7__0_" x="98.0" xlink:href="#io_bottom" y="0.0"/>
             <use id="cbx_7__0_" x="98.0" xlink:href="#cbx" y="10"/>
             <use id="clb_7__1_" x="98.0" xlink:href="#clb" y="14.0"/>
             <use id="cbx_7__1_" x="98.0" xlink:href="#cbx" y="24"/>
@@ -541,7 +520,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;}
             <use id="cbx_7__7_" x="98.0" xlink:href="#cbx" y="108"/>
             <use id="clb_7__8_" x="98.0" xlink:href="#clb" y="112.0"/>
             <use id="cbx_7__8_" x="98.0" xlink:href="#cbx" y="122"/>
-            <use id="io_top_7__9_" x="98.0" xlink:href="#io_top" y="126.0"/>
             <use id="sb_7__0_" x="108" xlink:href="#sb08" y="10"/>
             <use id="cby_7__1_" x="108" xlink:href="#cby" y="14.0"/>
             <use id="sb_7__1_" x="108" xlink:href="#sb00" y="24"/>
@@ -559,7 +537,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;}
             <use id="sb_7__7_" x="108" xlink:href="#sb00" y="108"/>
             <use id="cby_7__8_" x="108" xlink:href="#cby" y="112.0"/>
             <use id="sb_7__8_" x="108" xlink:href="#sb04" y="122"/>
-            <use id="io_bottom_8__0_" x="112.0" xlink:href="#io_bottom" y="0.0"/>
             <use id="cbx_8__0_" x="112.0" xlink:href="#cbx" y="10"/>
             <use id="clb_8__1_" x="112.0" xlink:href="#clb" y="14.0"/>
             <use id="cbx_8__1_" x="112.0" xlink:href="#cbx" y="24"/>
@@ -577,7 +554,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;}
             <use id="cbx_8__7_" x="112.0" xlink:href="#cbx" y="108"/>
             <use id="clb_8__8_" x="112.0" xlink:href="#clb" y="112.0"/>
             <use id="cbx_8__8_" x="112.0" xlink:href="#cbx" y="122"/>
-            <use id="io_top_8__9_" x="112.0" xlink:href="#io_top" y="126.0"/>
             <use id="sb_8__0_" x="122" xlink:href="#sb07" y="10"/>
             <use id="cby_8__1_" x="122" xlink:href="#cby" y="14.0"/>
             <use id="sb_8__1_" x="122" xlink:href="#sb06" y="24"/>
@@ -595,14 +571,6 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;}
             <use id="sb_8__7_" x="122" xlink:href="#sb06" y="108"/>
             <use id="cby_8__8_" x="122" xlink:href="#cby" y="112.0"/>
             <use id="sb_8__8_" x="122" xlink:href="#sb05" y="122"/>
-            <use id="io_right_9__1_" x="126.0" xlink:href="#io_right" y="14.0"/>
-            <use id="io_right_9__2_" x="126.0" xlink:href="#io_right" y="28.0"/>
-            <use id="io_right_9__3_" x="126.0" xlink:href="#io_right" y="42.0"/>
-            <use id="io_right_9__4_" x="126.0" xlink:href="#io_right" y="56.0"/>
-            <use id="io_right_9__5_" x="126.0" xlink:href="#io_right" y="70.0"/>
-            <use id="io_right_9__6_" x="126.0" xlink:href="#io_right" y="84.0"/>
-            <use id="io_right_9__7_" x="126.0" xlink:href="#io_right" y="98.0"/>
-            <use id="io_right_9__8_" x="126.0" xlink:href="#io_right" y="112.0"/>
             <use x="10" xlink:href="#sides_merged_at_0_2" y="28.0"/>
             <use x="112.0" xlink:href="#sides_merged_at_8_2" y="28.0"/>
             <use x="10" xlink:href="#sides_merged_at_0_3" y="42.0"/>
@@ -667,17 +635,9 @@ symbol[id*='merged'] * { stroke:white; stroke-width:1px;}
             <use x="112.0" xlink:href="#corner_merged_rtop" y="112.0"/>
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