mirror of https://github.com/lnis-uofu/SOFA.git
Added scan chain ports
This commit is contained in:
Ganesh Gore
parent
f10d475363
commit
9db5e34f3b
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@ -195,7 +195,7 @@ def main():
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# Signal pins
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fpga.fix_grid_pin_names(
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regex=r".*__pin_(reset|prog_reset)_0_", module="grid_*")
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regex=r".*__pin_(reset|prog_reset|sc_in|sc_out)_0_", module="grid_*")
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fpga.fix_grid_pin_names(
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regex=r".*__pin_(reset|prog_reset)_0_", module="cbx*")
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# For clock signals
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@ -208,6 +208,8 @@ def main():
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regex=r".*__pin_(clk.*)_", module="cb*", name_map=lambda x: x.replace("_", "")
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)
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connect_scan_chain(fpga)
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filename = SVG_DIR + f"{PROJ_NAME}_raw_floorplan.svg"
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save_tiling_floorplan(fpga, filename, STYLE_SHEET=STYLE_SHEET)
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@ -267,6 +269,34 @@ def main():
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)
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def connect_scan_chain(fpga: OpenFPGA):
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"""
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Adds scan chain port
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"""
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# .........creating ports and cables on FPGA TOP............#
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sc_head_port = fpga.top_module.create_port("sc_head", direction=sdn.IN, pins=1)
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sc_head_cable = fpga.top_module.create_cable("sc_head", wires=1)
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sc_tail_port = fpga.top_module.create_port("sc_tail", direction=sdn.OUT, pins=1)
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sc_tail_cable = fpga.top_module.create_cable("sc_tail", wires=1)
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sc_head_cable.wires[0].connect_pin(sc_head_port.pins[0])
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sc_tail_cable.wires[0].connect_pin(sc_tail_port.pins[0])
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grid_clb = next(fpga.top_module.get_definitions("grid_clb"))
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grid_clb_sc_in_pin = next(grid_clb.get_ports("sc_in")).pins[0]
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grid_clb_sc_out_pin = next(grid_clb.get_ports("sc_out")).pins[0]
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grid_clb_1__8_sc_in = next(fpga.top_module.get_instances(
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"grid_clb_1__8_")).pins[grid_clb_sc_in_pin]
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grid_clb_8__8_sc_out = next(fpga.top_module.get_instances(
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"grid_clb_8__8_")).pins[grid_clb_sc_out_pin]
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grid_clb_1__8_sc_in.wire.disconnect_pin(grid_clb_1__8_sc_in)
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grid_clb_8__8_sc_out.wire.disconnect_pin(grid_clb_8__8_sc_out)
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sc_head_cable.wires[0].connect_pin(grid_clb_1__8_sc_in)
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sc_tail_cable.wires[0].connect_pin(grid_clb_8__8_sc_out)
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def create_global_feedthrough(
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fpga: OpenFPGA, signal, instance_map, down_port=None, top_cable=None
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):
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@ -0,0 +1,263 @@
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<!--
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- FPGA Fabric I/O Information
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- Generated by OpenFPGA
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-->
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<io_coordinates>
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<io pad="gfpga_pad_io_soc_in[96]" x="0" y="1" z="0"/>
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<io pad="gfpga_pad_io_soc_out[96]" x="0" y="1" z="0"/>
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<io pad="gfpga_pad_io_soc_in[97]" x="0" y="1" z="1"/>
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<io pad="gfpga_pad_io_soc_out[97]" x="0" y="1" z="1"/>
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<io pad="gfpga_pad_io_soc_in[98]" x="0" y="1" z="2"/>
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<io pad="gfpga_pad_io_soc_out[98]" x="0" y="1" z="2"/>
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<io pad="gfpga_pad_io_soc_in[99]" x="0" y="1" z="3"/>
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<io pad="gfpga_pad_io_soc_out[99]" x="0" y="1" z="3"/>
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<io pad="gfpga_pad_io_soc_in[100]" x="0" y="2" z="0"/>
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<io pad="gfpga_pad_io_soc_out[100]" x="0" y="2" z="0"/>
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<io pad="gfpga_pad_io_soc_in[101]" x="0" y="2" z="1"/>
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<io pad="gfpga_pad_io_soc_out[101]" x="0" y="2" z="1"/>
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<io pad="gfpga_pad_io_soc_in[102]" x="0" y="2" z="2"/>
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<io pad="gfpga_pad_io_soc_out[102]" x="0" y="2" z="2"/>
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<io pad="gfpga_pad_io_soc_in[103]" x="0" y="2" z="3"/>
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<io pad="gfpga_pad_io_soc_out[103]" x="0" y="2" z="3"/>
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<io pad="gfpga_pad_io_soc_in[104]" x="0" y="3" z="0"/>
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<io pad="gfpga_pad_io_soc_out[104]" x="0" y="3" z="0"/>
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<io pad="gfpga_pad_io_soc_in[105]" x="0" y="3" z="1"/>
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<io pad="gfpga_pad_io_soc_out[105]" x="0" y="3" z="1"/>
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<io pad="gfpga_pad_io_soc_in[106]" x="0" y="3" z="2"/>
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<io pad="gfpga_pad_io_soc_out[106]" x="0" y="3" z="2"/>
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<io pad="gfpga_pad_io_soc_in[107]" x="0" y="3" z="3"/>
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<io pad="gfpga_pad_io_soc_out[107]" x="0" y="3" z="3"/>
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<io pad="gfpga_pad_io_soc_in[108]" x="0" y="4" z="0"/>
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<io pad="gfpga_pad_io_soc_out[108]" x="0" y="4" z="0"/>
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<io pad="gfpga_pad_io_soc_in[109]" x="0" y="4" z="1"/>
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<io pad="gfpga_pad_io_soc_out[109]" x="0" y="4" z="1"/>
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<io pad="gfpga_pad_io_soc_in[110]" x="0" y="4" z="2"/>
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<io pad="gfpga_pad_io_soc_out[110]" x="0" y="4" z="2"/>
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<io pad="gfpga_pad_io_soc_in[111]" x="0" y="4" z="3"/>
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<io pad="gfpga_pad_io_soc_out[111]" x="0" y="4" z="3"/>
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<io pad="gfpga_pad_io_soc_in[112]" x="0" y="5" z="0"/>
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<io pad="gfpga_pad_io_soc_out[112]" x="0" y="5" z="0"/>
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<io pad="gfpga_pad_io_soc_in[113]" x="0" y="5" z="1"/>
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<io pad="gfpga_pad_io_soc_out[113]" x="0" y="5" z="1"/>
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<io pad="gfpga_pad_io_soc_in[114]" x="0" y="5" z="2"/>
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<io pad="gfpga_pad_io_soc_out[114]" x="0" y="5" z="2"/>
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<io pad="gfpga_pad_io_soc_in[115]" x="0" y="5" z="3"/>
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<io pad="gfpga_pad_io_soc_out[115]" x="0" y="5" z="3"/>
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<io pad="gfpga_pad_io_soc_in[116]" x="0" y="6" z="0"/>
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<io pad="gfpga_pad_io_soc_out[116]" x="0" y="6" z="0"/>
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<io pad="gfpga_pad_io_soc_in[117]" x="0" y="6" z="1"/>
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<io pad="gfpga_pad_io_soc_out[117]" x="0" y="6" z="1"/>
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<io pad="gfpga_pad_io_soc_in[118]" x="0" y="6" z="2"/>
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<io pad="gfpga_pad_io_soc_out[118]" x="0" y="6" z="2"/>
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<io pad="gfpga_pad_io_soc_in[119]" x="0" y="6" z="3"/>
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<io pad="gfpga_pad_io_soc_out[119]" x="0" y="6" z="3"/>
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<io pad="gfpga_pad_io_soc_in[120]" x="0" y="7" z="0"/>
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<io pad="gfpga_pad_io_soc_out[120]" x="0" y="7" z="0"/>
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<io pad="gfpga_pad_io_soc_in[121]" x="0" y="7" z="1"/>
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<io pad="gfpga_pad_io_soc_out[121]" x="0" y="7" z="1"/>
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<io pad="gfpga_pad_io_soc_in[122]" x="0" y="7" z="2"/>
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<io pad="gfpga_pad_io_soc_out[122]" x="0" y="7" z="2"/>
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<io pad="gfpga_pad_io_soc_in[123]" x="0" y="7" z="3"/>
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<io pad="gfpga_pad_io_soc_out[123]" x="0" y="7" z="3"/>
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<io pad="gfpga_pad_io_soc_in[124]" x="0" y="8" z="0"/>
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<io pad="gfpga_pad_io_soc_out[124]" x="0" y="8" z="0"/>
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<io pad="gfpga_pad_io_soc_in[125]" x="0" y="8" z="1"/>
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<io pad="gfpga_pad_io_soc_out[125]" x="0" y="8" z="1"/>
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<io pad="gfpga_pad_io_soc_in[126]" x="0" y="8" z="2"/>
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<io pad="gfpga_pad_io_soc_out[126]" x="0" y="8" z="2"/>
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<io pad="gfpga_pad_io_soc_in[127]" x="0" y="8" z="3"/>
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<io pad="gfpga_pad_io_soc_out[127]" x="0" y="8" z="3"/>
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<io pad="gfpga_pad_io_soc_in[92]" x="1" y="0" z="0"/>
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<io pad="gfpga_pad_io_soc_out[92]" x="1" y="0" z="0"/>
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<io pad="gfpga_pad_io_soc_in[93]" x="1" y="0" z="1"/>
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<io pad="gfpga_pad_io_soc_out[93]" x="1" y="0" z="1"/>
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<io pad="gfpga_pad_io_soc_in[94]" x="1" y="0" z="2"/>
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<io pad="gfpga_pad_io_soc_out[94]" x="1" y="0" z="2"/>
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<io pad="gfpga_pad_io_soc_in[95]" x="1" y="0" z="3"/>
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<io pad="gfpga_pad_io_soc_out[95]" x="1" y="0" z="3"/>
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<io pad="gfpga_pad_io_soc_in[0]" x="1" y="9" z="0"/>
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<io pad="gfpga_pad_io_soc_out[0]" x="1" y="9" z="0"/>
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<io pad="gfpga_pad_io_soc_in[1]" x="1" y="9" z="1"/>
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<io pad="gfpga_pad_io_soc_out[1]" x="1" y="9" z="1"/>
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<io pad="gfpga_pad_io_soc_in[2]" x="1" y="9" z="2"/>
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<io pad="gfpga_pad_io_soc_out[2]" x="1" y="9" z="2"/>
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<io pad="gfpga_pad_io_soc_in[3]" x="1" y="9" z="3"/>
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<io pad="gfpga_pad_io_soc_out[3]" x="1" y="9" z="3"/>
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<io pad="gfpga_pad_io_soc_in[88]" x="2" y="0" z="0"/>
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<io pad="gfpga_pad_io_soc_out[88]" x="2" y="0" z="0"/>
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<io pad="gfpga_pad_io_soc_in[89]" x="2" y="0" z="1"/>
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<io pad="gfpga_pad_io_soc_out[89]" x="2" y="0" z="1"/>
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<io pad="gfpga_pad_io_soc_in[90]" x="2" y="0" z="2"/>
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<io pad="gfpga_pad_io_soc_out[90]" x="2" y="0" z="2"/>
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<io pad="gfpga_pad_io_soc_in[91]" x="2" y="0" z="3"/>
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<io pad="gfpga_pad_io_soc_out[91]" x="2" y="0" z="3"/>
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<io pad="gfpga_pad_io_soc_in[4]" x="2" y="9" z="0"/>
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<io pad="gfpga_pad_io_soc_out[4]" x="2" y="9" z="0"/>
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<io pad="gfpga_pad_io_soc_in[5]" x="2" y="9" z="1"/>
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<io pad="gfpga_pad_io_soc_out[5]" x="2" y="9" z="1"/>
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<io pad="gfpga_pad_io_soc_in[6]" x="2" y="9" z="2"/>
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<io pad="gfpga_pad_io_soc_out[6]" x="2" y="9" z="2"/>
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<io pad="gfpga_pad_io_soc_in[7]" x="2" y="9" z="3"/>
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<io pad="gfpga_pad_io_soc_out[7]" x="2" y="9" z="3"/>
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<io pad="gfpga_pad_io_soc_in[84]" x="3" y="0" z="0"/>
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<io pad="gfpga_pad_io_soc_out[84]" x="3" y="0" z="0"/>
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<io pad="gfpga_pad_io_soc_in[85]" x="3" y="0" z="1"/>
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<io pad="gfpga_pad_io_soc_out[85]" x="3" y="0" z="1"/>
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<io pad="gfpga_pad_io_soc_in[86]" x="3" y="0" z="2"/>
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<io pad="gfpga_pad_io_soc_out[86]" x="3" y="0" z="2"/>
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<io pad="gfpga_pad_io_soc_in[87]" x="3" y="0" z="3"/>
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<io pad="gfpga_pad_io_soc_out[87]" x="3" y="0" z="3"/>
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<io pad="gfpga_pad_io_soc_in[8]" x="3" y="9" z="0"/>
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<io pad="gfpga_pad_io_soc_out[8]" x="3" y="9" z="0"/>
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<io pad="gfpga_pad_io_soc_in[9]" x="3" y="9" z="1"/>
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<io pad="gfpga_pad_io_soc_out[9]" x="3" y="9" z="1"/>
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<io pad="gfpga_pad_io_soc_in[10]" x="3" y="9" z="2"/>
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<io pad="gfpga_pad_io_soc_out[10]" x="3" y="9" z="2"/>
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<io pad="gfpga_pad_io_soc_in[11]" x="3" y="9" z="3"/>
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<io pad="gfpga_pad_io_soc_out[11]" x="3" y="9" z="3"/>
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<io pad="gfpga_pad_io_soc_in[80]" x="4" y="0" z="0"/>
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<io pad="gfpga_pad_io_soc_out[80]" x="4" y="0" z="0"/>
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<io pad="gfpga_pad_io_soc_in[81]" x="4" y="0" z="1"/>
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<io pad="gfpga_pad_io_soc_out[81]" x="4" y="0" z="1"/>
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<io pad="gfpga_pad_io_soc_in[82]" x="4" y="0" z="2"/>
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<io pad="gfpga_pad_io_soc_out[82]" x="4" y="0" z="2"/>
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<io pad="gfpga_pad_io_soc_in[83]" x="4" y="0" z="3"/>
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<io pad="gfpga_pad_io_soc_out[83]" x="4" y="0" z="3"/>
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<io pad="gfpga_pad_io_soc_in[12]" x="4" y="9" z="0"/>
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<io pad="gfpga_pad_io_soc_out[12]" x="4" y="9" z="0"/>
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<io pad="gfpga_pad_io_soc_in[13]" x="4" y="9" z="1"/>
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<io pad="gfpga_pad_io_soc_out[13]" x="4" y="9" z="1"/>
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<io pad="gfpga_pad_io_soc_in[14]" x="4" y="9" z="2"/>
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<io pad="gfpga_pad_io_soc_out[14]" x="4" y="9" z="2"/>
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<io pad="gfpga_pad_io_soc_in[15]" x="4" y="9" z="3"/>
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<io pad="gfpga_pad_io_soc_out[15]" x="4" y="9" z="3"/>
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<io pad="gfpga_pad_io_soc_in[76]" x="5" y="0" z="0"/>
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<io pad="gfpga_pad_io_soc_out[76]" x="5" y="0" z="0"/>
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<io pad="gfpga_pad_io_soc_in[77]" x="5" y="0" z="1"/>
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<io pad="gfpga_pad_io_soc_out[77]" x="5" y="0" z="1"/>
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<io pad="gfpga_pad_io_soc_in[78]" x="5" y="0" z="2"/>
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<io pad="gfpga_pad_io_soc_out[78]" x="5" y="0" z="2"/>
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<io pad="gfpga_pad_io_soc_in[79]" x="5" y="0" z="3"/>
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<io pad="gfpga_pad_io_soc_out[79]" x="5" y="0" z="3"/>
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<io pad="gfpga_pad_io_soc_in[16]" x="5" y="9" z="0"/>
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<io pad="gfpga_pad_io_soc_out[16]" x="5" y="9" z="0"/>
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<io pad="gfpga_pad_io_soc_in[17]" x="5" y="9" z="1"/>
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<io pad="gfpga_pad_io_soc_out[17]" x="5" y="9" z="1"/>
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<io pad="gfpga_pad_io_soc_in[18]" x="5" y="9" z="2"/>
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<io pad="gfpga_pad_io_soc_out[18]" x="5" y="9" z="2"/>
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<io pad="gfpga_pad_io_soc_in[19]" x="5" y="9" z="3"/>
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<io pad="gfpga_pad_io_soc_out[19]" x="5" y="9" z="3"/>
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<io pad="gfpga_pad_io_soc_in[72]" x="6" y="0" z="0"/>
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<io pad="gfpga_pad_io_soc_out[72]" x="6" y="0" z="0"/>
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<io pad="gfpga_pad_io_soc_in[73]" x="6" y="0" z="1"/>
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<io pad="gfpga_pad_io_soc_out[73]" x="6" y="0" z="1"/>
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<io pad="gfpga_pad_io_soc_in[74]" x="6" y="0" z="2"/>
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<io pad="gfpga_pad_io_soc_out[74]" x="6" y="0" z="2"/>
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<io pad="gfpga_pad_io_soc_in[75]" x="6" y="0" z="3"/>
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<io pad="gfpga_pad_io_soc_out[75]" x="6" y="0" z="3"/>
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<io pad="gfpga_pad_io_soc_in[20]" x="6" y="9" z="0"/>
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<io pad="gfpga_pad_io_soc_out[20]" x="6" y="9" z="0"/>
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<io pad="gfpga_pad_io_soc_in[21]" x="6" y="9" z="1"/>
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<io pad="gfpga_pad_io_soc_out[21]" x="6" y="9" z="1"/>
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<io pad="gfpga_pad_io_soc_in[22]" x="6" y="9" z="2"/>
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<io pad="gfpga_pad_io_soc_out[22]" x="6" y="9" z="2"/>
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<io pad="gfpga_pad_io_soc_in[23]" x="6" y="9" z="3"/>
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<io pad="gfpga_pad_io_soc_out[23]" x="6" y="9" z="3"/>
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<io pad="gfpga_pad_io_soc_in[68]" x="7" y="0" z="0"/>
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<io pad="gfpga_pad_io_soc_out[68]" x="7" y="0" z="0"/>
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<io pad="gfpga_pad_io_soc_in[69]" x="7" y="0" z="1"/>
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<io pad="gfpga_pad_io_soc_out[69]" x="7" y="0" z="1"/>
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<io pad="gfpga_pad_io_soc_in[70]" x="7" y="0" z="2"/>
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<io pad="gfpga_pad_io_soc_out[70]" x="7" y="0" z="2"/>
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<io pad="gfpga_pad_io_soc_in[71]" x="7" y="0" z="3"/>
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<io pad="gfpga_pad_io_soc_out[71]" x="7" y="0" z="3"/>
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<io pad="gfpga_pad_io_soc_in[24]" x="7" y="9" z="0"/>
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<io pad="gfpga_pad_io_soc_out[24]" x="7" y="9" z="0"/>
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<io pad="gfpga_pad_io_soc_in[25]" x="7" y="9" z="1"/>
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<io pad="gfpga_pad_io_soc_out[25]" x="7" y="9" z="1"/>
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<io pad="gfpga_pad_io_soc_in[26]" x="7" y="9" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_out[26]" x="7" y="9" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_in[27]" x="7" y="9" z="3"/>
|
||||
<io pad="gfpga_pad_io_soc_out[27]" x="7" y="9" z="3"/>
|
||||
<io pad="gfpga_pad_io_soc_in[64]" x="8" y="0" z="0"/>
|
||||
<io pad="gfpga_pad_io_soc_out[64]" x="8" y="0" z="0"/>
|
||||
<io pad="gfpga_pad_io_soc_in[65]" x="8" y="0" z="1"/>
|
||||
<io pad="gfpga_pad_io_soc_out[65]" x="8" y="0" z="1"/>
|
||||
<io pad="gfpga_pad_io_soc_in[66]" x="8" y="0" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_out[66]" x="8" y="0" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_in[67]" x="8" y="0" z="3"/>
|
||||
<io pad="gfpga_pad_io_soc_out[67]" x="8" y="0" z="3"/>
|
||||
<io pad="gfpga_pad_io_soc_in[28]" x="8" y="9" z="0"/>
|
||||
<io pad="gfpga_pad_io_soc_out[28]" x="8" y="9" z="0"/>
|
||||
<io pad="gfpga_pad_io_soc_in[29]" x="8" y="9" z="1"/>
|
||||
<io pad="gfpga_pad_io_soc_out[29]" x="8" y="9" z="1"/>
|
||||
<io pad="gfpga_pad_io_soc_in[30]" x="8" y="9" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_out[30]" x="8" y="9" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_in[31]" x="8" y="9" z="3"/>
|
||||
<io pad="gfpga_pad_io_soc_out[31]" x="8" y="9" z="3"/>
|
||||
<io pad="gfpga_pad_io_soc_in[60]" x="9" y="1" z="0"/>
|
||||
<io pad="gfpga_pad_io_soc_out[60]" x="9" y="1" z="0"/>
|
||||
<io pad="gfpga_pad_io_soc_in[61]" x="9" y="1" z="1"/>
|
||||
<io pad="gfpga_pad_io_soc_out[61]" x="9" y="1" z="1"/>
|
||||
<io pad="gfpga_pad_io_soc_in[62]" x="9" y="1" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_out[62]" x="9" y="1" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_in[63]" x="9" y="1" z="3"/>
|
||||
<io pad="gfpga_pad_io_soc_out[63]" x="9" y="1" z="3"/>
|
||||
<io pad="gfpga_pad_io_soc_in[56]" x="9" y="2" z="0"/>
|
||||
<io pad="gfpga_pad_io_soc_out[56]" x="9" y="2" z="0"/>
|
||||
<io pad="gfpga_pad_io_soc_in[57]" x="9" y="2" z="1"/>
|
||||
<io pad="gfpga_pad_io_soc_out[57]" x="9" y="2" z="1"/>
|
||||
<io pad="gfpga_pad_io_soc_in[58]" x="9" y="2" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_out[58]" x="9" y="2" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_in[59]" x="9" y="2" z="3"/>
|
||||
<io pad="gfpga_pad_io_soc_out[59]" x="9" y="2" z="3"/>
|
||||
<io pad="gfpga_pad_io_soc_in[52]" x="9" y="3" z="0"/>
|
||||
<io pad="gfpga_pad_io_soc_out[52]" x="9" y="3" z="0"/>
|
||||
<io pad="gfpga_pad_io_soc_in[53]" x="9" y="3" z="1"/>
|
||||
<io pad="gfpga_pad_io_soc_out[53]" x="9" y="3" z="1"/>
|
||||
<io pad="gfpga_pad_io_soc_in[54]" x="9" y="3" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_out[54]" x="9" y="3" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_in[55]" x="9" y="3" z="3"/>
|
||||
<io pad="gfpga_pad_io_soc_out[55]" x="9" y="3" z="3"/>
|
||||
<io pad="gfpga_pad_io_soc_in[48]" x="9" y="4" z="0"/>
|
||||
<io pad="gfpga_pad_io_soc_out[48]" x="9" y="4" z="0"/>
|
||||
<io pad="gfpga_pad_io_soc_in[49]" x="9" y="4" z="1"/>
|
||||
<io pad="gfpga_pad_io_soc_out[49]" x="9" y="4" z="1"/>
|
||||
<io pad="gfpga_pad_io_soc_in[50]" x="9" y="4" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_out[50]" x="9" y="4" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_in[51]" x="9" y="4" z="3"/>
|
||||
<io pad="gfpga_pad_io_soc_out[51]" x="9" y="4" z="3"/>
|
||||
<io pad="gfpga_pad_io_soc_in[44]" x="9" y="5" z="0"/>
|
||||
<io pad="gfpga_pad_io_soc_out[44]" x="9" y="5" z="0"/>
|
||||
<io pad="gfpga_pad_io_soc_in[45]" x="9" y="5" z="1"/>
|
||||
<io pad="gfpga_pad_io_soc_out[45]" x="9" y="5" z="1"/>
|
||||
<io pad="gfpga_pad_io_soc_in[46]" x="9" y="5" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_out[46]" x="9" y="5" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_in[47]" x="9" y="5" z="3"/>
|
||||
<io pad="gfpga_pad_io_soc_out[47]" x="9" y="5" z="3"/>
|
||||
<io pad="gfpga_pad_io_soc_in[40]" x="9" y="6" z="0"/>
|
||||
<io pad="gfpga_pad_io_soc_out[40]" x="9" y="6" z="0"/>
|
||||
<io pad="gfpga_pad_io_soc_in[41]" x="9" y="6" z="1"/>
|
||||
<io pad="gfpga_pad_io_soc_out[41]" x="9" y="6" z="1"/>
|
||||
<io pad="gfpga_pad_io_soc_in[42]" x="9" y="6" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_out[42]" x="9" y="6" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_in[43]" x="9" y="6" z="3"/>
|
||||
<io pad="gfpga_pad_io_soc_out[43]" x="9" y="6" z="3"/>
|
||||
<io pad="gfpga_pad_io_soc_in[36]" x="9" y="7" z="0"/>
|
||||
<io pad="gfpga_pad_io_soc_out[36]" x="9" y="7" z="0"/>
|
||||
<io pad="gfpga_pad_io_soc_in[37]" x="9" y="7" z="1"/>
|
||||
<io pad="gfpga_pad_io_soc_out[37]" x="9" y="7" z="1"/>
|
||||
<io pad="gfpga_pad_io_soc_in[38]" x="9" y="7" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_out[38]" x="9" y="7" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_in[39]" x="9" y="7" z="3"/>
|
||||
<io pad="gfpga_pad_io_soc_out[39]" x="9" y="7" z="3"/>
|
||||
<io pad="gfpga_pad_io_soc_in[32]" x="9" y="8" z="0"/>
|
||||
<io pad="gfpga_pad_io_soc_out[32]" x="9" y="8" z="0"/>
|
||||
<io pad="gfpga_pad_io_soc_in[33]" x="9" y="8" z="1"/>
|
||||
<io pad="gfpga_pad_io_soc_out[33]" x="9" y="8" z="1"/>
|
||||
<io pad="gfpga_pad_io_soc_in[34]" x="9" y="8" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_out[34]" x="9" y="8" z="2"/>
|
||||
<io pad="gfpga_pad_io_soc_in[35]" x="9" y="8" z="3"/>
|
||||
<io pad="gfpga_pad_io_soc_out[35]" x="9" y="8" z="3"/>
|
||||
</io_coordinates>
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -23,6 +23,7 @@ module grid_clb
|
|||
right_width_0_height_0_subtile_0__pin_I7_1_,
|
||||
right_width_0_height_0_subtile_0__pin_I7i_0_,
|
||||
right_width_0_height_0_subtile_0__pin_I7i_1_,
|
||||
sc_in,
|
||||
test_enable,
|
||||
top_width_0_height_0_subtile_0__pin_I0_0_,
|
||||
top_width_0_height_0_subtile_0__pin_I0_1_,
|
||||
|
|
@ -42,10 +43,8 @@ module grid_clb
|
|||
top_width_0_height_0_subtile_0__pin_I3i_1_,
|
||||
top_width_0_height_0_subtile_0__pin_cin_0_,
|
||||
top_width_0_height_0_subtile_0__pin_reg_in_0_,
|
||||
top_width_0_height_0_subtile_0__pin_sc_in_0_,
|
||||
bottom_width_0_height_0_subtile_0__pin_cout_0_,
|
||||
bottom_width_0_height_0_subtile_0__pin_reg_out_0_,
|
||||
bottom_width_0_height_0_subtile_0__pin_sc_out_0_,
|
||||
ccff_tail,
|
||||
right_width_0_height_0_subtile_0__pin_O_10_,
|
||||
right_width_0_height_0_subtile_0__pin_O_11_,
|
||||
|
|
@ -55,6 +54,7 @@ module grid_clb
|
|||
right_width_0_height_0_subtile_0__pin_O_15_,
|
||||
right_width_0_height_0_subtile_0__pin_O_8_,
|
||||
right_width_0_height_0_subtile_0__pin_O_9_,
|
||||
sc_out,
|
||||
top_width_0_height_0_subtile_0__pin_O_0_,
|
||||
top_width_0_height_0_subtile_0__pin_O_1_,
|
||||
top_width_0_height_0_subtile_0__pin_O_2_,
|
||||
|
|
@ -86,6 +86,7 @@ module grid_clb
|
|||
input right_width_0_height_0_subtile_0__pin_I7_1_;
|
||||
input right_width_0_height_0_subtile_0__pin_I7i_0_;
|
||||
input right_width_0_height_0_subtile_0__pin_I7i_1_;
|
||||
input sc_in;
|
||||
input test_enable;
|
||||
input top_width_0_height_0_subtile_0__pin_I0_0_;
|
||||
input top_width_0_height_0_subtile_0__pin_I0_1_;
|
||||
|
|
@ -105,10 +106,8 @@ module grid_clb
|
|||
input top_width_0_height_0_subtile_0__pin_I3i_1_;
|
||||
input top_width_0_height_0_subtile_0__pin_cin_0_;
|
||||
input top_width_0_height_0_subtile_0__pin_reg_in_0_;
|
||||
input top_width_0_height_0_subtile_0__pin_sc_in_0_;
|
||||
output bottom_width_0_height_0_subtile_0__pin_cout_0_;
|
||||
output bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
|
||||
output bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
|
||||
output ccff_tail;
|
||||
output right_width_0_height_0_subtile_0__pin_O_10_;
|
||||
output right_width_0_height_0_subtile_0__pin_O_11_;
|
||||
|
|
@ -118,6 +117,7 @@ module grid_clb
|
|||
output right_width_0_height_0_subtile_0__pin_O_15_;
|
||||
output right_width_0_height_0_subtile_0__pin_O_8_;
|
||||
output right_width_0_height_0_subtile_0__pin_O_9_;
|
||||
output sc_out;
|
||||
output top_width_0_height_0_subtile_0__pin_O_0_;
|
||||
output top_width_0_height_0_subtile_0__pin_O_1_;
|
||||
output top_width_0_height_0_subtile_0__pin_O_2_;
|
||||
|
|
@ -129,7 +129,6 @@ module grid_clb
|
|||
|
||||
wire bottom_width_0_height_0_subtile_0__pin_cout_0_;
|
||||
wire bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
|
||||
wire bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
|
||||
wire ccff_head;
|
||||
wire ccff_tail;
|
||||
wire clk0;
|
||||
|
|
@ -160,6 +159,8 @@ module grid_clb
|
|||
wire right_width_0_height_0_subtile_0__pin_O_15_;
|
||||
wire right_width_0_height_0_subtile_0__pin_O_8_;
|
||||
wire right_width_0_height_0_subtile_0__pin_O_9_;
|
||||
wire sc_in;
|
||||
wire sc_out;
|
||||
wire test_enable;
|
||||
wire top_width_0_height_0_subtile_0__pin_I0_0_;
|
||||
wire top_width_0_height_0_subtile_0__pin_I0_1_;
|
||||
|
|
@ -187,7 +188,6 @@ module grid_clb
|
|||
wire top_width_0_height_0_subtile_0__pin_O_7_;
|
||||
wire top_width_0_height_0_subtile_0__pin_cin_0_;
|
||||
wire top_width_0_height_0_subtile_0__pin_reg_in_0_;
|
||||
wire top_width_0_height_0_subtile_0__pin_sc_in_0_;
|
||||
|
||||
logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0
|
||||
(
|
||||
|
|
@ -212,7 +212,7 @@ module grid_clb
|
|||
.clb_clk(clk0),
|
||||
.clb_reg_in(top_width_0_height_0_subtile_0__pin_reg_in_0_),
|
||||
.clb_reset(reset),
|
||||
.clb_sc_in(top_width_0_height_0_subtile_0__pin_sc_in_0_),
|
||||
.clb_sc_in(sc_in),
|
||||
.prog_clk(prog_clk),
|
||||
.prog_reset(prog_reset),
|
||||
.test_enable(test_enable),
|
||||
|
|
@ -220,7 +220,7 @@ module grid_clb
|
|||
.clb_O({top_width_0_height_0_subtile_0__pin_O_0_, top_width_0_height_0_subtile_0__pin_O_1_, top_width_0_height_0_subtile_0__pin_O_2_, top_width_0_height_0_subtile_0__pin_O_3_, top_width_0_height_0_subtile_0__pin_O_4_, top_width_0_height_0_subtile_0__pin_O_5_, top_width_0_height_0_subtile_0__pin_O_6_, top_width_0_height_0_subtile_0__pin_O_7_, right_width_0_height_0_subtile_0__pin_O_8_, right_width_0_height_0_subtile_0__pin_O_9_, right_width_0_height_0_subtile_0__pin_O_10_, right_width_0_height_0_subtile_0__pin_O_11_, right_width_0_height_0_subtile_0__pin_O_12_, right_width_0_height_0_subtile_0__pin_O_13_, right_width_0_height_0_subtile_0__pin_O_14_, right_width_0_height_0_subtile_0__pin_O_15_}),
|
||||
.clb_cout(bottom_width_0_height_0_subtile_0__pin_cout_0_),
|
||||
.clb_reg_out(bottom_width_0_height_0_subtile_0__pin_reg_out_0_),
|
||||
.clb_sc_out(bottom_width_0_height_0_subtile_0__pin_sc_out_0_)
|
||||
.clb_sc_out(sc_out)
|
||||
);
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@ module right_tile
|
|||
reset_bottom_in,
|
||||
reset_right_in,
|
||||
reset_top_in,
|
||||
sc_in,
|
||||
test_enable_bottom_in,
|
||||
test_enable_right_in,
|
||||
test_enable_top_in,
|
||||
|
|
@ -35,10 +36,8 @@ module right_tile
|
|||
top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_,
|
||||
top_width_0_height_0_subtile_0__pin_cin_0_,
|
||||
top_width_0_height_0_subtile_0__pin_reg_in_0_,
|
||||
top_width_0_height_0_subtile_0__pin_sc_in_0_,
|
||||
bottom_width_0_height_0_subtile_0__pin_cout_0_,
|
||||
bottom_width_0_height_0_subtile_0__pin_reg_out_0_,
|
||||
bottom_width_0_height_0_subtile_0__pin_sc_out_0_,
|
||||
ccff_tail,
|
||||
ccff_tail_0,
|
||||
ccff_tail_1,
|
||||
|
|
@ -64,6 +63,7 @@ module right_tile
|
|||
right_width_0_height_0_subtile_0__pin_O_15_,
|
||||
right_width_0_height_0_subtile_0__pin_O_8_,
|
||||
right_width_0_height_0_subtile_0__pin_O_9_,
|
||||
sc_out,
|
||||
test_enable_bottom_out,
|
||||
test_enable_left_out,
|
||||
test_enable_top_out,
|
||||
|
|
@ -93,6 +93,7 @@ module right_tile
|
|||
input reset_bottom_in;
|
||||
input reset_right_in;
|
||||
input reset_top_in;
|
||||
input sc_in;
|
||||
input test_enable_bottom_in;
|
||||
input test_enable_right_in;
|
||||
input test_enable_top_in;
|
||||
|
|
@ -110,10 +111,8 @@ module right_tile
|
|||
input top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
input top_width_0_height_0_subtile_0__pin_cin_0_;
|
||||
input top_width_0_height_0_subtile_0__pin_reg_in_0_;
|
||||
input top_width_0_height_0_subtile_0__pin_sc_in_0_;
|
||||
output bottom_width_0_height_0_subtile_0__pin_cout_0_;
|
||||
output bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
|
||||
output bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
|
||||
output ccff_tail;
|
||||
output ccff_tail_0;
|
||||
output ccff_tail_1;
|
||||
|
|
@ -139,6 +138,7 @@ module right_tile
|
|||
output right_width_0_height_0_subtile_0__pin_O_15_;
|
||||
output right_width_0_height_0_subtile_0__pin_O_8_;
|
||||
output right_width_0_height_0_subtile_0__pin_O_9_;
|
||||
output sc_out;
|
||||
output test_enable_bottom_out;
|
||||
output test_enable_left_out;
|
||||
output test_enable_top_out;
|
||||
|
|
@ -169,7 +169,6 @@ module right_tile
|
|||
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_;
|
||||
wire bottom_width_0_height_0_subtile_0__pin_cout_0_;
|
||||
wire bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
|
||||
wire bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
|
||||
wire ccff_head_0_0;
|
||||
wire ccff_head_1;
|
||||
wire ccff_head_2;
|
||||
|
|
@ -235,6 +234,8 @@ module right_tile
|
|||
wire right_width_0_height_0_subtile_0__pin_O_15_;
|
||||
wire right_width_0_height_0_subtile_0__pin_O_8_;
|
||||
wire right_width_0_height_0_subtile_0__pin_O_9_;
|
||||
wire sc_in;
|
||||
wire sc_out;
|
||||
wire test_enable;
|
||||
wire test_enable_bottom_in;
|
||||
wire test_enable_bottom_out;
|
||||
|
|
@ -264,7 +265,6 @@ module right_tile
|
|||
wire top_width_0_height_0_subtile_0__pin_O_7_;
|
||||
wire top_width_0_height_0_subtile_0__pin_cin_0_;
|
||||
wire top_width_0_height_0_subtile_0__pin_reg_in_0_;
|
||||
wire top_width_0_height_0_subtile_0__pin_sc_in_0_;
|
||||
|
||||
assign prog_reset = prog_reset_bottom_in;
|
||||
assign prog_reset_top_in = prog_reset_left_in;
|
||||
|
|
@ -370,6 +370,7 @@ assign test_enable_bottom_out = test_enable_top_out;
|
|||
.right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
|
||||
.right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
|
||||
.right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
|
||||
.sc_in(sc_in),
|
||||
.test_enable(test_enable),
|
||||
.top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
|
||||
.top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
|
||||
|
|
@ -389,10 +390,8 @@ assign test_enable_bottom_out = test_enable_top_out;
|
|||
.top_width_0_height_0_subtile_0__pin_I3i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_),
|
||||
.top_width_0_height_0_subtile_0__pin_cin_0_(top_width_0_height_0_subtile_0__pin_cin_0_),
|
||||
.top_width_0_height_0_subtile_0__pin_reg_in_0_(top_width_0_height_0_subtile_0__pin_reg_in_0_),
|
||||
.top_width_0_height_0_subtile_0__pin_sc_in_0_(top_width_0_height_0_subtile_0__pin_sc_in_0_),
|
||||
.bottom_width_0_height_0_subtile_0__pin_cout_0_(bottom_width_0_height_0_subtile_0__pin_cout_0_),
|
||||
.bottom_width_0_height_0_subtile_0__pin_reg_out_0_(bottom_width_0_height_0_subtile_0__pin_reg_out_0_),
|
||||
.bottom_width_0_height_0_subtile_0__pin_sc_out_0_(bottom_width_0_height_0_subtile_0__pin_sc_out_0_),
|
||||
.ccff_tail(ccff_tail),
|
||||
.right_width_0_height_0_subtile_0__pin_O_10_(right_width_0_height_0_subtile_0__pin_O_10_),
|
||||
.right_width_0_height_0_subtile_0__pin_O_11_(right_width_0_height_0_subtile_0__pin_O_11_),
|
||||
|
|
@ -402,6 +401,7 @@ assign test_enable_bottom_out = test_enable_top_out;
|
|||
.right_width_0_height_0_subtile_0__pin_O_15_(right_width_0_height_0_subtile_0__pin_O_15_),
|
||||
.right_width_0_height_0_subtile_0__pin_O_8_(right_width_0_height_0_subtile_0__pin_O_8_),
|
||||
.right_width_0_height_0_subtile_0__pin_O_9_(right_width_0_height_0_subtile_0__pin_O_9_),
|
||||
.sc_out(sc_out),
|
||||
.top_width_0_height_0_subtile_0__pin_O_0_(top_width_0_height_0_subtile_0__pin_O_0_),
|
||||
.top_width_0_height_0_subtile_0__pin_O_1_(top_width_0_height_0_subtile_0__pin_O_1_),
|
||||
.top_width_0_height_0_subtile_0__pin_O_2_(top_width_0_height_0_subtile_0__pin_O_2_),
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@ module tile
|
|||
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_,
|
||||
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_,
|
||||
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_,
|
||||
sc_in,
|
||||
test_enable_bottom_in,
|
||||
test_enable_right_in,
|
||||
test_enable_top_in,
|
||||
|
|
@ -37,10 +38,8 @@ module tile
|
|||
top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_,
|
||||
top_width_0_height_0_subtile_0__pin_cin_0_,
|
||||
top_width_0_height_0_subtile_0__pin_reg_in_0_,
|
||||
top_width_0_height_0_subtile_0__pin_sc_in_0_,
|
||||
bottom_width_0_height_0_subtile_0__pin_cout_0_,
|
||||
bottom_width_0_height_0_subtile_0__pin_reg_out_0_,
|
||||
bottom_width_0_height_0_subtile_0__pin_sc_out_0_,
|
||||
ccff_tail,
|
||||
ccff_tail_0,
|
||||
chanx_left_out,
|
||||
|
|
@ -61,6 +60,7 @@ module tile
|
|||
right_width_0_height_0_subtile_0__pin_O_15_,
|
||||
right_width_0_height_0_subtile_0__pin_O_8_,
|
||||
right_width_0_height_0_subtile_0__pin_O_9_,
|
||||
sc_out,
|
||||
test_enable_bottom_out,
|
||||
test_enable_left_out,
|
||||
test_enable_top_out,
|
||||
|
|
@ -96,6 +96,7 @@ module tile
|
|||
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_5_;
|
||||
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_6_;
|
||||
input right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_7_;
|
||||
input sc_in;
|
||||
input test_enable_bottom_in;
|
||||
input test_enable_right_in;
|
||||
input test_enable_top_in;
|
||||
|
|
@ -109,10 +110,8 @@ module tile
|
|||
input top_left_grid_right_width_0_height_0_subtile_0__pin_O_9_;
|
||||
input top_width_0_height_0_subtile_0__pin_cin_0_;
|
||||
input top_width_0_height_0_subtile_0__pin_reg_in_0_;
|
||||
input top_width_0_height_0_subtile_0__pin_sc_in_0_;
|
||||
output bottom_width_0_height_0_subtile_0__pin_cout_0_;
|
||||
output bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
|
||||
output bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
|
||||
output ccff_tail;
|
||||
output ccff_tail_0;
|
||||
output [29:0]chanx_left_out;
|
||||
|
|
@ -133,6 +132,7 @@ module tile
|
|||
output right_width_0_height_0_subtile_0__pin_O_15_;
|
||||
output right_width_0_height_0_subtile_0__pin_O_8_;
|
||||
output right_width_0_height_0_subtile_0__pin_O_9_;
|
||||
output sc_out;
|
||||
output test_enable_bottom_out;
|
||||
output test_enable_left_out;
|
||||
output test_enable_top_out;
|
||||
|
|
@ -163,7 +163,6 @@ module tile
|
|||
wire bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_;
|
||||
wire bottom_width_0_height_0_subtile_0__pin_cout_0_;
|
||||
wire bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
|
||||
wire bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
|
||||
wire ccff_head_1;
|
||||
wire ccff_head_2;
|
||||
wire ccff_tail;
|
||||
|
|
@ -230,6 +229,8 @@ module tile
|
|||
wire right_width_0_height_0_subtile_0__pin_O_15_;
|
||||
wire right_width_0_height_0_subtile_0__pin_O_8_;
|
||||
wire right_width_0_height_0_subtile_0__pin_O_9_;
|
||||
wire sc_in;
|
||||
wire sc_out;
|
||||
wire test_enable;
|
||||
wire test_enable_bottom_in;
|
||||
wire test_enable_bottom_out;
|
||||
|
|
@ -255,7 +256,6 @@ module tile
|
|||
wire top_width_0_height_0_subtile_0__pin_O_7_;
|
||||
wire top_width_0_height_0_subtile_0__pin_cin_0_;
|
||||
wire top_width_0_height_0_subtile_0__pin_reg_in_0_;
|
||||
wire top_width_0_height_0_subtile_0__pin_sc_in_0_;
|
||||
|
||||
assign prog_reset = prog_reset_bottom_in;
|
||||
assign prog_reset_top_in = prog_reset_left_in;
|
||||
|
|
@ -352,6 +352,7 @@ assign test_enable_bottom_out = test_enable_top_out;
|
|||
.right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
|
||||
.right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
|
||||
.right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
|
||||
.sc_in(sc_in),
|
||||
.test_enable(test_enable),
|
||||
.top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
|
||||
.top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
|
||||
|
|
@ -371,10 +372,8 @@ assign test_enable_bottom_out = test_enable_top_out;
|
|||
.top_width_0_height_0_subtile_0__pin_I3i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_),
|
||||
.top_width_0_height_0_subtile_0__pin_cin_0_(top_width_0_height_0_subtile_0__pin_cin_0_),
|
||||
.top_width_0_height_0_subtile_0__pin_reg_in_0_(top_width_0_height_0_subtile_0__pin_reg_in_0_),
|
||||
.top_width_0_height_0_subtile_0__pin_sc_in_0_(top_width_0_height_0_subtile_0__pin_sc_in_0_),
|
||||
.bottom_width_0_height_0_subtile_0__pin_cout_0_(bottom_width_0_height_0_subtile_0__pin_cout_0_),
|
||||
.bottom_width_0_height_0_subtile_0__pin_reg_out_0_(bottom_width_0_height_0_subtile_0__pin_reg_out_0_),
|
||||
.bottom_width_0_height_0_subtile_0__pin_sc_out_0_(bottom_width_0_height_0_subtile_0__pin_sc_out_0_),
|
||||
.ccff_tail(ccff_tail),
|
||||
.right_width_0_height_0_subtile_0__pin_O_10_(right_width_0_height_0_subtile_0__pin_O_10_),
|
||||
.right_width_0_height_0_subtile_0__pin_O_11_(right_width_0_height_0_subtile_0__pin_O_11_),
|
||||
|
|
@ -384,6 +383,7 @@ assign test_enable_bottom_out = test_enable_top_out;
|
|||
.right_width_0_height_0_subtile_0__pin_O_15_(right_width_0_height_0_subtile_0__pin_O_15_),
|
||||
.right_width_0_height_0_subtile_0__pin_O_8_(right_width_0_height_0_subtile_0__pin_O_8_),
|
||||
.right_width_0_height_0_subtile_0__pin_O_9_(right_width_0_height_0_subtile_0__pin_O_9_),
|
||||
.sc_out(sc_out),
|
||||
.top_width_0_height_0_subtile_0__pin_O_0_(top_width_0_height_0_subtile_0__pin_O_0_),
|
||||
.top_width_0_height_0_subtile_0__pin_O_1_(top_width_0_height_0_subtile_0__pin_O_1_),
|
||||
.top_width_0_height_0_subtile_0__pin_O_2_(top_width_0_height_0_subtile_0__pin_O_2_),
|
||||
|
|
|
|||
|
|
@ -13,14 +13,13 @@ module top_right_tile
|
|||
prog_clk,
|
||||
prog_reset_bottom_in,
|
||||
reset_bottom_in,
|
||||
sc_in,
|
||||
test_enable_bottom_in,
|
||||
top_width_0_height_0_subtile_0__pin_cin_0_,
|
||||
top_width_0_height_0_subtile_0__pin_reg_in_0_,
|
||||
top_width_0_height_0_subtile_0__pin_sc_in_0_,
|
||||
bottom_width_0_height_0_subtile_0__pin_cout_0_,
|
||||
bottom_width_0_height_0_subtile_0__pin_inpad_0_,
|
||||
bottom_width_0_height_0_subtile_0__pin_reg_out_0_,
|
||||
bottom_width_0_height_0_subtile_0__pin_sc_out_0_,
|
||||
bottom_width_0_height_0_subtile_1__pin_inpad_0_,
|
||||
bottom_width_0_height_0_subtile_2__pin_inpad_0_,
|
||||
bottom_width_0_height_0_subtile_3__pin_inpad_0_,
|
||||
|
|
@ -44,6 +43,7 @@ module top_right_tile
|
|||
right_width_0_height_0_subtile_0__pin_O_15_,
|
||||
right_width_0_height_0_subtile_0__pin_O_8_,
|
||||
right_width_0_height_0_subtile_0__pin_O_9_,
|
||||
sc_out,
|
||||
top_width_0_height_0_subtile_0__pin_O_0_,
|
||||
top_width_0_height_0_subtile_0__pin_O_1_,
|
||||
top_width_0_height_0_subtile_0__pin_O_2_,
|
||||
|
|
@ -65,14 +65,13 @@ module top_right_tile
|
|||
input prog_clk;
|
||||
input prog_reset_bottom_in;
|
||||
input reset_bottom_in;
|
||||
input sc_in;
|
||||
input test_enable_bottom_in;
|
||||
input top_width_0_height_0_subtile_0__pin_cin_0_;
|
||||
input top_width_0_height_0_subtile_0__pin_reg_in_0_;
|
||||
input top_width_0_height_0_subtile_0__pin_sc_in_0_;
|
||||
output bottom_width_0_height_0_subtile_0__pin_cout_0_;
|
||||
output bottom_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
output bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
|
||||
output bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
|
||||
output bottom_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
output bottom_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
output bottom_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
|
|
@ -96,6 +95,7 @@ module top_right_tile
|
|||
output right_width_0_height_0_subtile_0__pin_O_15_;
|
||||
output right_width_0_height_0_subtile_0__pin_O_8_;
|
||||
output right_width_0_height_0_subtile_0__pin_O_9_;
|
||||
output sc_out;
|
||||
output top_width_0_height_0_subtile_0__pin_O_0_;
|
||||
output top_width_0_height_0_subtile_0__pin_O_1_;
|
||||
output top_width_0_height_0_subtile_0__pin_O_2_;
|
||||
|
|
@ -124,7 +124,6 @@ module top_right_tile
|
|||
wire bottom_width_0_height_0_subtile_0__pin_cout_0_;
|
||||
wire bottom_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
wire bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
|
||||
wire bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
|
||||
wire bottom_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
wire bottom_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
wire bottom_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
|
|
@ -184,6 +183,8 @@ module top_right_tile
|
|||
wire right_width_0_height_0_subtile_0__pin_O_15_;
|
||||
wire right_width_0_height_0_subtile_0__pin_O_8_;
|
||||
wire right_width_0_height_0_subtile_0__pin_O_9_;
|
||||
wire sc_in;
|
||||
wire sc_out;
|
||||
wire test_enable;
|
||||
wire test_enable_bottom_in;
|
||||
wire top_width_0_height_0_subtile_0__pin_O_0_;
|
||||
|
|
@ -196,7 +197,6 @@ module top_right_tile
|
|||
wire top_width_0_height_0_subtile_0__pin_O_7_;
|
||||
wire top_width_0_height_0_subtile_0__pin_cin_0_;
|
||||
wire top_width_0_height_0_subtile_0__pin_reg_in_0_;
|
||||
wire top_width_0_height_0_subtile_0__pin_sc_in_0_;
|
||||
|
||||
assign prog_reset = prog_reset_bottom_in;
|
||||
assign reset = reset_bottom_in;
|
||||
|
|
@ -296,6 +296,7 @@ assign test_enable = test_enable_bottom_in;
|
|||
.right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
|
||||
.right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
|
||||
.right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
|
||||
.sc_in(sc_in),
|
||||
.test_enable(test_enable),
|
||||
.top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
|
||||
.top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
|
||||
|
|
@ -315,10 +316,8 @@ assign test_enable = test_enable_bottom_in;
|
|||
.top_width_0_height_0_subtile_0__pin_I3i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_),
|
||||
.top_width_0_height_0_subtile_0__pin_cin_0_(top_width_0_height_0_subtile_0__pin_cin_0_),
|
||||
.top_width_0_height_0_subtile_0__pin_reg_in_0_(top_width_0_height_0_subtile_0__pin_reg_in_0_),
|
||||
.top_width_0_height_0_subtile_0__pin_sc_in_0_(top_width_0_height_0_subtile_0__pin_sc_in_0_),
|
||||
.bottom_width_0_height_0_subtile_0__pin_cout_0_(bottom_width_0_height_0_subtile_0__pin_cout_0_),
|
||||
.bottom_width_0_height_0_subtile_0__pin_reg_out_0_(bottom_width_0_height_0_subtile_0__pin_reg_out_0_),
|
||||
.bottom_width_0_height_0_subtile_0__pin_sc_out_0_(bottom_width_0_height_0_subtile_0__pin_sc_out_0_),
|
||||
.ccff_tail(ccff_tail),
|
||||
.right_width_0_height_0_subtile_0__pin_O_10_(right_width_0_height_0_subtile_0__pin_O_10_),
|
||||
.right_width_0_height_0_subtile_0__pin_O_11_(right_width_0_height_0_subtile_0__pin_O_11_),
|
||||
|
|
@ -328,6 +327,7 @@ assign test_enable = test_enable_bottom_in;
|
|||
.right_width_0_height_0_subtile_0__pin_O_15_(right_width_0_height_0_subtile_0__pin_O_15_),
|
||||
.right_width_0_height_0_subtile_0__pin_O_8_(right_width_0_height_0_subtile_0__pin_O_8_),
|
||||
.right_width_0_height_0_subtile_0__pin_O_9_(right_width_0_height_0_subtile_0__pin_O_9_),
|
||||
.sc_out(sc_out),
|
||||
.top_width_0_height_0_subtile_0__pin_O_0_(top_width_0_height_0_subtile_0__pin_O_0_),
|
||||
.top_width_0_height_0_subtile_0__pin_O_1_(top_width_0_height_0_subtile_0__pin_O_1_),
|
||||
.top_width_0_height_0_subtile_0__pin_O_2_(top_width_0_height_0_subtile_0__pin_O_2_),
|
||||
|
|
|
|||
|
|
@ -25,14 +25,13 @@ module top_tile
|
|||
right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
|
||||
right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
|
||||
right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
|
||||
sc_in,
|
||||
test_enable_bottom_in,
|
||||
top_width_0_height_0_subtile_0__pin_cin_0_,
|
||||
top_width_0_height_0_subtile_0__pin_reg_in_0_,
|
||||
top_width_0_height_0_subtile_0__pin_sc_in_0_,
|
||||
bottom_width_0_height_0_subtile_0__pin_cout_0_,
|
||||
bottom_width_0_height_0_subtile_0__pin_inpad_0_,
|
||||
bottom_width_0_height_0_subtile_0__pin_reg_out_0_,
|
||||
bottom_width_0_height_0_subtile_0__pin_sc_out_0_,
|
||||
bottom_width_0_height_0_subtile_1__pin_inpad_0_,
|
||||
bottom_width_0_height_0_subtile_2__pin_inpad_0_,
|
||||
bottom_width_0_height_0_subtile_3__pin_inpad_0_,
|
||||
|
|
@ -51,6 +50,7 @@ module top_tile
|
|||
right_width_0_height_0_subtile_0__pin_O_15_,
|
||||
right_width_0_height_0_subtile_0__pin_O_8_,
|
||||
right_width_0_height_0_subtile_0__pin_O_9_,
|
||||
sc_out,
|
||||
top_width_0_height_0_subtile_0__pin_O_0_,
|
||||
top_width_0_height_0_subtile_0__pin_O_1_,
|
||||
top_width_0_height_0_subtile_0__pin_O_2_,
|
||||
|
|
@ -84,14 +84,13 @@ module top_tile
|
|||
input right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
input right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
input right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
input sc_in;
|
||||
input test_enable_bottom_in;
|
||||
input top_width_0_height_0_subtile_0__pin_cin_0_;
|
||||
input top_width_0_height_0_subtile_0__pin_reg_in_0_;
|
||||
input top_width_0_height_0_subtile_0__pin_sc_in_0_;
|
||||
output bottom_width_0_height_0_subtile_0__pin_cout_0_;
|
||||
output bottom_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
output bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
|
||||
output bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
|
||||
output bottom_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
output bottom_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
output bottom_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
|
|
@ -110,6 +109,7 @@ module top_tile
|
|||
output right_width_0_height_0_subtile_0__pin_O_15_;
|
||||
output right_width_0_height_0_subtile_0__pin_O_8_;
|
||||
output right_width_0_height_0_subtile_0__pin_O_9_;
|
||||
output sc_out;
|
||||
output top_width_0_height_0_subtile_0__pin_O_0_;
|
||||
output top_width_0_height_0_subtile_0__pin_O_1_;
|
||||
output top_width_0_height_0_subtile_0__pin_O_2_;
|
||||
|
|
@ -138,7 +138,6 @@ module top_tile
|
|||
wire bottom_width_0_height_0_subtile_0__pin_cout_0_;
|
||||
wire bottom_width_0_height_0_subtile_0__pin_inpad_0_;
|
||||
wire bottom_width_0_height_0_subtile_0__pin_reg_out_0_;
|
||||
wire bottom_width_0_height_0_subtile_0__pin_sc_out_0_;
|
||||
wire bottom_width_0_height_0_subtile_1__pin_inpad_0_;
|
||||
wire bottom_width_0_height_0_subtile_2__pin_inpad_0_;
|
||||
wire bottom_width_0_height_0_subtile_3__pin_inpad_0_;
|
||||
|
|
@ -204,6 +203,8 @@ module top_tile
|
|||
wire right_width_0_height_0_subtile_0__pin_O_15_;
|
||||
wire right_width_0_height_0_subtile_0__pin_O_8_;
|
||||
wire right_width_0_height_0_subtile_0__pin_O_9_;
|
||||
wire sc_in;
|
||||
wire sc_out;
|
||||
wire test_enable;
|
||||
wire test_enable_bottom_in;
|
||||
wire top_width_0_height_0_subtile_0__pin_O_0_;
|
||||
|
|
@ -216,7 +217,6 @@ module top_tile
|
|||
wire top_width_0_height_0_subtile_0__pin_O_7_;
|
||||
wire top_width_0_height_0_subtile_0__pin_cin_0_;
|
||||
wire top_width_0_height_0_subtile_0__pin_reg_in_0_;
|
||||
wire top_width_0_height_0_subtile_0__pin_sc_in_0_;
|
||||
|
||||
assign prog_reset = prog_reset_bottom_in;
|
||||
assign reset = reset_bottom_in;
|
||||
|
|
@ -306,6 +306,7 @@ assign test_enable = test_enable_bottom_in;
|
|||
.right_width_0_height_0_subtile_0__pin_I7_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7_1_),
|
||||
.right_width_0_height_0_subtile_0__pin_I7i_0_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_0_),
|
||||
.right_width_0_height_0_subtile_0__pin_I7i_1_(left_grid_right_width_0_height_0_subtile_0__pin_I7i_1_),
|
||||
.sc_in(sc_in),
|
||||
.test_enable(test_enable),
|
||||
.top_width_0_height_0_subtile_0__pin_I0_0_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_0_),
|
||||
.top_width_0_height_0_subtile_0__pin_I0_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I0_1_),
|
||||
|
|
@ -325,10 +326,8 @@ assign test_enable = test_enable_bottom_in;
|
|||
.top_width_0_height_0_subtile_0__pin_I3i_1_(bottom_grid_top_width_0_height_0_subtile_0__pin_I3i_1_),
|
||||
.top_width_0_height_0_subtile_0__pin_cin_0_(top_width_0_height_0_subtile_0__pin_cin_0_),
|
||||
.top_width_0_height_0_subtile_0__pin_reg_in_0_(top_width_0_height_0_subtile_0__pin_reg_in_0_),
|
||||
.top_width_0_height_0_subtile_0__pin_sc_in_0_(top_width_0_height_0_subtile_0__pin_sc_in_0_),
|
||||
.bottom_width_0_height_0_subtile_0__pin_cout_0_(bottom_width_0_height_0_subtile_0__pin_cout_0_),
|
||||
.bottom_width_0_height_0_subtile_0__pin_reg_out_0_(bottom_width_0_height_0_subtile_0__pin_reg_out_0_),
|
||||
.bottom_width_0_height_0_subtile_0__pin_sc_out_0_(bottom_width_0_height_0_subtile_0__pin_sc_out_0_),
|
||||
.ccff_tail(ccff_tail),
|
||||
.right_width_0_height_0_subtile_0__pin_O_10_(right_width_0_height_0_subtile_0__pin_O_10_),
|
||||
.right_width_0_height_0_subtile_0__pin_O_11_(right_width_0_height_0_subtile_0__pin_O_11_),
|
||||
|
|
@ -338,6 +337,7 @@ assign test_enable = test_enable_bottom_in;
|
|||
.right_width_0_height_0_subtile_0__pin_O_15_(right_width_0_height_0_subtile_0__pin_O_15_),
|
||||
.right_width_0_height_0_subtile_0__pin_O_8_(right_width_0_height_0_subtile_0__pin_O_8_),
|
||||
.right_width_0_height_0_subtile_0__pin_O_9_(right_width_0_height_0_subtile_0__pin_O_9_),
|
||||
.sc_out(sc_out),
|
||||
.top_width_0_height_0_subtile_0__pin_O_0_(top_width_0_height_0_subtile_0__pin_O_0_),
|
||||
.top_width_0_height_0_subtile_0__pin_O_1_(top_width_0_height_0_subtile_0__pin_O_1_),
|
||||
.top_width_0_height_0_subtile_0__pin_O_2_(top_width_0_height_0_subtile_0__pin_O_2_),
|
||||
|
|
|
|||
|
|
@ -268,11 +268,11 @@ Logic Element (fle) detailed count:
|
|||
LEs used for logic only : 1
|
||||
LEs used for registers only : 0
|
||||
|
||||
Incr Slack updates 1 in 2.269e-06 sec
|
||||
Full Max Req/Worst Slack updates 1 in 1.885e-06 sec
|
||||
Incr Slack updates 1 in 2.486e-06 sec
|
||||
Full Max Req/Worst Slack updates 1 in 1.884e-06 sec
|
||||
Incr Max Req/Worst Slack updates 0 in 0 sec
|
||||
Incr Criticality updates 0 in 0 sec
|
||||
Full Criticality updates 1 in 1.959e-06 sec
|
||||
Full Criticality updates 1 in 2.219e-06 sec
|
||||
Warning 27: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
|
||||
Warning 28: Ambiguous block type specification at grid location (0,9). Existing block type 'io_top' at (0,9) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
|
||||
Warning 29: Ambiguous block type specification at grid location (9,0). Existing block type 'io_bottom' at (9,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
|
||||
|
|
@ -507,11 +507,11 @@ Iter Time pres BBs Heap Re-Rtd Re-Rtd Overused RR Nodes Wireleng
|
|||
(sec) fac Updt push Nets Conns (ns) (ns) (ns) (ns) (ns) Iter
|
||||
---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- --------
|
||||
1 0.0 0.0 0 226 3 3 0 ( 0.000%) 27 ( 0.3%) 13.980 -13.98 -13.980 0.000 0.000 N/A
|
||||
Incr Slack updates 4 in 1.9618e-05 sec
|
||||
Full Max Req/Worst Slack updates 1 in 5.491e-06 sec
|
||||
Incr Max Req/Worst Slack updates 3 in 1.0638e-05 sec
|
||||
Incr Criticality updates 3 in 1.0959e-05 sec
|
||||
Full Criticality updates 1 in 5.516e-06 sec
|
||||
Incr Slack updates 4 in 1.7263e-05 sec
|
||||
Full Max Req/Worst Slack updates 1 in 3.428e-06 sec
|
||||
Incr Max Req/Worst Slack updates 3 in 1.1135e-05 sec
|
||||
Incr Criticality updates 3 in 1.1479e-05 sec
|
||||
Full Criticality updates 1 in 2.542e-06 sec
|
||||
Restoring best routing
|
||||
Critical path: 13.98 ns
|
||||
Successfully routed after 1 routing iterations.
|
||||
|
|
@ -658,11 +658,11 @@ Final setup slack histogram:
|
|||
Final geomean non-virtual intra-domain period: nan ns (nan MHz)
|
||||
Final fanout-weighted geomean non-virtual intra-domain period: nan ns (nan MHz)
|
||||
|
||||
Incr Slack updates 1 in 4.1293e-05 sec
|
||||
Full Max Req/Worst Slack updates 1 in 4.863e-06 sec
|
||||
Incr Slack updates 1 in 2.4791e-05 sec
|
||||
Full Max Req/Worst Slack updates 1 in 7.129e-06 sec
|
||||
Incr Max Req/Worst Slack updates 0 in 0 sec
|
||||
Incr Criticality updates 0 in 0 sec
|
||||
Full Criticality updates 1 in 4.307e-06 sec
|
||||
Full Criticality updates 1 in 6.058e-06 sec
|
||||
--line removed--
|
||||
VPR suceeded
|
||||
--line removed--
|
||||
|
|
@ -992,11 +992,11 @@ Building annotation for post-routing and clustering synchornization results...Do
|
|||
Building annotation for mapped blocks on grid locations...Done
|
||||
User specified the operating clock frequency to use VPR results
|
||||
Use VPR critical path delay 1.6776e-17 [ns] with a 20 [%] slack in OpenFPGA.
|
||||
Incr Slack updates 1 in 1.3184e-05 sec
|
||||
Full Max Req/Worst Slack updates 1 in 4.953e-06 sec
|
||||
Incr Slack updates 1 in 6.81e-06 sec
|
||||
Full Max Req/Worst Slack updates 1 in 4.271e-06 sec
|
||||
Incr Max Req/Worst Slack updates 0 in 0 sec
|
||||
Incr Criticality updates 0 in 0 sec
|
||||
Full Criticality updates 1 in 4.313e-06 sec
|
||||
Full Criticality updates 1 in 4.56e-06 sec
|
||||
Will apply operating clock frequency 59.609 [MHz] to simulations
|
||||
User specified the number of operating clock cycles to be inferred from signal activities
|
||||
Average net density: 0.42
|
||||
|
|
@ -1153,13 +1153,23 @@ Create I/O location mapping for top module
|
|||
Create global port info for top module
|
||||
--line removed--
|
||||
|
||||
Command line to execute: write_fabric_io_info --file --line removed-- --no_time_stamp
|
||||
|
||||
Confirm selected options when call command 'write_fabric_io_info':
|
||||
--file, -f: --line removed--
|
||||
--no_time_stamp: on
|
||||
--verbose: off
|
||||
Warning 56: Directory '/research/ece/lnis/USERS/DARPA_ERI/Tapeout/SOFA/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task' already exists. Will overwrite contents
|
||||
Write fabric I--line removed--'
|
||||
--line removed--
|
||||
|
||||
Command line to execute: write_fabric_hierarchy --file ./fabric_hierarchy.txt
|
||||
|
||||
Confirm selected options when call command 'write_fabric_hierarchy':
|
||||
--file, -f: ./fabric_hierarchy.txt
|
||||
--depth: off
|
||||
--verbose: off
|
||||
Warning 56: Directory '.' already exists. Will overwrite contents
|
||||
Warning 57: Directory '.' already exists. Will overwrite contents
|
||||
Write fabric hierarchy to plain-text file './fabric_hierarchy.txt'
|
||||
--line removed--
|
||||
|
||||
|
|
@ -1208,7 +1218,7 @@ Decoded 35888 configuration bits into 12283 blocks
|
|||
|
||||
Build fabric-independent bitstream for implementation 'top'
|
||||
--line removed--
|
||||
Warning 57: Directory path is empty and nothing will be created.
|
||||
Warning 58: Directory path is empty and nothing will be created.
|
||||
Write 35888 architecture independent bitstream into XML file 'fabric_independent_bitstream.xml'
|
||||
--line removed--
|
||||
|
||||
|
|
@ -1233,7 +1243,7 @@ Confirm selected options when call command 'write_fabric_bitstream':
|
|||
--keep_dont_care_bits: off
|
||||
--no_time_stamp: off
|
||||
--verbose: off
|
||||
Warning 58: Directory path is empty and nothing will be created.
|
||||
Warning 59: Directory path is empty and nothing will be created.
|
||||
Write 35888 fabric bitstream into plain text file 'fabric_bitstream.bit'
|
||||
--line removed--
|
||||
|
||||
|
|
@ -1314,9 +1324,9 @@ Finish execution with 0 errors
|
|||
--line removed--
|
||||
|
||||
Thank you for using OpenFPGA!
|
||||
Incr Slack updates 2 in 1.3959e-05 sec
|
||||
Full Max Req/Worst Slack updates 1 in 5.036e-06 sec
|
||||
Incr Max Req/Worst Slack updates 1 in 6.307e-06 sec
|
||||
Incr Slack updates 2 in 1.0449e-05 sec
|
||||
Full Max Req/Worst Slack updates 1 in 3.365e-06 sec
|
||||
Incr Max Req/Worst Slack updates 1 in 4.4e-06 sec
|
||||
Incr Criticality updates 0 in 0 sec
|
||||
Full Criticality updates 2 in 2.5362e-05 sec
|
||||
Full Criticality updates 2 in 7.422e-06 sec
|
||||
0
|
||||
Loading…
Reference in New Issue