3 Commits

Author	SHA1	Message	Date
tangxifan	3897c18ebe	[HDL] Bug fix in VSS port naming	2020-12-16 13:40:09 -07:00
tangxifan	3b56703c35	[HDL] Add VDD/VSS connects to wrapper netlists	2020-12-16 11:44:40 -07:00
tangxifan	682d15875b	[HDL] Add user project wrapper for post-PnRed FPGA netlists so that we can plug in for Caravel RTL simulation	2020-12-16 11:12:28 -07:00