tangxifan
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22f2b3aa90
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[HDL] Add python script to adapt OpenFPGA MUX primitives to use custom cells
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2020-12-05 21:14:56 -07:00 |
tangxifan
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4875b2de95
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[HDL] Patch pin assignment names to be consistent with post-PnR netlists
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2020-12-02 14:02:18 -07:00 |
Ganesh Gore
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f385c0ca11
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[FPGA1212_v1.1] Added OpenFPGA task and verilog netlist
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2020-12-02 01:43:05 -07:00 |
tangxifan
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a900cba5a5
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[HDL] Bug fix in the pin assignment due to the conflicts on sc_tail and ccff_tail
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2020-11-30 10:29:05 -07:00 |
tangxifan
|
78addbe294
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[HDL] Name fix to be compatible with testbench generation
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2020-11-29 21:01:44 -07:00 |
tangxifan
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fcee5f1c91
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[HDL] Typo fix in pin assignment description
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2020-11-29 18:02:26 -07:00 |
tangxifan
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de5411db6b
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[HDL] Add pin assignement for v1.1 HD FPGA
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2020-11-29 12:58:53 -07:00 |
tangxifan
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cdfa3d5ff4
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[HDL] Update wrapper using the new generator
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2020-11-29 12:47:52 -07:00 |
tangxifan
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d0f9ca718d
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[HDL] bug fix in wrapper line generator
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2020-11-29 12:47:22 -07:00 |
tangxifan
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9f82d9bf54
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[HDL] Correct typo in wrapper generator
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2020-11-29 12:39:56 -07:00 |
tangxifan
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899018d503
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[HDL] Bug fix in wrapper template
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2020-11-29 12:38:25 -07:00 |
tangxifan
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ea758cd5b1
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[HDL] Update wrapper template as most codes can be auto-generated
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2020-11-29 12:36:23 -07:00 |
tangxifan
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f78a53fd03
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[HDL] Add tab to wrapper line generation
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2020-11-29 12:35:24 -07:00 |
tangxifan
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ebd3053a4e
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[HDL] bug fix in wrapper generator
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2020-11-29 12:31:32 -07:00 |
tangxifan
|
0e964534bc
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[HDL] bug fix in wrapper line generator
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2020-11-29 12:01:15 -07:00 |
tangxifan
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9622b44554
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[HDL] Bug fix in JSON file syntax
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2020-11-29 11:59:56 -07:00 |
tangxifan
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27da78fe29
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[HDL] Update wrapper line generator to parse json data
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2020-11-29 11:57:34 -07:00 |
tangxifan
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bc3d839e5b
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[HDL] Upgrading code generator for wrapper
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2020-11-29 10:35:10 -07:00 |
tangxifan
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aac8ddc3ec
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[HDL] update json to ease parsing
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2020-11-28 21:10:46 -07:00 |
tangxifan
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47389a483e
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[HDL] Add json description for pin assignment v1.0
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2020-11-28 20:55:41 -07:00 |
tangxifan
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aff43bf473
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[Doc] Add README to HDL common files
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2020-11-28 17:37:36 -07:00 |
tangxifan
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31dcd4a17f
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[HDL] Add a wrapper for HD MUX2 cell required by carry logic
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2020-11-27 16:01:27 -07:00 |
tangxifan
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b08b77994c
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[HDL] Bug fix in the wrapper generator; now Wishbone clock is wired to a gpio of FPGA
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2020-11-20 18:13:37 -07:00 |
tangxifan
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6fa5e935fa
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[HDL] Update wrapper generator to use tri-state buffer for outputs
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2020-11-19 17:14:50 -07:00 |
tangxifan
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dde0656968
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[HDL] Patch tech mapped netlists of digital I/O and remove the out-of-date behavoiral codes
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2020-11-19 16:31:06 -07:00 |
Ganesh Gore
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37e72cffb5
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[HDL] Updated wrapper generation script
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2020-11-18 23:15:26 -07:00 |
tangxifan
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014a6b56ce
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[HDL] Add clock switch to wrapper
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2020-11-18 20:50:10 -07:00 |
tangxifan
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33824bf179
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[HDL] Update caravel wrapper for new I/O assignment
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2020-11-18 20:44:54 -07:00 |
tangxifan
|
ce91890a0e
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[HDL] Now use a proper drive strength of 4 in the digital I/O cells
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2020-11-18 11:58:21 -07:00 |
tangxifan
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4837e6d424
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[HDL] Remove out-of-data wrapper
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2020-11-18 11:30:53 -07:00 |
tangxifan
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a916ce7e03
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[HDL] Bug fix in the caravel fpga wrapper built with hd cell library
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2020-11-18 11:29:37 -07:00 |
tangxifan
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d36cb8abe7
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[HDL] Add behavoiral and tech-mapped caravel wrapper Verilog codes and code generator script
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2020-11-17 21:44:13 -07:00 |
tangxifan
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58440b8c42
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[HDL] Bug fix in I/O cell
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2020-11-17 20:03:20 -07:00 |
tangxifan
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8803b30b26
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[HDL] Rename por of I/O cell to be consistent with documentation
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2020-11-17 19:33:53 -07:00 |
tangxifan
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5415af07cc
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[HDL] Add digitial I/O with protection circuitry
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2020-11-17 19:17:48 -07:00 |
tangxifan
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625ad5e9c6
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[HDL] Alpha version of behavioral-level Verilog for SoC wrapper
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2020-11-13 18:34:40 -07:00 |
tangxifan
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80655c5869
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[HDL] Digital I/O of embedded FPGA is now lib independent
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2020-11-13 10:00:30 -07:00 |
tangxifan
|
5f02463098
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[HDL] Update wrapper for caravel SoC interface
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2020-11-12 19:06:49 -07:00 |
tangxifan
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ae97e4424d
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[HDL] Add wrapper for Caravel interface
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2020-11-07 22:42:29 -07:00 |
tangxifan
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e952eb951d
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[HDL] Add preprocessing flags for running functional verification
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2020-11-05 11:29:23 -07:00 |
tangxifan
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64d1113461
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[HDL] Add HDL codes for the FPGA I/O cell tuned for Caravel
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2020-11-05 10:18:52 -07:00 |
tangxifan
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12881d7a31
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[HDL] Move verilog wrapper to HDL directory
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2020-11-03 09:19:43 -07:00 |