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348 Commits 16 Branches 1 Tag 1.8 GiB
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4 Commits

Author SHA1 Message Date
Ganesh Gore 7db7c240e3 [FPGA1212_V1] Updated design + Added buffer on IO_EN net + Tie Off floating module inputs + Complete DRC/Timing closed 2020-11-29 10:24:03 -07:00
Ganesh Gore 66d09da857 [FPGA1212_v1] Updated the PostPnR Netlist and PnR Files 2020-11-27 22:11:51 -07:00
Ganesh Gore ce4a6f72f5 [FPGA1212_v1] Updated the task and PrePNR Verilog netlist 2020-11-27 22:08:16 -07:00
Ganesh Gore c54cdcd3ef Added FPGA12x12 with CocoTB tests 2020-11-21 16:07:09 -07:00