riscv
/
SOFA
mirror of https://github.com/lnis-uofu/SOFA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
332 Commits 16 Branches 1 Tag 1.8 GiB
Commit Graph

332 Commits

Author SHA1 Message Date
Laboratory for Nano Integrated Systems (LNIS) 720c65bc7f
Merge pull request #27 from LNIS-Projects/xt_dev 
Fabric Testbenches
 2020-11-18 16:28:24 -07:00
tangxifan f5d18d33ea [Testbench] Add scan-chain testbench for post-pnr verification 2020-11-18 16:23:37 -07:00
tangxifan 2c590e6fb2 [Doc] Fix a typo in the resource count 2020-11-18 16:21:17 -07:00
tangxifan 439c73d211 [Testbench] Add configuration chain test benches for pre- and post- pnr simulation 2020-11-18 15:58:00 -07:00
tangxifan ce91890a0e [HDL] Now use a proper drive strength of 4 in the digital I/O cells 2020-11-18 11:58:21 -07:00
tangxifan 3ae41e2207 [Arch] Double checked I/O default direction set up in OpenFPGA architecture. Add comments for this point 2020-11-18 11:56:22 -07:00
tangxifan ea5c616339 [Doc] Enhance I/O management guidelines 2020-11-18 11:53:37 -07:00
tangxifan da0469728b [Doc] Add guidelines for setting unuses I/Os 2020-11-18 11:50:21 -07:00
Laboratory for Nano Integrated Systems (LNIS) 4badd4dbae
Merge pull request #26 from LNIS-Projects/xt_dev 
Update I/O arrangement for Caravel Project Wrapper
 2020-11-18 11:35:43 -07:00
tangxifan 4837e6d424 [HDL] Remove out-of-data wrapper 2020-11-18 11:30:53 -07:00
tangxifan a916ce7e03 [HDL] Bug fix in the caravel fpga wrapper built with hd cell library 2020-11-18 11:29:37 -07:00
tangxifan d36cb8abe7 [HDL] Add behavoiral and tech-mapped caravel wrapper Verilog codes and code generator script 2020-11-17 21:44:13 -07:00
tangxifan ed98aa27a8 [Doc] Add I/O cell truth table 2020-11-17 21:12:08 -07:00
tangxifan 2b0c5c67e9 [Doc] Update I/O arrangement to be consistent with new arch 2020-11-17 20:45:20 -07:00
Laboratory for Nano Integrated Systems (LNIS) 2fe312258e
Merge pull request #25 from LNIS-Projects/xt_dev 
Create digital I/O Cell with protection circuitry
 2020-11-17 20:11:56 -07:00
tangxifan 58440b8c42 [HDL] Bug fix in I/O cell 2020-11-17 20:03:20 -07:00
tangxifan 1bfc793600 [Arch] Bug fix due to the use of embedded I/O cell 2020-11-17 19:55:04 -07:00
tangxifan 6a27eca809 [Arch] Update arch to use digital I/O circuitry 2020-11-17 19:34:58 -07:00
tangxifan 8803b30b26 [HDL] Rename por of I/O cell to be consistent with documentation 2020-11-17 19:33:53 -07:00
tangxifan b1ce66e8ce [Doc] Update I/O circuitry details 2020-11-17 19:31:04 -07:00
tangxifan 5415af07cc [HDL] Add digitial I/O with protection circuitry 2020-11-17 19:17:48 -07:00
Laboratory for Nano Integrated Systems (LNIS) 6068eb9b01
Merge pull request #24 from LNIS-Projects/xt_dev 
Add Post-PnR Testbench for AND2_LATCH Benchmark
 2020-11-17 17:43:35 -07:00
tangxifan 0681e34a1b [Testbench] Add post PnR testbench for and2_latch benchmark 2020-11-17 17:39:53 -07:00
tangxifan 6cdf477bfc [Doc] Format documentation organization and text 2020-11-17 17:35:07 -07:00
tangxifan b1dc28e605 [Doc] Patch typo in fpga I/O resource overview 2020-11-17 15:32:49 -07:00
Laboratory for Nano Integrated Systems (LNIS) 3c898ae5c8
Merge pull request #23 from LNIS-Projects/xt_dev 
Misc Updates: OpenFPGA scripts, Benchmarks and Architecture
 2020-11-17 15:21:10 -07:00
tangxifan 55db5d5aaf [Arch] Revert to the classical pin location in vpr arch 2020-11-17 15:09:31 -07:00
tangxifan 86bb530709 [Script] Update openfpga task-run script to use the adhoc simulation settings tuned for Caravel SoC 2020-11-17 15:03:10 -07:00
tangxifan cbd9239e41 [Script] Add custom simulation settings for the Skywater 130nm eFPGA fabric 2020-11-17 14:57:23 -07:00
tangxifan a97598cef9 [Script] Patch example openfpga shell script to manage clock routing in VPR 2020-11-17 14:27:14 -07:00
tangxifan 0e2ee8a0cc [Script] Add benchmarks to OpenFPGA task run 2020-11-17 14:01:48 -07:00
tangxifan 75db7b255b [Benchmark] Add micro benchmarks 2020-11-17 13:55:47 -07:00
tangxifan 39aa11c42c [Script] Update OpenFPGA task run configuration for pre-pnr files 2020-11-17 13:46:25 -07:00
tangxifan 804d96bf50 [Testbench] Rename post-pnr testbenches to dedicated directories 2020-11-17 13:45:55 -07:00
tangxifan efda8e0f73 [Script] Update task run configuration in output directory 2020-11-17 13:21:26 -07:00
Laboratory for Nano Integrated Systems (LNIS) ffc072f36e
Merge pull request #22 from LNIS-Projects/xt_dev 
Misc Updates: Architecture, Post-PnR Testbench and Documentation
 2020-11-17 13:13:26 -07:00
tangxifan 0d62af2980 [Doc] Add missing files about clb architecture 2020-11-17 12:04:38 -07:00
tangxifan 22d0aaafeb [Arch] Move global pins to the first of pin list in vpr architecture to ease backend scripts 2020-11-17 11:47:47 -07:00
tangxifan 52076b8714 [Doc] Add detailed architecture schematic 2020-11-17 11:44:57 -07:00
tangxifan a1bb7a3ddc [Testbench] Update testbench for post-pnr 2020-11-17 11:42:35 -07:00
tangxifan 679cb3fea2 [Doc] Minor fix on broken link 2020-11-13 18:47:51 -07:00
Laboratory for Nano Integrated Systems (LNIS) 9932484944
Merge pull request #21 from LNIS-Projects/xt_dev 
Remove Obsolete Architectures and Update Documentation
 2020-11-13 18:45:06 -07:00
tangxifan a2353355ec [Doc] Update figures for I/O resources 2020-11-13 18:36:11 -07:00
tangxifan 625ad5e9c6 [HDL] Alpha version of behavioral-level Verilog for SoC wrapper 2020-11-13 18:34:40 -07:00
tangxifan 46171472a7 [Script] Rename output directory for netlsit generation 2020-11-13 17:47:38 -07:00
tangxifan 290b1f47a0 [Arch] Change I/O density to interface wishbone 2020-11-13 17:44:53 -07:00
tangxifan 8bae6bb893 [Doc] Update documentation about I/O resources 2020-11-13 17:24:43 -07:00
tangxifan 80655c5869 [HDL] Digital I/O of embedded FPGA is now lib independent 2020-11-13 10:00:30 -07:00
tangxifan be33082faf [Arch] Remove out-of-data architectures 2020-11-13 09:50:45 -07:00
tangxifan 6344bb420d [Script] Remove out-of-data task run 2020-11-13 09:47:32 -07:00