9 Commits

Author	SHA1	Message	Date
tangxifan	6e99257bed	[Arch] Now use SuperLUT4 to implement adder LUT functions	2021-05-25 18:19:54 -06:00
tangxifan	77a8a8644a	[Arch] Now use timing variables in the architecture file	2021-05-25 17:11:30 -06:00
tangxifan	2bbce2b92f	[Arch] Update timing for CHD	2021-04-03 17:46:53 -06:00
tangxifan	7d1d6517fb	[Arch] Update timing annotation for LUTs	2021-04-03 14:33:39 -06:00
tangxifan	0838b48dec	[Doc] Add timing and detailed routing arch to documentation	2021-04-02 18:46:43 -06:00
tangxifan	7059c6a014	[Arch] Add timing variables for CHD arch but will update later	2021-04-01 21:05:53 -06:00
tangxifan	36b871bcbb	[Arch] Name change for FF CLK2Q vairable	2021-04-01 21:00:53 -06:00
tangxifan	c9b4699508	[Arch] Add QLSOFA timing at TT corner	2021-04-01 20:59:47 -06:00
tangxifan	f28ff97b8b	[Arch] Move timing values to design variable yml so that we can reuse arch XML to model timing in different corners	2021-04-01 20:28:38 -06:00